r600/llvm: Add instructions for reading thread/group ids

These instructions are only for one dimensional grids.  Instructions
for 2-D and 3-D grids will be added in the future.

7 files changed, 166 insertions, 19 deletions

diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index 384bd814fff..dd458bb27ed 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -24,9 +24,6 @@
  *
  */
 
-
-#include "AMDILSubtarget.h"
-#include "AMDILUtilityFunctions.h"
 #include "AMDGPUISelLowering.h"
 
 using namespace llvm;
@@ -34,12 +31,4 @@ using namespace llvm;
 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
   AMDILTargetLowering(TM)
 {
-  const AMDILSubtarget &STM = TM.getSubtarget<AMDILSubtarget>();
-
-  /* XXX: Not supported yet on R600 */
-  if (STM.device()->getGeneration() > AMDILDeviceInfo::HD6XXX) {
-    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
-  }
-  setOperationAction(ISD::MUL, MVT::i64, Expand);
-  setOperationAction(ISD::BITCAST, MVT::iPTRAny, Legal);
 }
diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
index d2cf5af7cae..8d1bdf54af9 100644
--- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
@@ -32,7 +32,7 @@
 #include "AMDILMCAsmInfo.h"
 #include "AMDILTargetMachine.h"
 #include "AMDGPU.h"
-#include "AMDGPUISelLowering.h"
+#include "R600ISelLowering.h"
 #include "R600InstrInfo.h"
 
 #include "llvm/Analysis/Passes.h"
@@ -40,6 +40,7 @@
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/PassManager.h"
 #include "llvm/Support/TargetRegistry.h"
+#include "llvm/Transforms/IPO.h"
 #include "llvm/Transforms/Scalar.h"
 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
@@ -81,8 +82,9 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
 #endif
 ),
   Subtarget(TT, CPU, FS),
-  TLInfo(*this),
   InstrInfo(new R600InstrInfo(*this)),
+  /* TLInfo uses InstrInfo so it must be initialized after. */
+  TLInfo(*this),
   mGM(new AMDILGlobalManager(0 /* Debug mode */)),
   mKM(new AMDILKernelManager(this, mGM)),
   mDump(false)
diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.h b/src/gallium/drivers/radeon/AMDGPUTargetMachine.h
index 89449cf46cd..64b6402d02f 100644
--- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.h
+++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.h
@@ -31,7 +31,7 @@
 #include "AMDILTargetMachine.h"
 
 #include "AMDGPUInstrInfo.h"
-#include "AMDGPUISelLowering.h"
+#include "R600ISelLowering.h"
 #include "llvm/ADT/OwningPtr.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetData.h"
@@ -52,9 +52,9 @@ MCAsmInfo* createMCAsmInfo(const Target &T, StringRef TT);
 class AMDGPUTargetMachine : public AMDILTargetMachine {
   AMDILSubtarget Subtarget;
 /*   const TargetData DataLayout;
-*/   AMDGPUTargetLowering TLInfo;
-/*   AMDGPUSelectionDAGInfo TSInfo;
+     AMDGPUSelectionDAGInfo TSInfo;
 */   OwningPtr<AMDGPUInstrInfo> InstrInfo;
+     R600TargetLowering TLInfo;
 //   AMDGPUFrameLowering FrameLowering;
      AMDILGlobalManager *mGM;
      AMDILKernelManager *mKM;
@@ -82,8 +82,8 @@ public:
    virtual const AMDGPURegisterInfo *getRegisterInfo() const {
       return &InstrInfo->getRegisterInfo();
    }
-   virtual AMDGPUTargetLowering * getTargetLowering() const {
-      return const_cast<AMDGPUTargetLowering*>(&TLInfo);
+   virtual R600TargetLowering * getTargetLowering() const {
+      return const_cast<R600TargetLowering*>(&TLInfo);
    }
 /*   virtual const AMDGPUSelectionDAGInfo* getSelectionDAGInfo() const {
       return &TSInfo;
diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources
index 00e7c1b4da2..1f18981de7b 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -66,6 +66,7 @@ CPP_SOURCES := \
 	AMDGPUUtil.cpp			\
 	R600CodeEmitter.cpp		\
 	R600InstrInfo.cpp		\
+	R600ISelLowering.cpp	\
 	R600LowerInstructions.cpp	\
 	R600LowerShaderInstructions.cpp	\
 	R600RegisterInfo.cpp		\
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp
new file mode 100644
index 00000000000..031098c9315
--- /dev/null
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors: Tom Stellard <thomas.stellard@amd.com>
+ *
+ */
+
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+
+#include "R600ISelLowering.h"
+#include "R600InstrInfo.h"
+
+using namespace llvm;
+
+R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
+    AMDGPUTargetLowering(TM),
+    TII(static_cast<const R600InstrInfo*>(TM.getInstrInfo()))
+{
+  setOperationAction(ISD::MUL, MVT::i64, Expand);
+}
+
+MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
+    MachineInstr * MI, MachineBasicBlock * BB) const
+{
+  MachineFunction * MF = BB->getParent();
+  MachineRegisterInfo &MRI = MF->getRegInfo();
+
+  switch (MI->getOpcode()) {
+  default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
+  /* XXX: Use helper function from AMDGPULowerShaderInstructions here */
+  case AMDIL::TGID_X:
+    MRI.addLiveIn(AMDIL::T0_X, MI->getOperand(0).getReg());
+    BuildMI(MF->front(), MF->front().begin(), DebugLoc(), TII->get(TargetOpcode::COPY))
+            .addOperand(MI->getOperand(0))
+            .addReg(AMDIL::T1_X);
+    break;
+  case AMDIL::TIDIG_X:
+    MRI.addLiveIn(AMDIL::T1_X, MI->getOperand(0).getReg());
+    BuildMI(MF->front(), MF->front().begin(), DebugLoc(), TII->get(TargetOpcode::COPY))
+            .addOperand(MI->getOperand(0))
+            .addReg(AMDIL::T0_X);
+    break;
+  case AMDIL::NGROUPS_X:
+    lowerNGROUPS(MI, *BB, MRI, 0);
+    break;
+  }
+  MI->eraseFromParent();
+  return BB;
+}
+
+void R600TargetLowering::lowerNGROUPS(MachineInstr *MI, MachineBasicBlock &BB,
+    MachineRegisterInfo & MRI, unsigned dim) const
+{
+  MachineBasicBlock::iterator I = *MI;
+  unsigned offsetReg = MRI.createVirtualRegister(&AMDIL::R600_TReg32_XRegClass);
+  MRI.setRegClass(MI->getOperand(0).getReg(), &AMDIL::R600_TReg32_XRegClass);
+
+  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDIL::MOV), offsetReg)
+          .addReg(AMDIL::ALU_LITERAL_X)
+          .addImm(dim * 4);
+
+  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDIL::VTX_READ_eg))
+          .addOperand(MI->getOperand(0))
+          .addReg(offsetReg)
+          .addImm(0);
+}
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.h b/src/gallium/drivers/radeon/R600ISelLowering.h
new file mode 100644
index 00000000000..389c6e36302
--- /dev/null
+++ b/src/gallium/drivers/radeon/R600ISelLowering.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors: Tom Stellard <thomas.stellard@amd.com>
+ *
+ */
+
+#ifndef R600ISELLOWERING_H
+#define R600ISELLOWERING_H
+
+#include "AMDGPUISelLowering.h"
+
+namespace llvm {
+
+class R600InstrInfo;
+
+class R600TargetLowering : public AMDGPUTargetLowering
+{
+public:
+  R600TargetLowering(TargetMachine &TM);
+  virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI,
+      MachineBasicBlock * BB) const;
+
+private:
+  const R600InstrInfo * TII;
+
+  void lowerNGROUPS(MachineInstr *MI, MachineBasicBlock &BB,
+      MachineRegisterInfo & MRI, unsigned dim) const;
+
+};
+
+} // End namespace llvm;
+
+#endif // R600ISELLOWERING_H
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index 40356a81432..f9b8e4a1201 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -876,7 +876,24 @@ let isCodeGenOnly = 1 in {
     [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
   >;
 
-}
+let usesCustomInserter = 1, isPseudo = 1 in {
+
+class R600PreloadInst <string asm, Intrinsic intr> : AMDGPUInst <
+  (outs R600_TReg32:$dst),
+  (ins),
+  asm,
+  [(set R600_TReg32:$dst, (intr))]
+>;
+
+def TGID_X : R600PreloadInst <"TGID_X", int_r600_read_tgid_x>;
+def TIDIG_X : R600PreloadInst <"TIDIG_X", int_r600_read_tidig_x>;
+def NGROUPS_X : R600PreloadInst <"NGROUPS_X", int_r600_read_ngroups_x>;
+
+} // End usesCustomInserter = 1, isPseudo = 1
+
+} // End isCodeGenOnly = 1
+
+
 
 include "R600ShaderPatterns.td"