~tstellar/llvm - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2012-11-08	R600: Support for indirect addressingindirect-wip-2	Tom Stellard	17	-8/+464
2012-11-08	ADMGPU: Add helper function for setting instructions modifiers	Tom Stellard	3	-9/+16
2012-10-31	SI: Enable control flow pass again	tstellar	1	-2/+1
2012-10-31	SI: Handle kilp intrinsic	tstellar	1	-0/+5
2012-10-31	SI: Use SReg_1 class for SI_IF_(N)Z condition code operand	tstellar	1	-3/+3
2012-10-31	SI: Prevent instructions modifying the EXEC register from being moved	tstellar	2	-0/+6
2012-10-31	SI: Handle more cases in copyPhysReg callback	tstellar	1	-3/+15
2012-10-31	SI: Alternative handling of EXEC register for control flow	tstellar	2	-26/+36
2012-10-31	SI: Use SReg_64RegClass for i64 register class	tstellar	1	-1/+1
2012-10-31	R600: use specialised R600.store.pixel.* for fragment shader	tstellar	8	-2/+185
2012-10-26	R600: Add a v4f32 to v4i32 BitConvert pattern	tstellar	1	-0/+1
2012-10-26	R600: Set isBarrier bit for JUMP instruction	tstellar	1	-2/+2
2012-10-25	SI: Add intrinsic for reading the FRONT_FACE VGPR.	tstellar	2	-0/+6
2012-10-25	SI: Use 64-bit encoding for V_CMP instructions	tstellar	6	-51/+155
2012-10-22	R600: Cayman uses vector instruction for SIN/COS/RECIP_CLAMPED_RECIPSQRT_IEEE	tstellar	1	-10/+20
2012-10-22	R600: turn select into select_cc	tstellar	2	-0/+17
2012-10-22	R600: add support for vector setCC	tstellar	1	-4/+2
2012-10-22	R600: Remove input.face and input.position intrinsics	tstellar	3	-40/+0
2012-10-22	R600: Add super reg to reserved reg list	tstellar	1	-0/+3
2012-10-22	R600: interp instructions emits native outputs	tstellar	3	-38/+27
2012-10-22	R600: Fix llvm.pow.ll test	tstellar	1	-1/+1
2012-10-22	AMDGPU: Fix build after merge	tstellar	1	-1/+1
2012-10-22	Merge master branch	tstellar	164	-783/+5586
2012-10-19	R600: Remove deprecated code from R600MCCodeEmitter	tstellar	1	-129/+9
2012-10-19	R600: Use native operands for KILLGT instruction	tstellar	4	-38/+29
2012-10-19	R600: Use native operands for CUBE, DOT4 instructions	tstellar	3	-68/+46
2012-10-19	R600: Organize pseudo instruction in R600Instructions.td	tstellar	1	-27/+10
2012-10-19	R600: Add support for the AMDGPU::BREAK instruction	tstellar	1	-1/+17
2012-10-19	R600: Lower PRED_X to a native instruction prior to codegen	tstellar	9	-50/+111
2012-10-19	R600: Use native operands for R600_OP3 instructions	tstellar	1	-34/+64
2012-10-19	R600: Use native operands for R600_2OP instructions	tstellar	4	-123/+79
2012-10-19	R600: Use native operands for MOV_IMM_* instructions	tstellar	4	-23/+42
2012-10-19	R600: Use native operands for the MOV Instruction	tstellar	7	-47/+60
2012-10-19	R600: Use native operands for R600_1OP instructions	tstellar	9	-140/+469
2012-10-19	R600: Emit CONTINUE instructions correctly	tstellar	1	-3/+2
2012-10-19	R600: Prevent the CFG Structurizer from emitting extra ENDIFs	tstellar	1	-1/+0
2012-10-19	AMDGPU: Remove unused llvm.AMDGPU.ssg intrinsic	tstellar	2	-8/+0
2012-10-19	R600: Fix DIV_Common pattern use	tstellar	1	-1/+3
2012-10-19	R600: Set FlagOperandIdx for RECIP_IEEE	tstellar	1	-5/+5
2012-10-19	R600: Cayman now uses vector version of EXP_IEEE, LOG_IEEE and RECIPSQRT_CLAMPED	tstellar	1	-9/+19
2012-10-19	R600: Lower fpow(A, B) to fexp(mul(B, flog(A))) at DAG level	tstellar	3	-2/+13
2012-10-16	AMDGPU: Fix build after merge	tstellar	1	-8/+0
2012-10-16	Merge master branch	tstellar	381	-4194/+18653
2012-10-15	R600: use ceil intrinsic instead of llvm.AMDIL.round.posinf	tstellar	2	-4/+0
2012-10-15	R600: use floor intrinsic instead of llvm.AMDIL.floor	tstellar	5	-5/+5
2012-10-15	R600: use llvm fabs intrinsic	tstellar	3	-5/+3
2012-10-15	R600: use llvm intrinsic for flog2	tstellar	3	-3/+2
2012-10-15	R600: add support for cos/sin intrinsic	tstellar	4	-14/+17
2012-10-15	R600: add a pattern for fsqrt	tstellar	1	-0/+3
2012-10-15	R600: Store channel index in the register's HWEncoding field	tstellar	8	-1117/+31