diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2015-01-07 15:50:35 -0500 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-01-07 15:51:29 -0500 |
| commit | 3e281174d4aa422a8c823f179b4e2f76bccdadbf (patch) | |
| tree | 5f87ff3245863b65216402b67def84d644758c14 | |
| parent | 09f880e1b00b48804c96804baf1f339bb18f14b1 (diff) | |
R600/SI: Fix a few bugs in VGPR spilling
| -rw-r--r-- | lib/Target/R600/SIPrepareScratchRegs.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/lib/Target/R600/SIPrepareScratchRegs.cpp b/lib/Target/R600/SIPrepareScratchRegs.cpp index 888e9704665..ea505a1ca9c 100644 --- a/lib/Target/R600/SIPrepareScratchRegs.cpp +++ b/lib/Target/R600/SIPrepareScratchRegs.cpp @@ -115,6 +115,10 @@ bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) { BI != BE; ++BI) { MachineBasicBlock &MBB = *BI; + // Add the scratch offset reg as a live-in so that the register scavenger + // doesn't re-use it. + if (!MBB.isLiveIn(ScratchOffsetReg)) + MBB.addLiveIn(ScratchOffsetReg); RS.enterBasicBlock(&MBB); for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); @@ -146,7 +150,7 @@ bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) { unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2); - unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2); + unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3); BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc0) .addExternalSymbol("SCRATCH_RSRC_DWORD0") |