diff options
author | Tom Stellard <thomas.stellard@amd.com> | 2013-06-12 09:02:39 -0700 |
---|---|---|
committer | Tom Stellard <thomas.stellard@amd.com> | 2013-06-17 09:12:26 -0700 |
commit | 0d16b1e06c6d5e2fc06721e92a5c9a11772b73b1 (patch) | |
tree | c5a4fa342d791a9a2cc42b46476578ff369f7754 | |
parent | a4a1eae870d3247dc3357cbbfc68ea7dbe810e50 (diff) |
R600: Add ALUInst bit to tablegen definitions v2
v2:
- Remove functions left over from a previous rebase.
-rw-r--r-- | lib/Target/R600/R600Defines.h | 3 | ||||
-rw-r--r-- | lib/Target/R600/R600InstrFormats.td | 2 | ||||
-rw-r--r-- | lib/Target/R600/R600InstrInfo.cpp | 4 | ||||
-rw-r--r-- | lib/Target/R600/R600Instructions.td | 3 |
4 files changed, 8 insertions, 4 deletions
diff --git a/lib/Target/R600/R600Defines.h b/lib/Target/R600/R600Defines.h index e30ea27daa9..6bcf8aefa74 100644 --- a/lib/Target/R600/R600Defines.h +++ b/lib/Target/R600/R600Defines.h @@ -41,7 +41,8 @@ namespace R600_InstFlag { OP1 = (1 << 10), OP2 = (1 << 11), VTX_INST = (1 << 12), - TEX_INST = (1 << 13) + TEX_INST = (1 << 13), + ALU_INST = (1 << 14) }; } diff --git a/lib/Target/R600/R600InstrFormats.td b/lib/Target/R600/R600InstrFormats.td index d31f18cb47b..2c98fb90db5 100644 --- a/lib/Target/R600/R600InstrFormats.td +++ b/lib/Target/R600/R600InstrFormats.td @@ -26,6 +26,7 @@ class InstR600 <dag outs, dag ins, string asm, list<dag> pattern, bit HasNativeOperands = 0; bit VTXInst = 0; bit TEXInst = 0; + bit ALUInst = 0; let Namespace = "AMDGPU"; let OutOperandList = outs; @@ -47,6 +48,7 @@ class InstR600 <dag outs, dag ins, string asm, list<dag> pattern, let TSFlags{11} = Op2; let TSFlags{12} = VTXInst; let TSFlags{13} = TEXInst; + let TSFlags{14} = ALUInst; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/R600/R600InstrInfo.cpp b/lib/Target/R600/R600InstrInfo.cpp index b9da74c4d8d..adfe144a267 100644 --- a/lib/Target/R600/R600InstrInfo.cpp +++ b/lib/Target/R600/R600InstrInfo.cpp @@ -133,9 +133,7 @@ bool R600InstrInfo::isCubeOp(unsigned Opcode) const { bool R600InstrInfo::isALUInstr(unsigned Opcode) const { unsigned TargetFlags = get(Opcode).TSFlags; - return ((TargetFlags & R600_InstFlag::OP1) | - (TargetFlags & R600_InstFlag::OP2) | - (TargetFlags & R600_InstFlag::OP3)); + return (TargetFlags & R600_InstFlag::ALU_INST); } bool R600InstrInfo::isTransOnly(unsigned Opcode) const { diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td index 27b0214b009..31e103d6391 100644 --- a/lib/Target/R600/R600Instructions.td +++ b/lib/Target/R600/R600Instructions.td @@ -114,6 +114,7 @@ class R600_1OP <bits<11> inst, string opName, list<dag> pattern, let update_pred = 0; let HasNativeOperands = 1; let Op1 = 1; + let ALUInst = 1; let DisableEncoding = "$literal"; let Inst{31-0} = Word0; @@ -150,6 +151,7 @@ class R600_2OP <bits<11> inst, string opName, list<dag> pattern, let HasNativeOperands = 1; let Op2 = 1; + let ALUInst = 1; let DisableEncoding = "$literal"; let Inst{31-0} = Word0; @@ -190,6 +192,7 @@ class R600_3OP <bits<5> inst, string opName, list<dag> pattern, let HasNativeOperands = 1; let DisableEncoding = "$literal"; let Op3 = 1; + let ALUInst = 1; let Inst{31-0} = Word0; let Inst{63-32} = Word1; |