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author | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2018-04-18 22:35:28 -0400 |
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committer | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2018-04-18 22:36:27 -0400 |
commit | a4d33053ca1102f44be55dee34f45102d3915d18 (patch) | |
tree | 7cab8dff584152d098c89f1eef90ee54939ba830 | |
parent | b405f227d06d847560cde246976bbd9fee93db4d (diff) |
bti flush
-rw-r--r-- | src/mesa/drivers/dri/i965/genX_blorp_exec.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c index b72ca9c515..581438966e 100644 --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c @@ -241,6 +241,20 @@ genX(blorp_exec)(struct blorp_batch *batch, struct gl_context *ctx = &brw->ctx; bool check_aperture_failed_once = false; +#if GEN_GEN >= 11 + /* The PIPE_CONTROL command description says: + * + * "Whenever a Binding Table Index (BTI) used by a Render Taget Message + * points to a different RENDER_SURFACE_STATE, SW must issue a Render + * Target Cache Flush by enabling this bit. When render target flush + * is set due to new association of BTI, PS Scoreboard Stall bit must + * be set in this packet." + */ + brw_emit_pipe_control_flush(brw, + PIPE_CONTROL_RENDER_TARGET_FLUSH | + PIPE_CONTROL_STALL_AT_SCOREBOARD); +#endif + /* Flush the sampler and render caches. We definitely need to flush the * sampler cache so that we get updated contents from the render cache for * the glBlitFramebuffer() source. Also, we are sometimes warned in the |