i965: Port gen6+ 3DSTATE_WM to genxml.

Emit 3DSTATE_WM on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Use render_bo helper to setup brw_address (Kristian)
   - Remove TODO and use BRW_PSCDEPTH_OFF.
v3:
   - A couple of style fixes (Ken)
   - Enable RASTRULE_UPPER_RIGHT on gen6+ instead of gen8+ (Ken)

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

6 files changed, 185 insertions, 435 deletions

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index bfcf57cbbf..da09df83a1 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -101,7 +101,6 @@ i965_FILES = \
 	gen7_urb.c \
 	gen7_viewport_state.c \
 	gen7_vs_state.c \
-	gen7_wm_state.c \
 	gen7_wm_surface_state.c \
 	gen8_blend_state.c \
 	gen8_depth_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index c55c1752a3..5010237bf0 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -125,7 +125,6 @@ extern const struct brw_tracked_state gen6_viewport_state;
 extern const struct brw_tracked_state gen6_vs_push_constants;
 extern const struct brw_tracked_state gen6_vs_state;
 extern const struct brw_tracked_state gen6_wm_push_constants;
-extern const struct brw_tracked_state gen6_wm_state;
 extern const struct brw_tracked_state gen7_depthbuffer;
 extern const struct brw_tracked_state gen7_ds_state;
 extern const struct brw_tracked_state gen7_gs_state;
@@ -138,7 +137,6 @@ extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state gen7_vs_state;
-extern const struct brw_tracked_state gen7_wm_state;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_blend_state;
 extern const struct brw_tracked_state gen8_ds_state;
@@ -149,7 +147,6 @@ extern const struct brw_tracked_state gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
-extern const struct brw_tracked_state gen8_wm_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
@@ -320,17 +317,6 @@ void brw_emit_sampler_state(struct brw_context *brw,
                             bool non_normalized_coordinates,
                             uint32_t border_color_offset);
 
-/* gen6_wm_state.c */
-void
-gen6_upload_wm_state(struct brw_context *brw,
-                     const struct brw_wm_prog_data *prog_data,
-                     const struct brw_stage_state *stage_state,
-                     bool multisampled_fbo,
-                     bool dual_source_blend_enable, bool kill_enable,
-                     bool color_buffer_write_enable, bool msaa_enabled,
-                     bool line_stipple_enable, bool polygon_stipple_enable,
-                     bool statistic_enable);
-
 /* gen6_surface_state.c */
 void gen6_init_vtable_surface_functions(struct brw_context *brw);
 
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 2fb2a33385..9da1bddb1c 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -68,224 +68,3 @@ const struct brw_tracked_state gen6_wm_push_constants = {
    },
    .emit = gen6_upload_wm_push_constants,
 };
-
-void
-gen6_upload_wm_state(struct brw_context *brw,
-                     const struct brw_wm_prog_data *prog_data,
-                     const struct brw_stage_state *stage_state,
-                     bool multisampled_fbo,
-                     bool dual_source_blend_enable, bool kill_enable,
-                     bool color_buffer_write_enable, bool msaa_enabled,
-                     bool line_stipple_enable, bool polygon_stipple_enable,
-                     bool statistic_enable)
-{
-   const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   uint32_t dw2, dw4, dw5, dw6, ksp0, ksp2;
-
-   /* We can't fold this into gen6_upload_wm_push_constants(), because
-    * according to the SNB PRM, vol 2 part 1 section 7.2.2
-    * (3DSTATE_CONSTANT_PS [DevSNB]):
-    *
-    *     "[DevSNB]: This packet must be followed by WM_STATE."
-    */
-   if (prog_data->base.nr_params == 0) {
-      /* Disable the push constant buffers. */
-      BEGIN_BATCH(5);
-      OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      ADVANCE_BATCH();
-   } else {
-      BEGIN_BATCH(5);
-      OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
-		GEN6_CONSTANT_BUFFER_0_ENABLE |
-		(5 - 2));
-      /* Pointer to the WM constant buffer.  Covered by the set of
-       * state flags from gen6_upload_wm_push_constants.
-       */
-      OUT_BATCH(stage_state->push_const_offset +
-                stage_state->push_const_size - 1);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      ADVANCE_BATCH();
-   }
-
-   dw2 = dw4 = dw5 = dw6 = ksp2 = 0;
-
-   if (statistic_enable)
-      dw4 |= GEN6_WM_STATISTICS_ENABLE;
-
-   dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
-   dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
-
-   if (prog_data->base.use_alt_mode)
-      dw2 |= GEN6_WM_FLOATING_POINT_MODE_ALT;
-
-   dw2 |= (ALIGN(stage_state->sampler_count, 4) / 4) <<
-           GEN6_WM_SAMPLER_COUNT_SHIFT;
-
-   dw2 |= ((prog_data->base.binding_table.size_bytes / 4) <<
-           GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT);
-
-   dw5 |= (devinfo->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
-
-   if (prog_data->dispatch_8)
-      dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
-
-   if (prog_data->dispatch_16)
-      dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
-
-   dw4 |= prog_data->base.dispatch_grf_start_reg <<
-          GEN6_WM_DISPATCH_START_GRF_SHIFT_0;
-   dw4 |= prog_data->dispatch_grf_start_reg_2 <<
-          GEN6_WM_DISPATCH_START_GRF_SHIFT_2;
-
-   ksp0 = stage_state->prog_offset;
-   ksp2 = stage_state->prog_offset + prog_data->prog_offset_2;
-
-   if (dual_source_blend_enable)
-      dw5 |= GEN6_WM_DUAL_SOURCE_BLEND_ENABLE;
-
-   if (line_stipple_enable)
-      dw5 |= GEN6_WM_LINE_STIPPLE_ENABLE;
-
-   if (polygon_stipple_enable)
-      dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
-
-   if (prog_data->uses_src_depth)
-      dw5 |= GEN6_WM_USES_SOURCE_DEPTH;
-   if (prog_data->uses_src_w)
-      dw5 |= GEN6_WM_USES_SOURCE_W;
-   if (prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF)
-      dw5 |= GEN6_WM_COMPUTED_DEPTH;
-   dw6 |= prog_data->barycentric_interp_modes <<
-      GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
-
-   if (kill_enable)
-      dw5 |= GEN6_WM_KILL_ENABLE;
-
-   if (color_buffer_write_enable ||
-       dw5 & (GEN6_WM_KILL_ENABLE | GEN6_WM_COMPUTED_DEPTH))
-      dw5 |= GEN6_WM_DISPATCH_ENABLE;
-
-   /* From the SNB PRM, volume 2 part 1, page 278:
-    * "This bit is inserted in the PS payload header and made available to
-    * the DataPort (either via the message header or via header bypass) to
-    * indicate that oMask data (one or two phases) is included in Render
-    * Target Write messages. If present, the oMask data is used to mask off
-    * samples."
-    */
-    if (prog_data->uses_omask)
-      dw5 |= GEN6_WM_OMASK_TO_RENDER_TARGET;
-
-   dw6 |= prog_data->num_varying_inputs <<
-      GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
-   if (multisampled_fbo) {
-      if (msaa_enabled)
-         dw6 |= GEN6_WM_MSRAST_ON_PATTERN;
-      else
-         dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
-
-      if (prog_data->persample_dispatch)
-         dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
-      else {
-         dw6 |= GEN6_WM_MSDISPMODE_PERPIXEL;
-      }
-   } else {
-      dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
-      dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
-   }
-
-   dw6 |= GEN6_WM_POINT_RASTRULE_UPPER_RIGHT;
-
-   /* From the SNB PRM, volume 2 part 1, page 281:
-    * "If the PS kernel does not need the Position XY Offsets
-    * to compute a Position XY value, then this field should be
-    * programmed to POSOFFSET_NONE."
-    *
-    * "SW Recommendation: If the PS kernel needs the Position Offsets
-    * to compute a Position XY value, this field should match Position
-    * ZW Interpolation Mode to ensure a consistent position.xyzw
-    * computation."
-    * We only require XY sample offsets. So, this recommendation doesn't
-    * look useful at the moment. We might need this in future.
-    */
-   if (prog_data->uses_pos_offset)
-      dw6 |= GEN6_WM_POSOFFSET_SAMPLE;
-   else
-      dw6 |= GEN6_WM_POSOFFSET_NONE;
-
-   BEGIN_BATCH(9);
-   OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
-   OUT_BATCH(ksp0);
-   OUT_BATCH(dw2);
-   if (prog_data->base.total_scratch) {
-      OUT_RELOC(stage_state->scratch_bo,
-                I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-		ffs(stage_state->per_thread_scratch) - 11);
-   } else {
-      OUT_BATCH(0);
-   }
-   OUT_BATCH(dw4);
-   OUT_BATCH(dw5);
-   OUT_BATCH(dw6);
-   OUT_BATCH(0); /* kernel 1 pointer */
-   OUT_BATCH(ksp2);
-   ADVANCE_BATCH();
-}
-
-static void
-upload_wm_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = &brw->ctx;
-   /* BRW_NEW_FS_PROG_DATA */
-   const struct brw_wm_prog_data *prog_data =
-      brw_wm_prog_data(brw->wm.base.prog_data);
-
-   /* _NEW_BUFFERS */
-   const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1;
-
-   /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */
-   const bool dual_src_blend_enable = prog_data->dual_src_blend &&
-                                      (ctx->Color.BlendEnabled & 1) &&
-                                      ctx->Color.Blend[0]._UsesDualSrc;
-
-   /* _NEW_COLOR, _NEW_MULTISAMPLE _NEW_BUFFERS */
-   const bool kill_enable = prog_data->uses_kill ||
-                            _mesa_is_alpha_test_enabled(ctx) ||
-                            _mesa_is_alpha_to_coverage_enabled(ctx) ||
-                            prog_data->uses_omask;
-
-   /* Rendering against the gl-context is always taken into account. */
-   const bool statistic_enable = true;
-
-   /* _NEW_LINE | _NEW_POLYGON | _NEW_BUFFERS | _NEW_COLOR |
-    * _NEW_MULTISAMPLE
-    */
-   gen6_upload_wm_state(brw, prog_data, &brw->wm.base,
-                        multisampled_fbo,
-                        dual_src_blend_enable, kill_enable,
-                        brw_color_buffer_write_enabled(brw),
-                        ctx->Multisample.Enabled,
-                        ctx->Line.StippleFlag, ctx->Polygon.StippleFlag,
-                        statistic_enable);
-}
-
-const struct brw_tracked_state gen6_wm_state = {
-   .dirty = {
-      .mesa  = _NEW_BUFFERS |
-               _NEW_COLOR |
-               _NEW_LINE |
-               _NEW_MULTISAMPLE |
-               _NEW_POLYGON |
-               _NEW_PROGRAM_CONSTANTS,
-      .brw   = BRW_NEW_BATCH |
-               BRW_NEW_BLORP |
-               BRW_NEW_FS_PROG_DATA |
-               BRW_NEW_PUSH_CONSTANT_ALLOCATION,
-   },
-   .emit = upload_wm_state,
-};
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
deleted file mode 100644
index 3173035f1c..0000000000
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright © 2011 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include <stdbool.h>
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "compiler/brw_eu_defines.h"
-#include "brw_util.h"
-#include "brw_wm.h"
-#include "program/program.h"
-#include "program/prog_parameter.h"
-#include "program/prog_statevars.h"
-#include "main/framebuffer.h"
-#include "intel_batchbuffer.h"
-
-static void
-upload_wm_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = &brw->ctx;
-   /* BRW_NEW_FS_PROG_DATA */
-   const struct brw_wm_prog_data *prog_data =
-      brw_wm_prog_data(brw->wm.base.prog_data);
-   bool writes_depth = prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
-   uint32_t dw1, dw2;
-
-   /* _NEW_BUFFERS */
-   const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1;
-
-   dw1 = dw2 = 0;
-   dw1 |= GEN7_WM_STATISTICS_ENABLE;
-   dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
-   dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
-   dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
-
-   /* _NEW_LINE */
-   if (ctx->Line.StippleFlag)
-      dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
-
-   /* _NEW_POLYGON */
-   if (ctx->Polygon.StippleFlag)
-      dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
-
-   if (prog_data->uses_src_depth)
-      dw1 |= GEN7_WM_USES_SOURCE_DEPTH;
-
-   if (prog_data->uses_src_w)
-      dw1 |= GEN7_WM_USES_SOURCE_W;
-
-   dw1 |= prog_data->computed_depth_mode << GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT;
-   dw1 |= prog_data->barycentric_interp_modes <<
-      GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
-
-   /* _NEW_COLOR, _NEW_MULTISAMPLE _NEW_BUFFERS */
-   /* Enable if the pixel shader kernel generates and outputs oMask.
-    */
-   if (prog_data->uses_kill ||
-       _mesa_is_alpha_test_enabled(ctx) ||
-       _mesa_is_alpha_to_coverage_enabled(ctx) ||
-       prog_data->uses_omask) {
-      dw1 |= GEN7_WM_KILL_ENABLE;
-   }
-
-   /* _NEW_BUFFERS | _NEW_COLOR */
-   if (brw_color_buffer_write_enabled(brw) || writes_depth ||
-       prog_data->has_side_effects || dw1 & GEN7_WM_KILL_ENABLE) {
-      dw1 |= GEN7_WM_DISPATCH_ENABLE;
-   }
-   if (multisampled_fbo) {
-      /* _NEW_MULTISAMPLE */
-      if (ctx->Multisample.Enabled)
-         dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
-      else
-         dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
-
-      if (prog_data->persample_dispatch)
-         dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
-      else
-         dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
-   } else {
-      dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
-      dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
-   }
-
-   if (prog_data->uses_sample_mask) {
-      dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK;
-   }
-
-   /* BRW_NEW_FS_PROG_DATA */
-   if (prog_data->early_fragment_tests)
-      dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
-   else if (prog_data->has_side_effects)
-      dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
-
-   /* The "UAV access enable" bits are unnecessary on HSW because they only
-    * seem to have an effect on the HW-assisted coherency mechanism which we
-    * don't need, and the rasterization-related UAV_ONLY flag and the
-    * DISPATCH_ENABLE bit can be set independently from it.
-    * C.f. gen8_upload_ps_extra().
-    *
-    * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS | _NEW_COLOR
-    */
-   if (brw->is_haswell &&
-       !(brw_color_buffer_write_enabled(brw) || writes_depth) &&
-       prog_data->has_side_effects)
-      dw2 |= HSW_WM_UAV_ONLY;
-
-   BEGIN_BATCH(3);
-   OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
-   OUT_BATCH(dw1);
-   OUT_BATCH(dw2);
-   ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state gen7_wm_state = {
-   .dirty = {
-      .mesa  = _NEW_BUFFERS |
-               _NEW_COLOR |
-               _NEW_LINE |
-               _NEW_MULTISAMPLE |
-               _NEW_POLYGON,
-      .brw   = BRW_NEW_BATCH |
-               BRW_NEW_BLORP |
-               BRW_NEW_FS_PROG_DATA,
-   },
-   .emit = upload_wm_state,
-};
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 581aa54c90..1a4a680999 100644
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -136,52 +136,3 @@ const struct brw_tracked_state gen8_ps_extra = {
    },
    .emit = upload_ps_extra,
 };
-
-static void
-upload_wm_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = &brw->ctx;
-   uint32_t dw1 = 0;
-
-   /* BRW_NEW_FS_PROG_DATA */
-   const struct brw_wm_prog_data *wm_prog_data =
-      brw_wm_prog_data(brw->wm.base.prog_data);
-
-   dw1 |= GEN7_WM_STATISTICS_ENABLE;
-   dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
-   dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
-   dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
-
-   /* _NEW_LINE */
-   if (ctx->Line.StippleFlag)
-      dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
-
-   /* _NEW_POLYGON */
-   if (ctx->Polygon.StippleFlag)
-      dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
-
-   dw1 |= wm_prog_data->barycentric_interp_modes <<
-      GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
-
-   /* BRW_NEW_FS_PROG_DATA */
-   if (wm_prog_data->early_fragment_tests)
-      dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
-   else if (wm_prog_data->has_side_effects)
-      dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
-
-   BEGIN_BATCH(2);
-   OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
-   OUT_BATCH(dw1);
-   ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state gen8_wm_state = {
-   .dirty = {
-      .mesa  = _NEW_LINE |
-               _NEW_POLYGON,
-      .brw   = BRW_NEW_BLORP |
-               BRW_NEW_CONTEXT |
-               BRW_NEW_FS_PROG_DATA,
-   },
-   .emit = upload_wm_state,
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 09537c3e58..8ccad9ee2f 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -28,6 +28,7 @@
 
 #include "brw_context.h"
 #include "brw_state.h"
+#include "brw_wm.h"
 #include "brw_util.h"
 
 #include "intel_batchbuffer.h"
@@ -772,6 +773,187 @@ static const struct brw_tracked_state genX(sf_state) = {
    .emit = genX(upload_sf),
 };
 
+/* ---------------------------------------------------------------------- */
+
+static void
+genX(upload_wm)(struct brw_context *brw)
+{
+   struct gl_context *ctx = &brw->ctx;
+
+   /* BRW_NEW_FS_PROG_DATA */
+   const struct brw_wm_prog_data *wm_prog_data =
+      brw_wm_prog_data(brw->wm.base.prog_data);
+
+   UNUSED bool writes_depth =
+      wm_prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
+
+#if GEN_GEN < 7
+   const struct brw_stage_state *stage_state = &brw->wm.base;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
+
+   /* We can't fold this into gen6_upload_wm_push_constants(), because
+    * according to the SNB PRM, vol 2 part 1 section 7.2.2
+    * (3DSTATE_CONSTANT_PS [DevSNB]):
+    *
+    *     "[DevSNB]: This packet must be followed by WM_STATE."
+    */
+   brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_PS), wmcp) {
+      if (wm_prog_data->base.nr_params != 0) {
+         wmcp.Buffer0Valid = true;
+         /* Pointer to the WM constant buffer.  Covered by the set of
+          * state flags from gen6_upload_wm_push_constants.
+          */
+         wmcp.PointertoPSConstantBuffer0 = stage_state->push_const_offset;
+         wmcp.PSConstantBuffer0ReadLength = stage_state->push_const_size - 1;
+      }
+   }
+#endif
+
+   brw_batch_emit(brw, GENX(3DSTATE_WM), wm) {
+      wm.StatisticsEnable = true;
+      wm.LineAntialiasingRegionWidth = _10pixels;
+      wm.LineEndCapAntialiasingRegionWidth = _05pixels;
+
+#if GEN_GEN < 7
+      if (wm_prog_data->base.use_alt_mode)
+         wm.FloatingPointMode = Alternate;
+
+      wm.SamplerCount = DIV_ROUND_UP(stage_state->sampler_count, 4);
+      wm.BindingTableEntryCount = wm_prog_data->base.binding_table.size_bytes / 4;
+      wm.MaximumNumberofThreads = devinfo->max_wm_threads - 1;
+      wm._8PixelDispatchEnable = wm_prog_data->dispatch_8;
+      wm._16PixelDispatchEnable = wm_prog_data->dispatch_16;
+      wm.DispatchGRFStartRegisterForConstantSetupData0 =
+         wm_prog_data->base.dispatch_grf_start_reg;
+      wm.DispatchGRFStartRegisterForConstantSetupData2 =
+         wm_prog_data->dispatch_grf_start_reg_2;
+      wm.KernelStartPointer0 = stage_state->prog_offset;
+      wm.KernelStartPointer2 = stage_state->prog_offset +
+         wm_prog_data->prog_offset_2;
+      wm.DualSourceBlendEnable =
+         wm_prog_data->dual_src_blend && (ctx->Color.BlendEnabled & 1) &&
+         ctx->Color.Blend[0]._UsesDualSrc;
+      wm.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask;
+      wm.NumberofSFOutputAttributes = wm_prog_data->num_varying_inputs;
+
+      /* From the SNB PRM, volume 2 part 1, page 281:
+       * "If the PS kernel does not need the Position XY Offsets
+       * to compute a Position XY value, then this field should be
+       * programmed to POSOFFSET_NONE."
+       *
+       * "SW Recommendation: If the PS kernel needs the Position Offsets
+       * to compute a Position XY value, this field should match Position
+       * ZW Interpolation Mode to ensure a consistent position.xyzw
+       * computation."
+       * We only require XY sample offsets. So, this recommendation doesn't
+       * look useful at the moment. We might need this in future.
+       */
+      if (wm_prog_data->uses_pos_offset)
+         wm.PositionXYOffsetSelect = POSOFFSET_SAMPLE;
+      else
+         wm.PositionXYOffsetSelect = POSOFFSET_NONE;
+
+      if (wm_prog_data->base.total_scratch) {
+         wm.ScratchSpaceBasePointer =
+            render_bo(stage_state->scratch_bo,
+                      ffs(stage_state->per_thread_scratch) - 11);
+      }
+
+      wm.PixelShaderComputedDepth = writes_depth;
+#endif
+
+      wm.PointRasterizationRule = RASTRULE_UPPER_RIGHT;
+
+      /* _NEW_LINE */
+      wm.LineStippleEnable = ctx->Line.StippleFlag;
+
+      /* _NEW_POLYGON */
+      wm.PolygonStippleEnable = ctx->Polygon.StippleFlag;
+      wm.BarycentricInterpolationMode = wm_prog_data->barycentric_interp_modes;
+
+#if GEN_GEN < 8
+      /* _NEW_BUFFERS */
+      const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1;
+
+      wm.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth;
+      wm.PixelShaderUsesSourceW = wm_prog_data->uses_src_w;
+      if (wm_prog_data->uses_kill ||
+          _mesa_is_alpha_test_enabled(ctx) ||
+          _mesa_is_alpha_to_coverage_enabled(ctx) ||
+          wm_prog_data->uses_omask) {
+         wm.PixelShaderKillsPixel = true;
+      }
+
+      /* _NEW_BUFFERS | _NEW_COLOR */
+      if (brw_color_buffer_write_enabled(brw) || writes_depth ||
+          wm_prog_data->has_side_effects || wm.PixelShaderKillsPixel) {
+         wm.ThreadDispatchEnable = true;
+      }
+      if (multisampled_fbo) {
+         /* _NEW_MULTISAMPLE */
+         if (ctx->Multisample.Enabled)
+            wm.MultisampleRasterizationMode = MSRASTMODE_ON_PATTERN;
+         else
+            wm.MultisampleRasterizationMode = MSRASTMODE_OFF_PIXEL;
+
+         if (wm_prog_data->persample_dispatch)
+            wm.MultisampleDispatchMode = MSDISPMODE_PERSAMPLE;
+         else
+            wm.MultisampleDispatchMode = MSDISPMODE_PERPIXEL;
+      } else {
+         wm.MultisampleRasterizationMode = MSRASTMODE_OFF_PIXEL;
+         wm.MultisampleDispatchMode = MSDISPMODE_PERSAMPLE;
+      }
+
+#if GEN_GEN >= 7
+      wm.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode;
+      wm.PixelShaderUsesInputCoverageMask = wm_prog_data->uses_sample_mask;
+#endif
+
+      /* The "UAV access enable" bits are unnecessary on HSW because they only
+       * seem to have an effect on the HW-assisted coherency mechanism which we
+       * don't need, and the rasterization-related UAV_ONLY flag and the
+       * DISPATCH_ENABLE bit can be set independently from it.
+       * C.f. gen8_upload_ps_extra().
+       *
+       * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
+       * _NEW_COLOR
+       */
+#if GEN_IS_HASWELL
+      if (!(brw_color_buffer_write_enabled(brw) || writes_depth) &&
+          wm_prog_data->has_side_effects)
+         wm.PSUAVonly = ON;
+#endif
+#endif
+
+#if GEN_GEN >= 7
+      /* BRW_NEW_FS_PROG_DATA */
+      if (wm_prog_data->early_fragment_tests)
+         wm.EarlyDepthStencilControl = EDSC_PREPS;
+      else if (wm_prog_data->has_side_effects)
+         wm.EarlyDepthStencilControl = EDSC_PSEXEC;
+#endif
+   }
+}
+
+static const struct brw_tracked_state genX(wm_state) = {
+   .dirty = {
+      .mesa  = _NEW_LINE |
+               _NEW_POLYGON |
+               (GEN_GEN < 8 ? _NEW_BUFFERS |
+                              _NEW_COLOR |
+                              _NEW_MULTISAMPLE :
+                              0) |
+               (GEN_GEN < 7 ? _NEW_PROGRAM_CONSTANTS : 0),
+      .brw   = BRW_NEW_BLORP |
+               BRW_NEW_FS_PROG_DATA |
+               (GEN_GEN < 7 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION |
+                              BRW_NEW_BATCH
+                            : BRW_NEW_CONTEXT),
+   },
+   .emit = genX(upload_wm),
+};
+
 #endif
 
 /* ---------------------------------------------------------------------- */
@@ -1560,7 +1742,7 @@ genX(init_atoms)(struct brw_context *brw)
       &gen6_gs_state,
       &genX(clip_state),
       &genX(sf_state),
-      &gen6_wm_state,
+      &genX(wm_state),
 
       &gen6_scissor_state,
 
@@ -1649,7 +1831,7 @@ genX(init_atoms)(struct brw_context *brw)
       &genX(clip_state),
       &genX(sbe_state),
       &genX(sf_state),
-      &gen7_wm_state,
+      &genX(wm_state),
       &genX(ps_state),
 
       &gen6_scissor_state,
@@ -1741,7 +1923,7 @@ genX(init_atoms)(struct brw_context *brw)
       &gen8_ps_extra,
       &genX(ps_state),
       &genX(depth_stencil_state),
-      &gen8_wm_state,
+      &genX(wm_state),
 
       &gen6_scissor_state,