diff options
| author | Nabendu Maiti <nabendu.bikash.maiti@intel.com> | 2017-02-24 13:59:08 +0200 |
|---|---|---|
| committer | Tapani Pälli <tapani.palli@intel.com> | 2017-03-28 09:38:32 +0300 |
| commit | 68ed0b8dcf272bc2f37460cd09a2b2ccb890307c (patch) | |
| tree | f549b4874b5b8371491ca3d3baf7d01296de91e4 | |
| parent | 48d54e0e9561c35a77f8ff25356363569715e59c (diff) | |
drm/i915: Update pipe-scaler according to destination size
Pipe scaler is scaler registers are updated according to provided
destination size from user.
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 82be6b717ffe..de0d7b641d56 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4679,12 +4679,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, */ int skl_update_scaler_crtc(struct intel_crtc_state *state) { - const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; - return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, &state->scaler_state.scaler_id, DRM_ROTATE_0, state->pipe_src_w, state->pipe_src_h, - adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); + state->pipe_dst_w, state->pipe_dst_h); } /** @@ -10987,15 +10985,15 @@ static int skylake_pfiter_calculate(struct drm_crtc *crtc, intel_pch_panel_fitting(intel_crtc, pipe_config, pipe_config->pipe_scaling_mode); - pipe_config->pipe_dst_x = - (pipe_config->pch_pfit.pos >> 16); - pipe_config->pipe_dst_y = - (pipe_config->pch_pfit.pos & 0xffff); - pipe_config->pipe_dst_w = - (pipe_config->pch_pfit.size >> 16); - pipe_config->pipe_dst_h = - (pipe_config->pch_pfit.size & 0xffff); } + pipe_config->pipe_dst_x = + (pipe_config->pch_pfit.pos >> 16); + pipe_config->pipe_dst_y = + (pipe_config->pch_pfit.pos & 0xffff); + pipe_config->pipe_dst_w = + (pipe_config->pch_pfit.size >> 16); + pipe_config->pipe_dst_h = + (pipe_config->pch_pfit.size & 0xffff); } } return ret; @@ -11453,6 +11451,10 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, pipe_config->pipe_dst_w = pipe_config->pipe_src_w; pipe_config->pipe_dst_h = pipe_config->pipe_src_h; + pipe_config->base.dst_w = pipe_config->pipe_src_w; + pipe_config->base.dst_h = pipe_config->pipe_src_h; + pipe_config->base.src_w = pipe_config->pipe_src_w; + pipe_config->base.src_h = pipe_config->pipe_src_h; encoder_retry: /* Ensure the port clock defaults are reset when retrying. */ @@ -12559,8 +12561,8 @@ static int intel_atomic_check(struct drm_device *dev, crtc_state->src_w = adjusted_mode->hdisplay; crtc_state->src_h = adjusted_mode->vdisplay; - crtc_state->dst_w = adjusted_mode->hdisplay; - crtc_state->dst_h = adjusted_mode->vdisplay; + crtc_state->dst_w = crtc_state->src_w; + crtc_state->dst_h = crtc_state->src_h; crtc_state->dst_x = 0; crtc_state->dst_y = 0; crtc_state->fitting_mode = 0; |