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path: root/drivers/spi/Makefile
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2012-12-06spi/stmp: remove obsolete driverWolfram Sang1-1/+0
This driver is obsolete and can't even be built anymore since the platform it depends has been removed. The STMP series is completely covered by the MXS platform these days, so spi-mxs can be used instead. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2012-12-06Merge branch 'spi-next' from ↵Grant Likely1-1/+2
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc.git Pull in the changes Mark has queued up for SPI
2012-12-05spi/clps711x: New SPI master driverAlexander Shiyan1-0/+1
This patch add new driver for CLPS711X SPI master controller. Due to platform limitations driver supports only 8 bit transfer mode. Chip select control is handled via GPIO. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2012-11-14spi: tegra: add spi driver for sflash controllerLaxman Dewangan1-0/+1
NVIDIA's Tegra20 have the SPI (SFLASH) controller to interface with spi flash device which is used for system boot. Add the spi driver for this controller. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-10-30spi: tegra: add spi driver for SLINK controllerLaxman Dewangan1-1/+1
Tegra20/Tegra30 supports the spi interface through its SLINK controller. Add spi driver for SLINK controller. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-10-09Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds1-0/+1
Pull MIPS update from Ralf Baechle: "This is the MIPS update for 3.7. A fair chunk of them are platform updates to the Cavium Octeon SOC (which involves machine generated header files of considerable size), Atheros ATH79xx, RMI aka Netlogic aka Broadcom XLP, Broadcom BCM63xx platforms. Support for the commercial MIPS simulator MIPSsim has been removed as MIPS Technologies is shifting away from this product and Qemu is offering various more powerful platforms. The generic MIPS code can now also probe for no-execute / write-only TLB features implemented without the full SmartMIPS extension as permitted by the latest MIPS processor architecture. Lots of small changes to generic code." * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (78 commits) MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x MIPS: BCM63XX: Properly handle mac address octet overflow MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user. MIPS: Replace `-' in defconfig filename wth `_' for consistency. MIPS: Wire kcmp syscall. MIPS: MIPSsim: Remove the MIPSsim platform. MIPS: NOTIFY_RESUME is not needed in TIF masks MIPS: Merge the identical "return from syscall" per-ABI code MIPS: Unobfuscate _TIF..._MASK MIPS: Prevent hitting do_notify_resume() with !user_mode(regs). MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'. MIPS: Add base architecture support for RI and XI. MIPS: Optimise TLB handlers for MIPS32/64 R2 cores. MIPS: uasm: Add INS and EXT instructions. MIPS: Avoid pipeline stalls on some MIPS32R2 cores. MIPS: Make VPE count to be one-based. MIPS: Add new end of interrupt functionality for GIC. MIPS: Add EIC support for GIC. MIPS: Code clean-ups for the GIC. ...
2012-10-01spi: remove completely broken Tegra driverStephen Warren1-1/+0
The current SPI driver has many issues. Examples are: * Segfaulting on most transfers due to expecting all transfers to have both RX and TX buffers. * Hanging on TX transfers since the whole driver flow is driven by RX DMA completion, but the HW is only told to enable RX for RX transfers. * Use of clk_disable_unprepare() from atomic context. * Once those and other minor issues are fixed, the driver still doesn't actually work. * The driver also implements a deprecated API to the SPI core. For this reason, simply remove the driver completely. This has two advantages: 1) This will remove the last use of Tegra's <mach/dma.h>, which will allow that file to be removed, which is required for single zImage work. 2) The downstream driver is significaly different from the current code. I believe a patch to re-add the downstream driver (with appropriate cleanup) will be much simpler to review if it's a new file rather than randomly interspered with essentially unrelated existing code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-09-28Merge branches 'spi-drivers' and 'spi-mxs' into spi-nextMark Brown1-0/+2
2012-08-22spi: Add SPI master controller for OCTEON SOCs.David Daney1-0/+1
Add the driver, link it into the kbuild system and provide device tree binding documentation. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Patchwork: http://patchwork.linux-mips.org/patch/4292/ Signed-off-by: John Crispin <blogic@openwrt.org>
2012-08-22spi: Master driver for NXP SC18IS602/603Guenter Roeck1-0/+1
This driver adds support for NXP SC18IS602/603 I2C to SPI bus bridge. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-08-17spi/mxs: Add SPI driver for mx233/mx28Marek Vasut1-0/+1
This is slightly reworked version of the SPI driver. Support for DT has been added and it's been converted to queued API. Based on previous attempt by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Chris Ball <cjb@laptop.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-07-30Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds1-0/+1
Pull MIPS updates from Ralf Baechle: "More hardware support across the field including a bunch of device drivers. The highlight however really are further steps towards device tree. This has been sitting in -next for ages. All MIPS _defconfigs have been tested to boot or where I don't have hardware available, to at least build fine." * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (77 commits) MIPS: Loongson 1B: Add defconfig MIPS: Loongson 1B: Add board support MIPS: Netlogic: early console fix MIPS: Netlogic: Fix indentation of smpboot.S MIPS: Netlogic: remove cpu_has_dc_aliases define for XLP MIPS: Netlogic: Remove unused pcibios_fixups MIPS: Netlogic: Add XLP SoC devices in FDT MIPS: Netlogic: Add IRQ mappings for more devices MIPS: Netlogic: USB support for XLP MIPS: Netlogic: XLP PCIe controller support. MIPS: Netlogic: Platform changes for XLR/XLS I2C MIPS: Netlogic: Platform NAND/NOR flash support MIPS: Netlogic: Platform changes for XLS USB MIPS: Netlogic: Remove NETLOGIC_ prefix MIPS: Netlogic: SMP wakeup code update MIPS: Netlogic: Update comments in smpboot.S MIPS: BCM63XX: Add 96328avng reference board MIPS: Expose PCIe drivers for MIPS MIPS: BCM63XX: Add PCIe Support for BCM6328 MIPS: BCM63XX: Move the PCI initialization into its own function ...
2012-07-23SPI: MIPS: lantiq: add FALCON spi driverThomas Langer1-0/+1
The external bus unit (EBU) found on the FALCON SoC has spi emulation that is designed for serial flash access. This driver has only been tested with m25p80 type chips. The hardware has no support for other types of spi peripherals. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Cc: spi-devel-general@lists.sourceforge.net Cc: linux-mips@linux-mips.org Acked-by: Grant Likely <grant.likely@secretlab.ca> Patchwork: https://patchwork.linux-mips.org/patch/3844/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-07-20spi: Add AD-FMCOMMS1-EBZ I2C-SPI bridge driverLars-Peter Clausen1-0/+1
This patch adds support for the I2C-SPI bridge which can be found on the Analog Devices AD-FMCOMMS1-EBZ board. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2012-04-27spi/bfin5xx: rename config macro name for bfin5xx spi controller driverScott Jiang1-1/+1
This controller is only for blackfin 5xx soc, so rename it to BFIN5XX Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2012-03-09spi: add Broadcom BCM63xx SPI controller driverFlorian Fainelli1-0/+1
This patch adds support for the SPI controller found on the Broadcom BCM63xx SoCs. Signed-off-by: Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2012-03-09SPI: add CSR SiRFprimaII SPI controller driverZhiwu Song1-0/+1
CSR SiRFprimaII has two SPIs (SPI0 and SPI1). Features: * Master and slave modes * 8-/12-/16-/32-bit data unit * 256 bytes receive data FIFO and 256 bytes transmit data FIFO * Multi-unit frame * Configurable SPI_EN (chip select pin) active state * Configurable SPI_CLK polarity * Configurable SPI_CLK phase * Configurable MSB/LSB first Signed-off-by: Zhiwu Song <zhiwu.song@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2012-03-09spi: Add SuperH HSPI prototype driverKuninori Morimoto1-0/+1
This patch adds SuperH HSPI driver. It is still prototype driver, but has enough function at this point. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2012-03-07spi: add support for Renesas RSPIShimoda, Yoshihiro1-0/+1
The SH7757 has RSPI module. This patch supports it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-04spi: remove obsolete spi-s3c24xx-gpio driverPeter Korsgaard1-1/+0
It was equivalent to spi-gpio, and there's no longer any in-tree users of it, so get rid of it. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Acked-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-06-06spi: reorganize driversGrant Likely1-62/+50
Sort the SPI makefile and enforce the naming convention spi_*.c for spi drivers. This change also rolls the contents of atmel_spi.h into the .c file since there is only one user of that particular include file. v2: - Use 'spi-' prefix instead of 'spi_' to match what seems to be be the predominant pattern for subsystem prefixes. - Clean up filenames in Kconfig and header comment blocks Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2011-05-27spi/spi_bfin_sport: new driver for a SPI bus via the Blackfin SPORT peripheralCliff Cai1-0/+1
The Blackfin SPORT peripheral is a pretty flexible device. With enough coaching, we can make it generate SPI compatible waveforms. This is desirable as the SPORT can run at much higher clock frequencies than the dedicated on-chip SPI peripheral, and it can do full duplex DMA. It also opens up the possibility of multiple SPI buses in case someone wants to dedicate a whole bus to a specific part that does not play well with others. Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org> Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-03-18Merge branch 'spi/next' of git://git.secretlab.ca/git/linux-2.6Linus Torvalds1-0/+3
* 'spi/next' of git://git.secretlab.ca/git/linux-2.6: (34 commits) spi/dw_spi: move dw_spi.h into drivers/spi spi/dw_spi: Fix missing header gpio/langwell: Clear edge bit before handling gpio/langwell: Simplify demux loop gpio/langwell: Convert irq name space gpio/langwell: Fix broken irq_eoi change. gpio; Make Intel chipset gpio drivers depend on x86 gpio/cs5535-gpio: Fix section mismatch spi/rtc-{ds1390,ds3234,m41t94}: Use spi_get_drvdata() for SPI devices spi/davinci: Support DMA transfers larger than 65535 words spi/davinci: Use correct length parameter to dma_map_single calls gpio: Use __devexit at necessary places gpio: add MODULE_DEVICE_TABLE to pch_gpio and ml_ioh_gpio gpio/mcp23s08: support mcp23s17 variant of_mmc_spi: add card detect irq support spi/omap_mcspi: catch xfers of non-multiple SPI word size spi/omap_mcspi: Off-by-one error in finding the right divisor gpio/pca953x: Fix wrong pointer type spi/pl022: rid dangling labels spi: add support for SuperH SPI ...
2011-03-15spi: add ti-ssp spi master driverCyril Chemparathy1-0/+1
This patch adds an SPI master implementation that operates on top of an underlying TI-SSP port. Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-02-22spi: add support for SuperH SPIYoshihiro Shimoda1-0/+1
The SH7757 has SPI0 module. This patch supports it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [grant.likely@secretlab.ca: fixed Makefile ordering, added __dev{init,exit} annotations, removed DRIVER_VERSION (this is mainline, the version == the kernel version) and tidied some indentation & style stuff] Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-02-22spi: New driver for Altera SPIThomas Chou1-0/+1
This patch adds a new SPI driver to support the Altera SOPC Builder SPI component. It uses the bitbanging library. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-02-22spi: add OpenCores tiny SPI driverThomas Chou1-0/+1
This patch adds support of OpenCores tiny SPI driver. http://opencores.org/project,tiny_spi Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-01-18SPI: Add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCsGabor Juhos1-0/+1
The Atheros AR71XX/AR724X/AR913X SoCs have a built-in SPI controller. This patch implements a driver for that. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: David Brownell <dbrownell@users.sourceforge.net> Cc: spi-devel-general@lists.sourceforge.net Acked-by: Grant Likely <grant.likely@secretlab.ca> Cc: linux-mips@linux-mips.org Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1960/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-29Merge branch 'spi' of git://git.linutronix.de/users/bigeasy/soda into spi/nextGrant Likely1-0/+1
* 'spi' of git://git.linutronix.de/users/bigeasy/soda into spi/next spi/pxa2xx: register driver properly spi/pxa2xx: add support for shared IRQ handler spi/pxa2xx: Use define for SSSR_TFL_MASK instead of plain numbers arm/pxa2xx: reorgazine SSP and SPI header files spi/pxa2xx: Add CE4100 support spi/pxa2xx: Consider CE4100's FIFO depth spi/pxa2xx: Add chipselect support for Sodaville spi/pxa2xx: Modify RX-Tresh instead of busy-loop for the remaining RX bytes. spi/pxa2xx: pass of_node to spi device and set a parent device
2010-12-24spi/dw_spi: add DMA supportFeng Tang1-1/+2
dw_spi driver in upstream only supports PIO mode, and this patch will support it to cowork with the Designware dma controller used on Intel Moorestown platform, at the same time it provides a general framework to support dw_spi core to cowork with dma controllers on other platforms It has been tested with a Option GTM501L 3G modem and Infenion 60x60 modem. To use DMA mode, DMA controller 2 of Moorestown has to be enabled Also change the dma interface suggested by Linus Walleij. Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Feng Tang <feng.tang@intel.com> [Typo fix and renames to match intel_mid_dma renaming] Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-12-01spi/pxa2xx: Add CE4100 supportSebastian Andrzej Siewior1-0/+1
Sodaville's SPI controller is very much the same as in PXA25x. The difference: - The RX/TX FIFO is only 4 words deep instead of 16 - No DMA support - The SPI controller offers a CS functionality Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
2010-11-09spi/xilinx: merge OF support code into main driverGrant Likely1-1/+0
Now that the of_platform_bus_type has been merged with the platform bus type, a single platform driver can handle both OF and non-OF use cases. This patch merges the OF support into the platform driver. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Tested-by: Michal Simek <monstr@monstr.eu>
2010-11-09spi/xilinx: fold platform_driver support into main bodyGrant Likely1-1/+0
This patch merges the platform driver support into the main body of xilinx_spi.c in preparation for merging the OF and non-OF support code. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Tested-by: Michal Simek <monstr@monstr.eu>
2010-10-21spi: add spi_tegra driverErik Gilling1-0/+1
v2 changes: from Thierry Reding: * add "select TEGRA_SYSTEM_DMA" to Kconfig from Grant Likely: * add oneline description to header * inline references to DRIVER_NAME * inline references to BUSY_TIMEOUT * open coded bytes_per_word() * spi_readl/writel -> spi_tegra_readl/writel * move transfer validation to spi_tegra_transfer * don't request_mem_region iomem as platform bus does that for us * __exit -> __devexit v3 changes: from Russell King: * put request_mem_region back int from Grant Likely: * remove #undef DEBUG * add SLINK_ to register bit defines * remove unused bytes_per_word * make spi_tegra_readl/writel static linine * various refactoring for clarity * mark err if BSY bit is not cleared after 1000 retries * move spinlock to protect setting of RDY bit * subsys_initcall -> module_init v3 changes: from Grant Likely: * update spi_tegra to use PTR_ERRless dma API v4 changes: from Grant Likely: * remove empty spi_tegra_cleanup fucntion * allow device ids of -1 Signed-off-by: Erik Gilling <konkers@android.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Cc: Thierry Reding <thierry.reding@avionic-design.de> Cc: Russell King <linux@arm.linux.org.uk> spi: tegra: cleanups from upstream review Change-Id: Icecf7e64efcb39de072a15234ba1faa4bad40d25 Signed-off-by: Erik Gilling <konkers@android.com>
2010-10-12spi/fsl_spi: add eSPI controller supportMingkai Hu1-0/+1
Add eSPI controller support based on the library code spi_fsl_lib.c. The eSPI controller is newer controller 85xx/Pxxx devices supported. There're some differences comparing to the SPI controller: 1. Has different register map and different bit definition So leave the code operated the register to the driver code, not the common code. 2. Support 4 dedicated chip selects The software can't controll the chip selects directly, The SPCOM[CS] field is used to select which chip selects is used, and the SPCOM[TRANLEN] field is set to tell the controller how long the CS signal need to be asserted. So the driver doesn't need the chipselect related function when transfering data, just set corresponding register fields to controll the chipseclect. 3. Different Transmit/Receive FIFO access register behavior For SPI controller, the Tx/Rx FIFO access register can hold only one character regardless of the character length, but for eSPI controller, the register can hold 4 or 2 characters according to the character lengths. Access the Tx/Rx FIFO access register of the eSPI controller will shift out/in 4/2 characters one time. For SPI subsystem, the command and data are put into different transfers, so we need to combine all the transfers to one transfer in order to pass the transfer to eSPI controller. 4. The max transaction length limitation The max transaction length one time is limitted by the SPCOM[TRANSLEN] field which is 0xFFFF. When used mkfs.ext2 command to create ext2 filesystem on the flash, the read length will exceed the max value of the SPCOM[TRANSLEN] field. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12spi/mpc8xxx: refactor the common code for SPI/eSPI controllerMingkai Hu1-0/+1
Refactor the common code in file spi_fsl_spi.c to spi_fsl_lib.c used by SPI/eSPI controller driver as a library, and leave the QE/CPM SPI controller code in the SPI controller driver spi_fsl_spi.c. Because the register map of the SPI controller and eSPI controller is so different, also leave the code operated the register to the driver code, not the common code. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12spi/mpc8xxx: rename spi_mpc8xxx.c to spi_fsl_spi.cMingkai Hu1-1/+1
This will pave the way to refactor out the common code which can be used by the eSPI controller driver, and rename the SPI controller dirver to the file spi_fsl_spi.c. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-12spi: change to new flag variablematt mooney1-3/+1
Replace EXTRA_CFLAGS with ccflags-y. Signed-off-by: matt mooney <mfm@muteddisk.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-10-08spi/topcliff: Add topcliff platform controller hub (PCH) spi bus driverMasayuki Ohtake1-0/+1
Topcliff PCH is the platform controller hub that is going to be used in Intel's upcoming general embedded platform. All IO peripherals in Topcliff PCH are actually devices sitting on AMBA bus. This patch adds a driver for the SPI bus integrated into the Topcliff device. Signed-off-by: Masayuki Ohtake <masa-korg@dsn.okisemi.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-05-25spi/mpc5121: Add SPI master driver for MPC5121 PSCAnatolij Gustschin1-0/+1
Signed-off-by: John Rigby <jcrigby@gmail.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-05-25spi/ep93xx: implemented driver for Cirrus EP93xx SPI controllerMika Westerberg1-0/+1
This patch adds an SPI master driver for the Cirrus EP93xx SPI controller found in EP93xx chips. Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi> Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-01-21Memory-mapped dw_spi driverJean-Hugues Deschenes1-0/+1
Adds a memory-mapped I/O dw_spi platform device. Signed-off-by: Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-01-20spi: Add Freescale/Motorola Coldfire QSPI driverSteven King1-0/+1
Add support for the QSPI controller found some on Freescale/Motorola Coldfire MCUs. Full duplex, active high cs, spi modes 0-3 and word sizes 8-16 bits are supported. The hardware drives the MISO, MOSI and SCLK lines, but the chip selects are managed via GPIO and must be configured by the board code. The QSPI controller has an 80 byte buffer which allows us to transfer up to 16 words at a time. For transfers longer than 16 words, we split the buffer in half so we can update in one half while the controller is operating on the other half. Interrupt latencies then ultimately limits our sustained thru-put to something less than half the maximum speed supported by the part. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-01-20spi: Add SPI master driver for DaVinci/DA8xxSandeep Paulraj1-0/+1
This patch adds support for a SPI master driver for the DaVinci series of SOCs Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Philby John <pjohn@in.mvista.com> Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2009-12-17spi: Add s3c64xx SPI Controller driverJassi Brar1-0/+1
Each SPI controller has exactly one CS line and as such doesn't provide for multi-cs. We implement a workaround to support multi-cs by _not_ configuring the mux'ed CS pin for each SPI controller. The CS mechanism is assumed to be fully machine specific - the driver doesn't even assume some GPIO pin is used to control the CS. The driver selects between DMA and POLLING mode depending upon the xfer size - DMA mode for xfers bigger than FIFO size, POLLING mode otherwise. The driver has been designed to be capable of running SoCs since s3c64xx and till date, for that reason some of the register fields have been passed via, SoC specific, platform data. Signed-off-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2009-12-17spi_s3c24xx: add FIQ pseudo-DMA supportBen Dooks1-1/+6
Add pseudo-DMA by FIQ to the S3C24XX SPI driver. This allows the driver to get DMA-like performance where there are either no free DMA channels or when doing transfers that required both TX and RX data paths. Since this patch requires the addition of an assembly file to hold the FIQ code, we rename the module (instead of adding a rename of the .c file to this patch). We expect most users are loading this via udev and thus there should be no change to the userland configuration. Signed-off-by: Ben Dooks <ben@simtec.co.uk> Signed-off-by: Simtec Linux Team <linux@simtec.co.uk> Cc: David Brownell <david-b@pacbell.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2009-12-17spi: controller driver for Designware SPI coreFeng Tang1-0/+2
Driver for the Designware SPI core, it supports multipul interfaces like PCI/APB etc. User can use "dw_apb_ssi_db.pdf" from Synopsys as HW datasheet. [randy.dunlap@oracle.com: fix build] [akpm@linux-foundation.org: build fix] Signed-off-by: Feng Tang <feng.tang@intel.com> Cc: David Brownell <david-b@pacbell.net> Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2009-12-13Add OMAP spi100k driverCory Maccarrone1-0/+1
This change adds the OMAP SPI 100k driver created by Fabrice Crohas <fcrohas@gmail.com>. This SPI bus is found on OMAP7xx-series smartphones, and for many, the touchscreen is attached to this bus. The lion's share of the work was done by Fabrice on this driver -- I am merely porting it from the Linwizard project on his behalf. Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2009-12-13ARM: NUC900: Add spi driver support for nuc900Wan ZongShun1-0/+1
Signed-off-by: Wan ZongShun <mcuos.com@gmail.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2009-12-13spi: SuperH MSIOF SPI Master driver V2Magnus Damm1-0/+1
This patch is V2 of SPI Master support for the SuperH MSIOF. Full duplex, spi mode 0-3, active high cs, 3-wire and lsb first should all be supported, but the driver has so far only been tested with "mmc_spi". The MSIOF hardware comes with 32-bit FIFOs for receive and transmit, and this driver simply breaks the SPI messages into FIFO-sized chunks. The MSIOF hardware manages the pins for clock, receive and transmit (sck/miso/mosi), but the chip select pin is managed by software and must be configured as a regular GPIO pin by the board code. Performance wise there is still room for improvement, but on a Ecovec board with the built-in sh7724 MSIOF0 this driver gets Mini-sd read speeds of about half a megabyte per second. Future work include better clock setup and merging of 8-bit transfers into 32-bit words to reduce interrupt load and improve throughput. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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