diff options
| author | Jerome Glisse <jglisse@redhat.com> | 2010-03-09 14:45:11 +0000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2010-04-06 11:21:04 +1000 |
| commit | a2d07b7438f015a0349bc9af3c96a8164549bbc5 (patch) | |
| tree | 7e05f0789ab09215efc96f8d2fd49eb61c3cab9f /drivers/gpu/drm/radeon/rv515.c | |
| parent | 225758d8ba4fdcc1e8c9cf617fd89529bd4a9596 (diff) | |
drm/radeon/kms: rename gpu_reset to asic_reset
Patch rename gpu_reset to asic_reset in prevision of having
gpu_reset doing more stuff than just basic asic reset.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rv515.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/rv515.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 1cf233f7e516..2a4c01f5cf12 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c @@ -227,7 +227,7 @@ int rv515_ga_reset(struct radeon_device *rdev) return -1; } -int rv515_gpu_reset(struct radeon_device *rdev) +int rv515_asic_reset(struct radeon_device *rdev) { uint32_t status; @@ -334,7 +334,7 @@ static int rv515_debugfs_ga_info(struct seq_file *m, void *data) tmp = RREG32(0x2140); seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); - radeon_gpu_reset(rdev); + radeon_asic_reset(rdev); tmp = RREG32(0x425C); seq_printf(m, "GA_IDLE 0x%08x\n", tmp); return 0; @@ -502,7 +502,7 @@ int rv515_resume(struct radeon_device *rdev) /* Resume clock before doing reset */ rv515_clock_startup(rdev); /* Reset gpu before posting otherwise ATOM will enter infinite loop */ - if (radeon_gpu_reset(rdev)) { + if (radeon_asic_reset(rdev)) { dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", RREG32(R_000E40_RBBM_STATUS), RREG32(R_0007C0_CP_STAT)); @@ -572,7 +572,7 @@ int rv515_init(struct radeon_device *rdev) return -EINVAL; } /* Reset gpu before posting otherwise ATOM will enter infinite loop */ - if (radeon_gpu_reset(rdev)) { + if (radeon_asic_reset(rdev)) { dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", RREG32(R_000E40_RBBM_STATUS), |