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authorTakashi Yoshii <takasi-y@ops.dti.ne.jp>2013-12-02 03:19:15 +0900
committerMark Brown <broonie@linaro.org>2013-12-02 12:54:25 +0000
commit50a7799829835120950520231797642e19d4152f (patch)
tree72fa18b45bbcb69301b5955b3538d005788dbf99 /drivers/spi/spi-sh-msiof.c
parent5c32d29f13e9f7b94e0e82bf3ed7a1cf6b0c0dd3 (diff)
spi: spi-sh-msiof: set hi/low Active for HW CS
Set hardware CS(CS control function on MSIOF <-> GPIO CS) polarity according to SPI_CS_HIGH flag on spi->mode. Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'drivers/spi/spi-sh-msiof.c')
-rw-r--r--drivers/spi/spi-sh-msiof.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index d96b047afcd2..a0c3e54b0003 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -169,7 +169,7 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
u32 cpol, u32 cpha,
- u32 tx_hi_z, u32 lsb_first)
+ u32 tx_hi_z, u32 lsb_first, u32 cs_high)
{
u32 tmp;
int edge;
@@ -182,8 +182,12 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
* 1 1 11 11 1 1
*/
sh_msiof_write(p, FCTR, 0);
- sh_msiof_write(p, TMDR1, 0xe2000005 | (lsb_first << 24));
- sh_msiof_write(p, RMDR1, 0x22000005 | (lsb_first << 24));
+
+ tmp = 0;
+ tmp |= !cs_high << 25;
+ tmp |= lsb_first << 24;
+ sh_msiof_write(p, TMDR1, 0xe0000005 | tmp);
+ sh_msiof_write(p, RMDR1, 0x20000005 | tmp);
tmp = 0xa0000000;
tmp |= cpol << 30; /* TSCKIZ */
@@ -417,7 +421,8 @@ static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on)
sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
!!(spi->mode & SPI_CPHA),
!!(spi->mode & SPI_3WIRE),
- !!(spi->mode & SPI_LSB_FIRST));
+ !!(spi->mode & SPI_LSB_FIRST),
+ !!(spi->mode & SPI_CS_HIGH));
}
/* use spi->controller data for CS (same strategy as spi_gpio) */