WIP

8 files changed, 287 insertions, 385 deletions

diff --git a/include/drm-uapi/tegra_drm.h b/include/drm-uapi/tegra_drm.h
index 6c07919c04e9..154b125b685d 100644
--- a/include/drm-uapi/tegra_drm.h
+++ b/include/drm-uapi/tegra_drm.h
@@ -29,8 +29,8 @@
 extern "C" {
 #endif
 
-#define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
-#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
+#define DRM_TEGRA_GEM_CONTIGUOUS	(1 << 0)
+#define DRM_TEGRA_GEM_FLAGS		(DRM_TEGRA_GEM_CONTIGUOUS)
 
 /**
  * struct drm_tegra_gem_create - parameters for the GEM object creation IOCTL
@@ -48,19 +48,15 @@ struct drm_tegra_gem_create {
 	 *
 	 * A bitmask of flags that influence the creation of GEM objects:
 	 *
-	 * DRM_TEGRA_GEM_CREATE_TILED
-	 *   Use the 16x16 tiling format for this buffer.
-	 *
-	 * DRM_TEGRA_GEM_CREATE_BOTTOM_UP
-	 *   The buffer has a bottom-up layout.
+	 * DRM_TEGRA_GEM_CONTIGUOUS - The buffer is to be backed by physically
+	 *	contiguous memory.
 	 */
 	__u32 flags;
 
 	/**
 	 * @handle:
 	 *
-	 * The handle of the created GEM object. Set by the kernel upon
-	 * successful completion of the IOCTL.
+	 * Return location for the handle of the created GEM object.
 	 */
 	__u32 handle;
 };
@@ -86,113 +82,61 @@ struct drm_tegra_gem_mmap {
 	/**
 	 * @offset:
 	 *
-	 * The mmap offset for the given GEM object. Set by the kernel upon
-	 * successful completion of the IOCTL.
+	 * Return location for the mmap offset for the given GEM object.
 	 */
 	__u64 offset;
 };
 
-/**
- * struct drm_tegra_syncpt_read - parameters for the read syncpoint IOCTL
- */
-struct drm_tegra_syncpt_read {
-	/**
-	 * @id:
-	 *
-	 * ID of the syncpoint to read the current value from.
-	 */
-	__u32 id;
-
-	/**
-	 * @value:
-	 *
-	 * The current syncpoint value. Set by the kernel upon successful
-	 * completion of the IOCTL.
-	 */
-	__u32 value;
-};
+#define DRM_TEGRA_CHANNEL_FLAGS (0)
 
 /**
- * struct drm_tegra_syncpt_incr - parameters for the increment syncpoint IOCTL
- */
-struct drm_tegra_syncpt_incr {
-	/**
-	 * @id:
-	 *
-	 * ID of the syncpoint to increment.
-	 */
-	__u32 id;
-
-	/**
-	 * @pad:
-	 *
-	 * Structure padding that may be used in the future. Must be 0.
-	 */
-	__u32 pad;
-};
-
-/**
- * struct drm_tegra_syncpt_wait - parameters for the wait syncpoint IOCTL
+ * struct drm_tegra_open_channel - parameters for the open channel IOCTL
  */
-struct drm_tegra_syncpt_wait {
-	/**
-	 * @id:
-	 *
-	 * ID of the syncpoint to wait on.
-	 */
-	__u32 id;
-
+struct drm_tegra_open_channel {
 	/**
-	 * @thresh:
+	 * @client:
 	 *
-	 * Threshold value for which to wait.
+	 * The client ID for this channel.
 	 */
-	__u32 thresh;
+	__u32 client;
 
 	/**
-	 * @timeout:
+	 * @flags:
 	 *
-	 * Timeout, in milliseconds, to wait.
+	 * A bitmask of flags that influence the channel creation. Currently
+	 * no flags are defined, so this must be 0.
 	 */
-	__u32 timeout;
+	__u32 flags;
 
 	/**
-	 * @value:
+	 * @syncpts:
 	 *
-	 * The new syncpoint value after the wait. Set by the kernel upon
-	 * successful completion of the IOCTL.
+	 * Return location for the number of syncpoints used by this channel.
 	 */
-	__u32 value;
-};
-
-#define DRM_TEGRA_NO_TIMEOUT	(0xffffffff)
+	__u32 syncpts;
 
-/**
- * struct drm_tegra_open_channel - parameters for the open channel IOCTL
- */
-struct drm_tegra_open_channel {
 	/**
-	 * @client:
+	 * @version:
 	 *
-	 * The client ID for this channel.
+	 * Return location for the implementation version of this channel.
 	 */
-	__u32 client;
+	__u32 version;
 
 	/**
-	 * @pad:
+	 * @context:
 	 *
-	 * Structure padding that may be used in the future. Must be 0.
+	 * Return location for the application context of this channel. This
+	 * context needs to be passed to the DRM_TEGRA_CHANNEL_CLOSE or the
+	 * DRM_TEGRA_SUBMIT IOCTLs.
 	 */
-	__u32 pad;
+	__u64 context;
 
 	/**
-	 * @context:
+	 * @reserved:
 	 *
-	 * The application context of this channel. Set by the kernel upon
-	 * successful completion of the IOCTL. This context needs to be passed
-	 * to the DRM_TEGRA_CHANNEL_CLOSE or the DRM_TEGRA_SUBMIT IOCTLs.
+	 * This field is reserved for future use. Must be 0.
 	 */
-	__u64 context;
+	__u64 reserved;
 };
 
 /**
@@ -208,97 +152,106 @@ struct drm_tegra_close_channel {
 	__u64 context;
 };
 
-/**
- * struct drm_tegra_get_syncpt - parameters for the get syncpoint IOCTL
- */
-struct drm_tegra_get_syncpt {
+#define DRM_TEGRA_BUFFER_FLAGS	(0)
+
+struct drm_tegra_buffer {
 	/**
-	 * @context:
+	 * @handle:
 	 *
-	 * The application context identifying the channel for which to obtain
-	 * the syncpoint ID.
+	 * Handle of the buffer.
 	 */
-	__u64 context;
+	__u32 handle;
 
 	/**
-	 * @index:
+	 * @flags:
 	 *
-	 * Index of the client syncpoint for which to obtain the ID.
+	 * A bitmask of flags specifying the usage of the buffer. Currently no
+	 * flags are defined, so this must be 0.
 	 */
-	__u32 index;
+	__u32 flags;
+};
 
+#define DRM_TEGRA_FENCE_WAIT	(1 << 0)
+#define DRM_TEGRA_FENCE_EMIT	(1 << 1)
+#define DRM_TEGRA_FENCE_FD	(1 << 2)
+#define DRM_TEGRA_FENCE_FLAGS	(DRM_TEGRA_FENCE_WAIT | \
+				 DRM_TEGRA_FENCE_EMIT | \
+				 DRM_TEGRA_FENCE_FD)
+
+struct drm_tegra_fence {
 	/**
-	 * @id:
+	 * @handle:
 	 *
-	 * The ID of the given syncpoint. Set by the kernel upon successful
-	 * completion of the IOCTL.
+	 * Handle (syncobj) or file descriptor (sync FD) of the fence. It is
+	 * interpreted based on the DRM_TEGRA_FENCE_FD flag (see below).
 	 */
-	__u32 id;
-};
+	__u32 handle;
 
-/**
- * struct drm_tegra_get_syncpt_base - parameters for the get wait base IOCTL
- */
-struct drm_tegra_get_syncpt_base {
 	/**
-	 * @context:
+	 * @flags:
 	 *
-	 * The application context identifying for which channel to obtain the
-	 * wait base.
+	 * A bitmask of flags that specify this fence.
+	 *
+	 * DRM_TEGRA_FENCE_WAIT - Wait for this fence before the new command
+	 *	buffer is submitted.
+	 * DRM_TEGRA_FENCE_EMIT - Emit this fence when the command buffer is
+	 *	done being processed.
+	 * DRM_TEGRA_FENCE_FD - This fence is a sync FD. If not specified, a
+	 *	syncobj will be used.
 	 */
-	__u64 context;
+	__u32 flags;
 
 	/**
-	 * @syncpt:
+	 * @offset:
 	 *
-	 * ID of the syncpoint for which to obtain the wait base.
+	 * Offset in the command stream for this fence. This is used to patch
+	 * the command stream with the resolved syncpoint ID.
 	 */
-	__u32 syncpt;
+	__u32 offset;
 
 	/**
-	 * @id:
+	 * @index:
 	 *
-	 * The ID of the wait base corresponding to the client syncpoint. Set
-	 * by the kernel upon successful completion of the IOCTL.
+	 * Syncpoint to use for this fence. This is an index into the list of
+	 * syncpoints of the channel. It will be resolved to a real syncpoint
+	 * ID upon job submission.
 	 */
-	__u32 id;
-};
+	__u32 index;
 
-/**
- * struct drm_tegra_syncpt - syncpoint increment operation
- */
-struct drm_tegra_syncpt {
 	/**
-	 * @id:
+	 * @value:
 	 *
-	 * ID of the syncpoint to operate on.
+	 * Number of times to increment the syncpoint.
 	 */
-	__u32 id;
+	__u32 value;
 
 	/**
-	 * @incrs:
+	 * @reserved:
 	 *
-	 * Number of increments to perform for the syncpoint.
+	 * This field is reserved for future use. Must be 0.
 	 */
-	__u32 incrs;
+	__u32 reserved[3];
 };
 
+#define DRM_TEGRA_CMDBUF_FLAGS	(0)
+
 /**
  * struct drm_tegra_cmdbuf - structure describing a command buffer
  */
 struct drm_tegra_cmdbuf {
 	/**
-	 * @handle:
+	 * @index:
 	 *
-	 * Handle to a GEM object containing the command buffer.
+	 * Index into the job's buffer handle list, pointing to the handle of
+	 * the GEM object that contains this command buffer.
 	 */
-	__u32 handle;
+	__u32 index;
 
 	/**
 	 * @offset:
 	 *
-	 * Offset, in bytes, into the GEM object identified by @handle at
-	 * which the command buffer starts.
+	 * Offset, in bytes, into the GEM object at which the command buffer
+	 * starts. Needs to be a multiple of 4.
 	 */
 	__u32 offset;
 
@@ -310,47 +263,74 @@ struct drm_tegra_cmdbuf {
 	__u32 words;
 
 	/**
+	 * @flags:
+	 *
+	 * A bitmask of flags that influence the processing of this command
+	 * buffer. Currently no flags are defined, so this must be 0.
+	 */
+	__u32 flags;
+
+	/**
 	 * @pad:
 	 *
 	 * Structure padding that may be used in the future. Must be 0.
 	 */
 	__u32 pad;
+
+	/**
+	 * @num_fences:
+	 *
+	 * The number of fences attached to this command buffer.
+	 */
+	__u32 num_fences;
+
+	/**
+	 * @fences:
+	 *
+	 * Pointer to an array of @num_fences &struct drm_tegra_fence objects.
+	 */
+	__u64 fences;
 };
 
+#define DRM_TEGRA_RELOC_FLAGS	(0)
+
 /**
  * struct drm_tegra_reloc - GEM object relocation structure
  */
 struct drm_tegra_reloc {
 	struct {
 		/**
-		 * @cmdbuf.handle:
+		 * @cmdbuf.index:
 		 *
-		 * Handle to the GEM object containing the command buffer for
+		 * Index into the job's buffer handle list pointing to the
+		 * handle of the GEM object containing the command buffer for
 		 * which to perform this GEM object relocation.
 		 */
-		__u32 handle;
+		__u32 index;
 
 		/**
 		 * @cmdbuf.offset:
 		 *
-		 * Offset, in bytes, into the command buffer at which to
-		 * insert the relocated address.
+		 * Offset into the command buffer at which to insert the the
+		 * relocated address.
 		 */
 		__u32 offset;
 	} cmdbuf;
+
 	struct {
 		/**
-		 * @target.handle:
+		 * @target.index:
 		 *
-		 * Handle to the GEM object to be relocated.
+		 * Index into the job's buffer handle list pointing to the
+		 * handle of the GEM object to be relocated.
 		 */
-		__u32 handle;
+		__u32 index;
 
 		/**
 		 * @target.offset:
 		 *
-		 * Offset, in bytes, into the target GEM object at which the
-		 * relocated data starts.
+		 * Offset into the target GEM object at which the relocated
+		 * data starts.
 		 */
 		__u32 offset;
 	} target;
@@ -363,48 +343,23 @@ struct drm_tegra_reloc {
 	__u32 shift;
 
 	/**
-	 * @pad:
-	 *
-	 * Structure padding that may be used in the future. Must be 0.
-	 */
-	__u32 pad;
-};
-
-/**
- * struct drm_tegra_waitchk - wait check structure
- */
-struct drm_tegra_waitchk {
-	/**
-	 * @handle:
-	 *
-	 * Handle to the GEM object containing a command stream on which to
-	 * perform the wait check.
-	 */
-	__u32 handle;
-
-	/**
-	 * @offset:
-	 *
-	 * Offset, in bytes, of the location in the command stream to perform
-	 * the wait check on.
-	 */
-	__u32 offset;
-
-	/**
-	 * @syncpt:
+	 * @flags:
 	 *
-	 * ID of the syncpoint to wait check.
+	 * A bitmask of flags that determine how the GEM object should be
+	 * relocated.
 	 */
-	__u32 syncpt;
+	__u32 flags;
 
 	/**
-	 * @thresh:
+	 * @reserved:
 	 *
-	 * Threshold value for which to check.
+	 * This field is reserved for future use. Must be 0.
 	 */
-	__u32 thresh;
+	__u64 reserved;
 };
 
+#define DRM_TEGRA_SUBMIT_FLAGS	(0)
+
 /**
  * struct drm_tegra_submit - job submission structure
  */
@@ -418,18 +373,16 @@ struct drm_tegra_submit {
 	__u64 context;
 
 	/**
-	 * @num_syncpts:
+	 * @num_buffers:
 	 *
-	 * The number of syncpoints operated on by this job. This defines the
-	 * length of the array pointed to by @syncpts.
+	 * The number of GEM objects used during the execution of this job.
 	 */
-	__u32 num_syncpts;
+	__u32 num_buffers;
 
 	/**
 	 * @num_cmdbufs:
 	 *
-	 * The number of command buffers to execute as part of this job. This
-	 * defines the length of the array pointed to by @cmdbufs.
+	 * The number of command buffers to execute as part of this job.
 	 */
 	__u32 num_cmdbufs;
 
@@ -437,162 +390,49 @@ struct drm_tegra_submit {
 	 * @num_relocs:
 	 *
 	 * The number of relocations to perform before executing this job.
-	 * This defines the length of the array pointed to by @relocs.
 	 */
 	__u32 num_relocs;
 
 	/**
-	 * @num_waitchks:
-	 *
-	 * The number of wait checks to perform as part of this job. This
-	 * defines the length of the array pointed to by @waitchks.
-	 */
-	__u32 num_waitchks;
-
-	/**
-	 * @waitchk_mask:
-	 *
-	 * Bitmask of valid wait checks.
-	 */
-	__u32 waitchk_mask;
-
-	/**
 	 * @timeout:
 	 *
-	 * Timeout, in milliseconds, before this job is cancelled.
+	 * The maximum amount of time, in milliseconds, to allow for the
+	 * execution of this job.
 	 */
 	__u32 timeout;
 
 	/**
-	 * @syncpts:
+	 * @buffers:
 	 *
-	 * A pointer to an array of &struct drm_tegra_syncpt structures that
-	 * specify the syncpoint operations performed as part of this job.
-	 * The number of elements in the array must be equal to the value
-	 * given by @num_syncpts.
+	 * A pointer to @num_buffers &struct drm_tegra_buffer structures that
+	 * specify the GEM objects used during the execution of this job.
 	 */
-	__u64 syncpts;
+	__u64 buffers;
 
 	/**
 	 * @cmdbufs:
 	 *
-	 * A pointer to an array of &struct drm_tegra_cmdbuf structures that
-	 * define the command buffers to execute as part of this job. The
-	 * number of elements in the array must be equal to the value given
-	 * by @num_syncpts.
+	 * A pointer to @num_cmdbufs &struct drm_tegra_cmdbuf structures that
+	 * define the command buffers to execute as part of this job.
 	 */
 	__u64 cmdbufs;
 
 	/**
 	 * @relocs:
 	 *
-	 * A pointer to an array of &struct drm_tegra_reloc structures that
+	 * A pointer to @num_relocs &struct drm_tegra_reloc structures that
 	 * specify the relocations that need to be performed before executing
-	 * this job. The number of elements in the array must be equal to the
-	 * value given by @num_relocs.
+	 * this job.
 	 */
 	__u64 relocs;
 
 	/**
-	 * @waitchks:
-	 *
-	 * A pointer to an array of &struct drm_tegra_waitchk structures that
-	 * specify the wait checks to be performed while executing this job.
-	 * The number of elements in the array must be equal to the value
-	 * given by @num_waitchks.
-	 */
-	__u64 waitchks;
-
-	/**
-	 * @fence:
-	 *
-	 * The threshold of the syncpoint associated with this job after it
-	 * has been completed. Set by the kernel upon successful completion of
-	 * the IOCTL. This can be used with the DRM_TEGRA_SYNCPT_WAIT IOCTL to
-	 * wait for this job to be finished.
-	 */
-	__u32 fence;
-
-	/**
-	 * @reserved:
-	 *
-	 * This field is reserved for future use. Must be 0.
-	 */
-	__u32 reserved[5];
-};
-
-#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
-#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
-#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
-
-/**
- * struct drm_tegra_gem_set_tiling - parameters for the set tiling IOCTL
- */
-struct drm_tegra_gem_set_tiling {
-	/**
-	 * @handle:
-	 *
-	 * Handle to the GEM object for which to set the tiling parameters.
-	 */
-	__u32 handle;
-
-	/**
-	 * @mode:
-	 *
-	 * The tiling mode to set. Must be one of:
-	 *
-	 * DRM_TEGRA_GEM_TILING_MODE_PITCH
-	 *   pitch linear format
-	 *
-	 * DRM_TEGRA_GEM_TILING_MODE_TILED
-	 *   16x16 tiling format
-	 *
-	 * DRM_TEGRA_GEM_TILING_MODE_BLOCK
-	 *   16Bx2 tiling format
-	 */
-	__u32 mode;
-
-	/**
-	 * @value:
-	 *
-	 * The value to set for the tiling mode parameter.
-	 */
-	__u32 value;
-
-	/**
-	 * @pad:
-	 *
-	 * Structure padding that may be used in the future. Must be 0.
-	 */
-	__u32 pad;
-};
-
-/**
- * struct drm_tegra_gem_get_tiling - parameters for the get tiling IOCTL
- */
-struct drm_tegra_gem_get_tiling {
-	/**
-	 * @handle:
-	 *
-	 * Handle to the GEM object for which to query the tiling parameters.
-	 */
-	__u32 handle;
-
-	/**
-	 * @mode:
-	 *
-	 * The tiling mode currently associated with the GEM object. Set by
-	 * the kernel upon successful completion of the IOCTL.
-	 */
-	__u32 mode;
-
-	/**
-	 * @value:
+	 * @flags:
 	 *
-	 * The tiling mode parameter currently associated with the GEM object.
-	 * Set by the kernel upon successful completion of the IOCTL.
+	 * A bitmask of flags that specify how to execute this job. Currently
+	 * no flags are defined, so this must be 0.
 	 */
-	__u32 value;
+	__u32 flags;
 
 	/**
 	 * @pad:
@@ -600,79 +440,26 @@ struct drm_tegra_gem_get_tiling {
 	 * Structure padding that may be used in the future. Must be 0.
 	 */
 	__u32 pad;
-};
-
-#define DRM_TEGRA_GEM_BOTTOM_UP		(1 << 0)
-#define DRM_TEGRA_GEM_FLAGS		(DRM_TEGRA_GEM_BOTTOM_UP)
-
-/**
- * struct drm_tegra_gem_set_flags - parameters for the set flags IOCTL
- */
-struct drm_tegra_gem_set_flags {
-	/**
-	 * @handle:
-	 *
-	 * Handle to the GEM object for which to set the flags.
-	 */
-	__u32 handle;
-
-	/**
-	 * @flags:
-	 *
-	 * The flags to set for the GEM object.
-	 */
-	__u32 flags;
-};
 
-/**
- * struct drm_tegra_gem_get_flags - parameters for the get flags IOCTL
- */
-struct drm_tegra_gem_get_flags {
 	/**
-	 * @handle:
-	 *
-	 * Handle to the GEM object for which to query the flags.
-	 */
-	__u32 handle;
-
-	/**
-	 * @flags:
+	 * @reserved:
 	 *
-	 * The flags currently associated with the GEM object. Set by the
-	 * kernel upon successful completion of the IOCTL.
+	 * This field is reserved for future use. Must be 0.
 	 */
-	__u32 flags;
+	__u64 reserved[9]; /* future expansion */
 };
 
 #define DRM_TEGRA_GEM_CREATE		0x00
 #define DRM_TEGRA_GEM_MMAP		0x01
-#define DRM_TEGRA_SYNCPT_READ		0x02
-#define DRM_TEGRA_SYNCPT_INCR		0x03
-#define DRM_TEGRA_SYNCPT_WAIT		0x04
-#define DRM_TEGRA_OPEN_CHANNEL		0x05
-#define DRM_TEGRA_CLOSE_CHANNEL		0x06
-#define DRM_TEGRA_GET_SYNCPT		0x07
-#define DRM_TEGRA_SUBMIT		0x08
-#define DRM_TEGRA_GET_SYNCPT_BASE	0x09
-#define DRM_TEGRA_GEM_SET_TILING	0x0a
-#define DRM_TEGRA_GEM_GET_TILING	0x0b
-#define DRM_TEGRA_GEM_SET_FLAGS		0x0c
-#define DRM_TEGRA_GEM_GET_FLAGS		0x0d
+#define DRM_TEGRA_OPEN_CHANNEL		0x02
+#define DRM_TEGRA_CLOSE_CHANNEL		0x03
+#define DRM_TEGRA_SUBMIT		0x04
 
 #define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
 #define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
-#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
-#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
-#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
 #define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
 #define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel)
-#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
 #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
-#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
-#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
-#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
-#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
-#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
 
 #if defined(__cplusplus)
 }
diff --git a/meson.build b/meson.build
index 501957e35e1a..876c0e3b1688 100644
--- a/meson.build
+++ b/meson.build
@@ -1164,11 +1164,13 @@ dep_libdrm_amdgpu = null_dep
 dep_libdrm_radeon = null_dep
 dep_libdrm_nouveau = null_dep
 dep_libdrm_intel = null_dep
+dep_libdrm_tegra = null_dep
 
 _drm_amdgpu_ver = '2.4.99'
 _drm_radeon_ver = '2.4.71'
 _drm_nouveau_ver = '2.4.66'
 _drm_intel_ver = '2.4.75'
+_drm_tegra_ver = '2.4.75' # XXX
 _drm_ver = '2.4.81'
 
 _libdrm_checks = [
@@ -1177,6 +1179,7 @@ _libdrm_checks = [
   ['radeon', (with_gallium_radeonsi or with_dri_r100 or with_dri_r200 or
               with_gallium_r300 or with_gallium_r600)],
   ['nouveau', (with_gallium_nouveau or with_dri_nouveau)],
+  ['tegra', with_gallium_tegra],
 ]
 
 # VC4 only needs core libdrm support of this version, not a libdrm_vc4
diff --git a/src/gallium/auxiliary/util/u_debug_gallium.c b/src/gallium/auxiliary/util/u_debug_gallium.c
index 6ac84b556a0f..88d8e0829489 100644
--- a/src/gallium/auxiliary/util/u_debug_gallium.c
+++ b/src/gallium/auxiliary/util/u_debug_gallium.c
@@ -117,4 +117,86 @@ debug_print_flush_flags(const char *msg, enum pipe_flush_flags flags)
    debug_printf("%s: %s\n", msg, debug_dump_flags(names, flags));
 }
 
+void debug_print_video_format(const char *msg, enum pipe_video_format format)
+{
+   static const struct debug_named_value names[] = {
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_FORMAT_UNKNOWN),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_FORMAT_MPEG12),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_FORMAT_MPEG4),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_FORMAT_VC1),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_FORMAT_MPEG4_AVC),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_FORMAT_HEVC),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_FORMAT_JPEG),
+      DEBUG_NAMED_VALUE_END
+   };
+
+   debug_printf("%s: %s\n", msg, debug_dump_enum(names, format));
+}
+
+void debug_print_video_profile(const char *msg, enum pipe_video_profile profile)
+{
+   static const struct debug_named_value names[] = {
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_UNKNOWN),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_MPEG1),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_MPEG2_SIMPLE),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_MPEG2_MAIN),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_MPEG4_SIMPLE),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_VC1_SIMPLE),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_VC1_MAIN),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_VC1_ADVANCED),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_MPEG4_AVC_EXTENDED),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH10),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH422),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH444),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_HEVC_MAIN),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_HEVC_MAIN_10),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_HEVC_MAIN_STILL),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_HEVC_MAIN_12),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_HEVC_MAIN_444),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_PROFILE_JPEG_BASELINE),
+      DEBUG_NAMED_VALUE_END
+   };
+
+   debug_printf("%s: %s\n", msg, debug_dump_enum(names, profile));
+}
+
+void debug_print_video_entrypoint(const char *msg,
+                                  enum pipe_video_entrypoint entrypoint)
+{
+   static const struct debug_named_value names[] = {
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_ENTRYPOINT_UNKNOWN),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_ENTRYPOINT_BITSTREAM),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_ENTRYPOINT_IDCT),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_ENTRYPOINT_MC),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_ENTRYPOINT_ENCODE),
+      DEBUG_NAMED_VALUE_END
+   };
+
+   debug_printf("%s: %s\n", msg, debug_dump_enum(names, entrypoint));
+}
+
+void debug_print_video_cap(const char *msg, enum pipe_video_cap param)
+{
+   static const struct debug_named_value names[] = {
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_CAP_SUPPORTED),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_CAP_NPOT_TEXTURES),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_CAP_MAX_WIDTH),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_CAP_MAX_HEIGHT),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_CAP_PREFERED_FORMAT),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_CAP_PREFERS_INTERLACED),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_CAP_SUPPORTS_INTERLACED),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_CAP_MAX_LEVEL),
+      DEBUG_NAMED_VALUE(PIPE_VIDEO_CAP_STACKED_FRAMES),
+      DEBUG_NAMED_VALUE_END,
+   };
+
+   debug_printf("%s: %s\n", msg, debug_dump_enum(names, param));
+}
+
 #endif
diff --git a/src/gallium/auxiliary/util/u_debug_gallium.h b/src/gallium/auxiliary/util/u_debug_gallium.h
index 8edc75017fe1..a9087b18e9e7 100644
--- a/src/gallium/auxiliary/util/u_debug_gallium.h
+++ b/src/gallium/auxiliary/util/u_debug_gallium.h
@@ -30,6 +30,7 @@
 #define _U_DEBUG_GALLIUM_H_
 
 #include "pipe/p_defines.h"
+#include "pipe/p_video_enums.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -61,6 +62,19 @@ debug_print_usage_enum(const char *msg, enum pipe_resource_usage usage);
 void
 debug_print_flush_flags(const char *msg, enum pipe_flush_flags flags);
 
+void
+debug_print_video_format(const char *msg, enum pipe_video_format format);
+
+void
+debug_print_video_profile(const char *msg, enum pipe_video_profile profile);
+
+void
+debug_print_video_entrypoint(const char *msg,
+                             enum pipe_video_entrypoint entrypoint);
+
+void
+debug_print_video_cap(const char *msg, enum pipe_video_cap param);
+
 #endif
 
 #ifdef __cplusplus
diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h
index 808c2b8cfaf6..e3ed868266b6 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -413,6 +413,11 @@ enum pipe_flush_flags
 #define PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET (1 << 6)
 
 /**
+ * Create a video decoding context.
+ */
+#define PIPE_CONTEXT_VIDEO_ONLY        (1 << 6)
+
+/**
  * Flags for pipe_context::memory_barrier.
  */
 #define PIPE_BARRIER_MAPPED_BUFFER     (1 << 0)
@@ -696,7 +701,7 @@ enum pipe_cap
    PIPE_CAP_TEXTURE_SWIZZLE,
    PIPE_CAP_MAX_TEXTURE_2D_SIZE,
    PIPE_CAP_MAX_TEXTURE_3D_LEVELS,
-   PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS,
+   PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS, /* 10 */
    PIPE_CAP_TEXTURE_MIRROR_CLAMP,
    PIPE_CAP_BLEND_EQUATION_SEPARATE,
    PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS,
@@ -707,7 +712,7 @@ enum pipe_cap
    PIPE_CAP_INDEP_BLEND_FUNC,
    PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS,
    PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT,
-   PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT,
+   PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT, /* 20 */
    PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER,
    PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER,
    PIPE_CAP_DEPTH_CLIP_DISABLE,
@@ -718,7 +723,7 @@ enum pipe_cap
    PIPE_CAP_FRAGMENT_COLOR_CLAMPED,
    PIPE_CAP_MIXED_COLORBUFFER_FORMATS,
    PIPE_CAP_SEAMLESS_CUBE_MAP,
-   PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE,
+   PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE, /* 30 */
    PIPE_CAP_MIN_TEXEL_OFFSET,
    PIPE_CAP_MAX_TEXEL_OFFSET,
    PIPE_CAP_CONDITIONAL_RENDER,
@@ -728,7 +733,7 @@ enum pipe_cap
    PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME,
    PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS,
    PIPE_CAP_VERTEX_COLOR_UNCLAMPED,
-   PIPE_CAP_VERTEX_COLOR_CLAMPED,
+   PIPE_CAP_VERTEX_COLOR_CLAMPED, /* 40 */
    PIPE_CAP_GLSL_FEATURE_LEVEL,
    PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY,
    PIPE_CAP_ESSL_FEATURE_LEVEL,
@@ -740,7 +745,7 @@ enum pipe_cap
    PIPE_CAP_COMPUTE,
    PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT,
    PIPE_CAP_START_INSTANCE,
-   PIPE_CAP_QUERY_TIMESTAMP,
+   PIPE_CAP_QUERY_TIMESTAMP, /* 50 */
    PIPE_CAP_TEXTURE_MULTISAMPLE,
    PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT,
    PIPE_CAP_CUBE_MAP_ARRAY,
@@ -750,7 +755,7 @@ enum pipe_cap
    PIPE_CAP_TGSI_TEXCOORD,
    PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER,
    PIPE_CAP_QUERY_PIPELINE_STATISTICS,
-   PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK,
+   PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK, /* 60 */
    PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE,
    PIPE_CAP_MAX_VIEWPORTS,
    PIPE_CAP_ENDIANNESS,
@@ -760,7 +765,7 @@ enum pipe_cap
    PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS,
    PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS,
    PIPE_CAP_TEXTURE_GATHER_SM5,
-   PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT,
+   PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT, /* 70 */
    PIPE_CAP_FAKE_SW_MSAA,
    PIPE_CAP_TEXTURE_QUERY_LOD,
    PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET,
@@ -770,7 +775,7 @@ enum pipe_cap
    PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION,
    PIPE_CAP_MAX_VERTEX_STREAMS,
    PIPE_CAP_DRAW_INDIRECT,
-   PIPE_CAP_TGSI_FS_FINE_DERIVATIVE,
+   PIPE_CAP_TGSI_FS_FINE_DERIVATIVE, /* 80 */
    PIPE_CAP_VENDOR_ID,
    PIPE_CAP_DEVICE_ID,
    PIPE_CAP_ACCELERATED,
@@ -780,7 +785,7 @@ enum pipe_cap
    PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE,
    PIPE_CAP_SAMPLER_VIEW_TARGET,
    PIPE_CAP_CLIP_HALFZ,
-   PIPE_CAP_VERTEXID_NOBASE,
+   PIPE_CAP_VERTEXID_NOBASE, /* 90 */
    PIPE_CAP_POLYGON_OFFSET_CLAMP,
    PIPE_CAP_MULTISAMPLE_Z_RESOLVE,
    PIPE_CAP_RESOURCE_FROM_USER_MEMORY,
@@ -790,7 +795,7 @@ enum pipe_cap
    PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR,
    PIPE_CAP_DEPTH_BOUNDS_TEST,
    PIPE_CAP_TGSI_TXQS,
-   PIPE_CAP_FORCE_PERSAMPLE_INTERP,
+   PIPE_CAP_FORCE_PERSAMPLE_INTERP, /* 100 */
    PIPE_CAP_SHAREABLE_SHADERS,
    PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS,
    PIPE_CAP_CLEAR_TEXTURE,
@@ -801,7 +806,7 @@ enum pipe_cap
    PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL,
    PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL,
    PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL,
-   PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT,
+   PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT, /* 110 */
    PIPE_CAP_INVALIDATE_BUFFER,
    PIPE_CAP_GENERATE_MIPMAP,
    PIPE_CAP_STRING_MARKER,
@@ -811,7 +816,7 @@ enum pipe_cap
    PIPE_CAP_PCI_GROUP,
    PIPE_CAP_PCI_BUS,
    PIPE_CAP_PCI_DEVICE,
-   PIPE_CAP_PCI_FUNCTION,
+   PIPE_CAP_PCI_FUNCTION, /* 120 */
    PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT,
    PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR,
    PIPE_CAP_CULL_DISTANCE,
@@ -822,7 +827,7 @@ enum pipe_cap
    PIPE_CAP_VIEWPORT_SUBPIXEL_BITS,
    PIPE_CAP_RASTERIZER_SUBPIXEL_BITS,
    PIPE_CAP_MIXED_COLOR_DEPTH_BITS,
-   PIPE_CAP_TGSI_ARRAY_COMPONENTS,
+   PIPE_CAP_TGSI_ARRAY_COMPONENTS, /* 130 */
    PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS,
    PIPE_CAP_TGSI_CAN_READ_OUTPUTS,
    PIPE_CAP_NATIVE_FENCE_FD,
@@ -833,7 +838,7 @@ enum pipe_cap
    PIPE_CAP_DOUBLES,
    PIPE_CAP_INT64,
    PIPE_CAP_INT64_DIVMOD,
-   PIPE_CAP_TGSI_TEX_TXF_LZ,
+   PIPE_CAP_TGSI_TEX_TXF_LZ, /* 140 */
    PIPE_CAP_TGSI_CLOCK,
    PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE,
    PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE,
@@ -843,7 +848,7 @@ enum pipe_cap
    PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION,
    PIPE_CAP_POST_DEPTH_COVERAGE,
    PIPE_CAP_BINDLESS_TEXTURE,
-   PIPE_CAP_NIR_SAMPLERS_AS_DEREF,
+   PIPE_CAP_NIR_SAMPLERS_AS_DEREF, /* 150 */
    PIPE_CAP_QUERY_SO_OVERFLOW,
    PIPE_CAP_MEMOBJ,
    PIPE_CAP_LOAD_CONSTBUF,
@@ -854,7 +859,7 @@ enum pipe_cap
    PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET,
    PIPE_CAP_CONTEXT_PRIORITY_MASK,
    PIPE_CAP_FENCE_SIGNAL,
-   PIPE_CAP_CONSTBUF0_FLAGS,
+   PIPE_CAP_CONSTBUF0_FLAGS, /* 160 */
    PIPE_CAP_PACKED_UNIFORMS,
    PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES,
    PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES,
diff --git a/src/gallium/state_trackers/va/context.c b/src/gallium/state_trackers/va/context.c
index 2cb3a6c92684..9ddf1a8069f8 100644
--- a/src/gallium/state_trackers/va/context.c
+++ b/src/gallium/state_trackers/va/context.c
@@ -151,6 +151,7 @@ VA_DRIVER_INIT_FUNC(VADriverContextP ctx)
    if (!drv->vscreen)
       goto error_screen;
 
+   /* XXX PIPE_CONTEXT_VIDEO_ONLY */
    drv->pipe = pipe_create_multimedia_context(drv->vscreen->pscreen);
    if (!drv->pipe)
       goto error_pipe;
diff --git a/src/gallium/state_trackers/vdpau/device.c b/src/gallium/state_trackers/vdpau/device.c
index c5a3eeb6b303..58ca35a807f4 100644
--- a/src/gallium/state_trackers/vdpau/device.c
+++ b/src/gallium/state_trackers/vdpau/device.c
@@ -72,12 +72,18 @@ vdp_imp_device_create_x11(Display *display, int screen, VdpDevice *device,
    }
 
    pscreen = dev->vscreen->pscreen;
+   /* XXX PIPE_CONTEXT_VIDEO_ONLY */
    dev->context = pipe_create_multimedia_context(pscreen);
    if (!dev->context) {
       ret = VDP_STATUS_RESOURCES;
       goto no_context;
    }
 
+   debug_printf("  context: %p\n", dev->context);
+   pscreen = dev->context->screen;
+   dev->vscreen->pscreen = pscreen;
+   debug_printf("  screen: %p\n", pscreen);
+
    if (!pscreen->get_param(pscreen, PIPE_CAP_NPOT_TEXTURES)) {
       ret = VDP_STATUS_NO_IMPLEMENTATION;
       goto no_context;
diff --git a/src/gallium/state_trackers/vdpau/surface.c b/src/gallium/state_trackers/vdpau/surface.c
index e9d55a282e21..859cf0d3c15d 100644
--- a/src/gallium/state_trackers/vdpau/surface.c
+++ b/src/gallium/state_trackers/vdpau/surface.c
@@ -447,16 +447,20 @@ vlVdpVideoSurfaceClear(vlVdpSurface *vlsurf)
    surfaces = vlsurf->video_buffer->get_surfaces(vlsurf->video_buffer);
    for (i = 0; i < VL_MAX_SURFACES; ++i) {
       union pipe_color_union c = {};
+      struct pipe_context *pipe;
 
       if (!surfaces[i])
          continue;
 
+      pipe = surfaces[i]->context;
+
       if (i > !!vlsurf->templat.interlaced)
          c.f[0] = c.f[1] = c.f[2] = c.f[3] = 0.5f;
 
       pipe->clear_render_target(pipe, surfaces[i], &c, 0, 0,
                                 surfaces[i]->width, surfaces[i]->height, false);
    }
+   /* XXX do this on the same context as the ->clear_render_target() calls */
    pipe->flush(pipe, NULL, 0);
 }