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authorThierry Reding <treding@nvidia.com>2014-06-04 09:26:25 +0200
committerThierry Reding <treding@nvidia.com>2014-06-04 12:12:33 +0200
commita7426b06952338f3a10b30f22039780a493c7a61 (patch)
tree29b721727c7dd309c09af62ad91b41719189dfde /firmware/cxgb3/t3fw-7.10.0.bin.ihex
parent01de722e4387b7d227c8063e39504dddebec884b (diff)
HACK: drm/nouveau: prime: Pin buffer objects to VRAMHEADmaster
This is currently required to work around the lack of proper SMMU support on Tegra. Ideally buffer objects could always be pinned to GART and the SMMU will take care of mapping them to a linear I/O virtual address range for importers. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'firmware/cxgb3/t3fw-7.10.0.bin.ihex')
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