diff options
| author | Anusha Srivatsa <anusha.srivatsa@intel.com> | 2017-06-21 11:17:37 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-06-29 10:51:29 -0700 |
| commit | 4c98652cb5cd3b0ef3681b1a7b2892c14b7f5c34 (patch) | |
| tree | 29225b9b1a2bd6df68f4f28eeb3a81f6014e736b | |
| parent | 2b48faf30e03cdafccffd7d6c6a715c2f969fc31 (diff) | |
intel: PCI Ids for U SKU in CFL
Add the PCI IDs for U SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
| -rw-r--r-- | intel/intel_chipset.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index fed5a0d8..891b50fc 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -228,6 +228,10 @@ #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 +#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5 +#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6 +#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7 +#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ @@ -469,8 +473,14 @@ #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2) +#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4) + #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \ - IS_CFL_H(devid)) + IS_CFL_H(devid) || \ + IS_CFL_U(devid)) #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ IS_BROXTON(devid) || \ |