From 4585945bf1d348d006f7270beea3dae09fee3413 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 30 Nov 2015 22:07:53 +0100 Subject: clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output The configurable hdmi_ref output of the PLL block is derived from the tvdpll_594m clock signal via a configurable PLL post-divider. It is used as the PLL reference input to the HDMI PHY module. Signed-off-by: Philipp Zabel Acked-by: James Liao Acked-by: Stephen Boyd --- drivers/clk/mediatek/clk-mt8173.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 85c0bfc626ae..cf4fcb61ed28 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -1095,6 +1095,11 @@ static void __init mtk_apmixedsys_init(struct device_node *node) clk_data->clks[cku->id] = clk; } + clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0, + base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO, + NULL); + clk_data->clks[CLK_APMIXED_HDMI_REF] = clk; + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", -- cgit v1.2.3