From a1355e530173021099d0401f3294414382189dbd Mon Sep 17 00:00:00 2001 From: Andrew Morton Date: Wed, 30 Apr 2008 11:40:17 -0300 Subject: V4L/DVB (7800): tuner_symbol_probe(): don't do symbol_put() if symbol_request() failed Because it goes BUG. Signed-off-by: Andrew Morton Acked-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/tuner-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/video/tuner-core.c b/drivers/media/video/tuner-core.c index 6bf104ea051d..c8cd718675ab 100644 --- a/drivers/media/video/tuner-core.c +++ b/drivers/media/video/tuner-core.c @@ -40,11 +40,11 @@ typeof(&FUNCTION) __a = symbol_request(FUNCTION); \ if (__a) { \ __r = (int) __a(ARGS); \ + symbol_put(FUNCTION); \ } else { \ printk(KERN_ERR "TUNER: Unable to find " \ "symbol "#FUNCTION"()\n"); \ } \ - symbol_put(FUNCTION); \ __r; \ }) -- cgit v1.2.3 From d557dab5de82edfe5bab9a1964dfc5cf2b2b6833 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 30 Apr 2008 15:27:55 -0300 Subject: V4L/DVB (7801): saa7134: detach frontend, if tuner or Diseqc attach fails Before this patch, an error at tuner or diseqc were discarded by the driver. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/saa7134/saa7134-dvb.c | 141 +++++++++++++++++++++--------- 1 file changed, 101 insertions(+), 40 deletions(-) diff --git a/drivers/media/video/saa7134/saa7134-dvb.c b/drivers/media/video/saa7134/saa7134-dvb.c index 2d16be2259db..2a9aa726e984 100644 --- a/drivers/media/video/saa7134/saa7134-dvb.c +++ b/drivers/media/video/saa7134/saa7134-dvb.c @@ -538,19 +538,23 @@ static int philips_tda827x_tuner_sleep(struct dvb_frontend *fe) return 0; } -static void configure_tda827x_fe(struct saa7134_dev *dev, struct tda1004x_config *cdec_conf, - struct tda827x_config *tuner_conf) +static int configure_tda827x_fe(struct saa7134_dev *dev, + struct tda1004x_config *cdec_conf, + struct tda827x_config *tuner_conf) { dev->dvb.frontend = dvb_attach(tda10046_attach, cdec_conf, &dev->i2c_adap); if (dev->dvb.frontend) { if (cdec_conf->i2c_gate) dev->dvb.frontend->ops.i2c_gate_ctrl = tda8290_i2c_gate_ctrl; - if (dvb_attach(tda827x_attach, dev->dvb.frontend, cdec_conf->tuner_address, - &dev->i2c_adap, tuner_conf) == NULL) { - wprintk("no tda827x tuner found at addr: %02x\n", + if (dvb_attach(tda827x_attach, dev->dvb.frontend, + cdec_conf->tuner_address, + &dev->i2c_adap, tuner_conf)) + return 0; + + wprintk("no tda827x tuner found at addr: %02x\n", cdec_conf->tuner_address); - } } + return -EINVAL; } /* ------------------------------------------------------------------ */ @@ -997,7 +1001,9 @@ static int dvb_init(struct saa7134_dev *dev) break; case SAA7134_BOARD_FLYDVBTDUO: case SAA7134_BOARD_FLYDVBT_DUO_CARDBUS: - configure_tda827x_fe(dev, &tda827x_lifeview_config, &tda827x_cfg_0); + if (configure_tda827x_fe(dev, &tda827x_lifeview_config, + &tda827x_cfg_0) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_PHILIPS_EUROPA: case SAA7134_BOARD_VIDEOMATE_DVBT_300: @@ -1022,36 +1028,52 @@ static int dvb_init(struct saa7134_dev *dev) } break; case SAA7134_BOARD_KWORLD_DVBT_210: - configure_tda827x_fe(dev, &kworld_dvb_t_210_config, &tda827x_cfg_2); + if (configure_tda827x_fe(dev, &kworld_dvb_t_210_config, + &tda827x_cfg_2) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_PHILIPS_TIGER: - configure_tda827x_fe(dev, &philips_tiger_config, &tda827x_cfg_0); + if (configure_tda827x_fe(dev, &philips_tiger_config, + &tda827x_cfg_0) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_PINNACLE_PCTV_310i: - configure_tda827x_fe(dev, &pinnacle_pctv_310i_config, &tda827x_cfg_1); + if (configure_tda827x_fe(dev, &pinnacle_pctv_310i_config, + &tda827x_cfg_1) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_HAUPPAUGE_HVR1110: - configure_tda827x_fe(dev, &hauppauge_hvr_1110_config, &tda827x_cfg_1); + if (configure_tda827x_fe(dev, &hauppauge_hvr_1110_config, + &tda827x_cfg_1) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_ASUSTeK_P7131_DUAL: - configure_tda827x_fe(dev, &asus_p7131_dual_config, &tda827x_cfg_0); + if (configure_tda827x_fe(dev, &asus_p7131_dual_config, + &tda827x_cfg_0) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_FLYDVBT_LR301: - configure_tda827x_fe(dev, &tda827x_lifeview_config, &tda827x_cfg_0); + if (configure_tda827x_fe(dev, &tda827x_lifeview_config, + &tda827x_cfg_0) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_FLYDVB_TRIO: - if(! use_frontend) { /* terrestrial */ - configure_tda827x_fe(dev, &lifeview_trio_config, &tda827x_cfg_0); + if (!use_frontend) { /* terrestrial */ + if (configure_tda827x_fe(dev, &lifeview_trio_config, + &tda827x_cfg_0) < 0) + goto dettach_frontend; } else { /* satellite */ dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs, &dev->i2c_adap); if (dev->dvb.frontend) { if (dvb_attach(tda826x_attach, dev->dvb.frontend, 0x63, &dev->i2c_adap, 0) == NULL) { wprintk("%s: Lifeview Trio, No tda826x found!\n", __func__); + goto dettach_frontend; } if (dvb_attach(isl6421_attach, dev->dvb.frontend, &dev->i2c_adap, 0x08, 0, 0) == NULL) { wprintk("%s: Lifeview Trio, No ISL6421 found!\n", __func__); + goto dettach_frontend; } } } @@ -1067,15 +1089,20 @@ static int dvb_init(struct saa7134_dev *dev) &ads_duo_cfg) == NULL) { wprintk("no tda827x tuner found at addr: %02x\n", ads_tech_duo_config.tuner_address); + goto dettach_frontend; } } break; case SAA7134_BOARD_TEVION_DVBT_220RF: - configure_tda827x_fe(dev, &tevion_dvbt220rf_config, &tda827x_cfg_0); + if (configure_tda827x_fe(dev, &tevion_dvbt220rf_config, + &tda827x_cfg_0) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_MEDION_MD8800_QUADRO: if (!use_frontend) { /* terrestrial */ - configure_tda827x_fe(dev, &md8800_dvbt_config, &tda827x_cfg_0); + if (configure_tda827x_fe(dev, &md8800_dvbt_config, + &tda827x_cfg_0) < 0) + goto dettach_frontend; } else { /* satellite */ dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs, &dev->i2c_adap); @@ -1086,16 +1113,20 @@ static int dvb_init(struct saa7134_dev *dev) struct i2c_msg msg = {.addr = 0x08, .flags = 0, .len = 1}; if (dvb_attach(tda826x_attach, dev->dvb.frontend, - 0x60, &dev->i2c_adap, 0) == NULL) + 0x60, &dev->i2c_adap, 0) == NULL) { wprintk("%s: Medion Quadro, no tda826x " "found !\n", __func__); + goto dettach_frontend; + } if (dev_id != 0x08) { /* we need to open the i2c gate (we know it exists) */ fe->ops.i2c_gate_ctrl(fe, 1); if (dvb_attach(isl6405_attach, fe, - &dev->i2c_adap, 0x08, 0, 0) == NULL) + &dev->i2c_adap, 0x08, 0, 0) == NULL) { wprintk("%s: Medion Quadro, no ISL6405 " "found !\n", __func__); + goto dettach_frontend; + } if (dev_id == 0x07) { /* fire up the 2nd section of the LNB supply since we can't do this from the other section */ @@ -1117,19 +1148,17 @@ static int dvb_init(struct saa7134_dev *dev) case SAA7134_BOARD_AVERMEDIA_AVERTVHD_A180: dev->dvb.frontend = dvb_attach(nxt200x_attach, &avertvhda180, &dev->i2c_adap); - if (dev->dvb.frontend) { + if (dev->dvb.frontend) dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, NULL, DVB_PLL_TDHU2); - } break; case SAA7134_BOARD_KWORLD_ATSC110: dev->dvb.frontend = dvb_attach(nxt200x_attach, &kworldatsc110, &dev->i2c_adap); - if (dev->dvb.frontend) { + if (dev->dvb.frontend) dvb_attach(simple_tuner_attach, dev->dvb.frontend, &dev->i2c_adap, 0x61, TUNER_PHILIPS_TUV1236D); - } break; case SAA7134_BOARD_FLYDVBS_LR300: dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs, @@ -1138,10 +1167,12 @@ static int dvb_init(struct saa7134_dev *dev) if (dvb_attach(tda826x_attach, dev->dvb.frontend, 0x60, &dev->i2c_adap, 0) == NULL) { wprintk("%s: No tda826x found!\n", __func__); + goto dettach_frontend; } if (dvb_attach(isl6421_attach, dev->dvb.frontend, &dev->i2c_adap, 0x08, 0, 0) == NULL) { wprintk("%s: No ISL6421 found!\n", __func__); + goto dettach_frontend; } } break; @@ -1168,43 +1199,65 @@ static int dvb_init(struct saa7134_dev *dev) } break; case SAA7134_BOARD_CINERGY_HT_PCMCIA: - configure_tda827x_fe(dev, &cinergy_ht_config, &tda827x_cfg_0); + if (configure_tda827x_fe(dev, &cinergy_ht_config, + &tda827x_cfg_0) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_CINERGY_HT_PCI: - configure_tda827x_fe(dev, &cinergy_ht_pci_config, &tda827x_cfg_0); + if (configure_tda827x_fe(dev, &cinergy_ht_pci_config, + &tda827x_cfg_0) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_PHILIPS_TIGER_S: - configure_tda827x_fe(dev, &philips_tiger_s_config, &tda827x_cfg_2); + if (configure_tda827x_fe(dev, &philips_tiger_s_config, + &tda827x_cfg_2) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_ASUS_P7131_4871: - configure_tda827x_fe(dev, &asus_p7131_4871_config, &tda827x_cfg_2); + if (configure_tda827x_fe(dev, &asus_p7131_4871_config, + &tda827x_cfg_2) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_ASUSTeK_P7131_HYBRID_LNA: - configure_tda827x_fe(dev, &asus_p7131_hybrid_lna_config, &tda827x_cfg_2); + if (configure_tda827x_fe(dev, &asus_p7131_hybrid_lna_config, + &tda827x_cfg_2) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_AVERMEDIA_SUPER_007: - configure_tda827x_fe(dev, &avermedia_super_007_config, &tda827x_cfg_0); + if (configure_tda827x_fe(dev, &avermedia_super_007_config, + &tda827x_cfg_0) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_TWINHAN_DTV_DVB_3056: - configure_tda827x_fe(dev, &twinhan_dtv_dvb_3056_config, &tda827x_cfg_2_sw42); + if (configure_tda827x_fe(dev, &twinhan_dtv_dvb_3056_config, + &tda827x_cfg_2_sw42) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_PHILIPS_SNAKE: dev->dvb.frontend = dvb_attach(tda10086_attach, &flydvbs, &dev->i2c_adap); if (dev->dvb.frontend) { if (dvb_attach(tda826x_attach, dev->dvb.frontend, 0x60, - &dev->i2c_adap, 0) == NULL) + &dev->i2c_adap, 0) == NULL) { wprintk("%s: No tda826x found!\n", __func__); + goto dettach_frontend; + } if (dvb_attach(lnbp21_attach, dev->dvb.frontend, - &dev->i2c_adap, 0, 0) == NULL) + &dev->i2c_adap, 0, 0) == NULL) { wprintk("%s: No lnbp21 found!\n", __func__); + goto dettach_frontend; + } } break; case SAA7134_BOARD_CREATIX_CTX953: - configure_tda827x_fe(dev, &md8800_dvbt_config, &tda827x_cfg_0); + if (configure_tda827x_fe(dev, &md8800_dvbt_config, + &tda827x_cfg_0) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_MSI_TVANYWHERE_AD11: - configure_tda827x_fe(dev, &philips_tiger_s_config, &tda827x_cfg_2); + if (configure_tda827x_fe(dev, &philips_tiger_s_config, + &tda827x_cfg_2) < 0) + goto dettach_frontend; break; case SAA7134_BOARD_AVERMEDIA_CARDBUS_506: dev->dvb.frontend = dvb_attach(mt352_attach, @@ -1218,16 +1271,20 @@ static int dvb_init(struct saa7134_dev *dev) if (dev->dvb.frontend) { struct dvb_frontend *fe; if (dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60, - &dev->i2c_adap, DVB_PLL_PHILIPS_SD1878_TDA8261) == NULL) + &dev->i2c_adap, DVB_PLL_PHILIPS_SD1878_TDA8261) == NULL) { wprintk("%s: MD7134 DVB-S, no SD1878 " "found !\n", __func__); + goto dettach_frontend; + } /* we need to open the i2c gate (we know it exists) */ fe = dev->dvb.frontend; fe->ops.i2c_gate_ctrl(fe, 1); if (dvb_attach(isl6405_attach, fe, - &dev->i2c_adap, 0x08, 0, 0) == NULL) + &dev->i2c_adap, 0x08, 0, 0) == NULL) { wprintk("%s: MD7134 DVB-S, no ISL6405 " "found !\n", __func__); + goto dettach_frontend; + } fe->ops.i2c_gate_ctrl(fe, 0); dev->original_set_voltage = fe->ops.set_voltage; fe->ops.set_voltage = md8800_set_voltage; @@ -1254,10 +1311,7 @@ static int dvb_init(struct saa7134_dev *dev) if (!fe) { printk(KERN_ERR "%s/2: xc3028 attach failed\n", dev->name); - dvb_frontend_detach(dev->dvb.frontend); - dvb_unregister_frontend(dev->dvb.frontend); - dev->dvb.frontend = NULL; - return -1; + goto dettach_frontend; } } @@ -1282,6 +1336,13 @@ static int dvb_init(struct saa7134_dev *dev) dev->dvb.frontend->ops.tuner_ops.sleep(dev->dvb.frontend); } return ret; + +dettach_frontend: + dvb_frontend_detach(dev->dvb.frontend); + dvb_unregister_frontend(dev->dvb.frontend); + dev->dvb.frontend = NULL; + + return -1; } static int dvb_fini(struct saa7134_dev *dev) -- cgit v1.2.3 From 09fee5f8211fc0a586187c4a0db7f5f42a4e333f Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 30 Apr 2008 15:29:57 -0300 Subject: V4L/DVB (7802): tuner: Failures at tuner_attach were producing OOPS As reported by Mike Galbraith : [ 13.666587] TUNER: Unable to find symbol tda829x_probe() [ 13.674638] tuner' 1-004b: chip found @ 0x96 (saa7133[0]) [ 13.691175] DVB: Unable to find symbol tda9887_attach() [ 13.698968] BUG: unable to handle kernel NULL pointer dereference at 0000000000000000 [ 13.709509] IP: [] strlcpy+0x11/0x36 [ 13.711135] PGD be167067 PUD be140067 PMD 0 [ 13.711137] Oops: 0000 [1] SMP Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/tuner-core.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/drivers/media/video/tuner-core.c b/drivers/media/video/tuner-core.c index c8cd718675ab..b5dacde023ee 100644 --- a/drivers/media/video/tuner-core.c +++ b/drivers/media/video/tuner-core.c @@ -340,16 +340,6 @@ static void tuner_i2c_address_check(struct tuner *t) tuner_warn("====================== WARNING! ======================\n"); } -static void attach_tda829x(struct tuner *t) -{ - struct tda829x_config cfg = { - .lna_cfg = t->config, - .tuner_callback = t->tuner_callback, - }; - dvb_attach(tda829x_attach, - &t->fe, t->i2c->adapter, t->i2c->addr, &cfg); -} - static struct xc5000_config xc5000_cfg; static void set_type(struct i2c_client *c, unsigned int type, @@ -385,12 +375,19 @@ static void set_type(struct i2c_client *c, unsigned int type, switch (t->type) { case TUNER_MT2032: - dvb_attach(microtune_attach, - &t->fe, t->i2c->adapter, t->i2c->addr); + if (!dvb_attach(microtune_attach, + &t->fe, t->i2c->adapter, t->i2c->addr)) + goto attach_failed; break; case TUNER_PHILIPS_TDA8290: { - attach_tda829x(t); + struct tda829x_config cfg = { + .lna_cfg = t->config, + .tuner_callback = t->tuner_callback, + }; + if (!dvb_attach(tda829x_attach, &t->fe, t->i2c->adapter, + t->i2c->addr, &cfg)) + goto attach_failed; break; } case TUNER_TEA5767: @@ -441,8 +438,9 @@ static void set_type(struct i2c_client *c, unsigned int type, break; } case TUNER_TDA9887: - dvb_attach(tda9887_attach, - &t->fe, t->i2c->adapter, t->i2c->addr); + if (!dvb_attach(tda9887_attach, + &t->fe, t->i2c->adapter, t->i2c->addr)) + goto attach_failed; break; case TUNER_XC5000: { -- cgit v1.2.3 From b538d28c2e326ed226096408dce4d9469d7ffa39 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 30 Apr 2008 15:45:00 -0300 Subject: V4L/DVB (7804): tea5767: Fix error logic As pointed by Andrew Morton, the error testing were wrong. After reviewing tea5767, it were returning a positive value for errors. So, the double errors were cancelling each other. This patch fix it properly. It also considers any positive value as ok, on tuner-core. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/tea5767.c | 6 +++--- drivers/media/video/tuner-core.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/media/common/tuners/tea5767.c b/drivers/media/common/tuners/tea5767.c index f6e7d7ad8424..1f5646334a8f 100644 --- a/drivers/media/common/tuners/tea5767.c +++ b/drivers/media/common/tuners/tea5767.c @@ -373,14 +373,14 @@ int tea5767_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr) if ((rc = tuner_i2c_xfer_recv(&i2c, buffer, 7))< 5) { printk(KERN_WARNING "It is not a TEA5767. Received %i bytes.\n", rc); - return EINVAL; + return -EINVAL; } /* If all bytes are the same then it's a TV tuner and not a tea5767 */ if (buffer[0] == buffer[1] && buffer[0] == buffer[2] && buffer[0] == buffer[3] && buffer[0] == buffer[4]) { printk(KERN_WARNING "All bytes are equal. It is not a TEA5767\n"); - return EINVAL; + return -EINVAL; } /* Status bytes: @@ -390,7 +390,7 @@ int tea5767_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr) */ if (((buffer[3] & 0x0f) != 0x00) || (buffer[4] != 0x00)) { printk(KERN_WARNING "Chip ID is not zero. It is not a TEA5767\n"); - return EINVAL; + return -EINVAL; } diff --git a/drivers/media/video/tuner-core.c b/drivers/media/video/tuner-core.c index b5dacde023ee..4ca686fad557 100644 --- a/drivers/media/video/tuner-core.c +++ b/drivers/media/video/tuner-core.c @@ -1165,7 +1165,7 @@ static int tuner_probe(struct i2c_client *client, /* If chip is not tda8290, don't register. since it can be tda9887*/ if (tuner_symbol_probe(tda829x_probe, t->i2c->adapter, - t->i2c->addr) == 0) { + t->i2c->addr) >= 0) { tuner_dbg("tda829x detected\n"); } else { /* Default is being tda9887 */ @@ -1179,7 +1179,7 @@ static int tuner_probe(struct i2c_client *client, case 0x60: if (tuner_symbol_probe(tea5767_autodetection, t->i2c->adapter, t->i2c->addr) - != EINVAL) { + >= 0) { t->type = TUNER_TEA5767; t->mode_mask = T_RADIO; t->mode = T_STANDBY; -- cgit v1.2.3 From f50090fc947e82464b4a033c9eff1898cb0676b5 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 30 Apr 2008 18:13:05 -0300 Subject: V4L/DVB (7805): saa7134: dvb_unregister_frontend() shouldn't be called, if not registered yet Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/saa7134/saa7134-dvb.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/media/video/saa7134/saa7134-dvb.c b/drivers/media/video/saa7134/saa7134-dvb.c index 2a9aa726e984..469f93aac008 100644 --- a/drivers/media/video/saa7134/saa7134-dvb.c +++ b/drivers/media/video/saa7134/saa7134-dvb.c @@ -1339,7 +1339,6 @@ static int dvb_init(struct saa7134_dev *dev) dettach_frontend: dvb_frontend_detach(dev->dvb.frontend); - dvb_unregister_frontend(dev->dvb.frontend); dev->dvb.frontend = NULL; return -1; -- cgit v1.2.3 From 6430a5a368208ae6c4bcd13e1f06460c96af66be Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 30 Apr 2008 18:13:46 -0300 Subject: V4L/DVB (7806): em28xx: dvb_unregister_frontend() shouldn't be called, if not registered yet Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/em28xx/em28xx-dvb.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/media/video/em28xx/em28xx-dvb.c b/drivers/media/video/em28xx/em28xx-dvb.c index 7df81575b7f2..8cf4983f0039 100644 --- a/drivers/media/video/em28xx/em28xx-dvb.c +++ b/drivers/media/video/em28xx/em28xx-dvb.c @@ -251,7 +251,6 @@ static int attach_xc3028(u8 addr, struct em28xx *dev) printk(KERN_ERR "%s/2: xc3028 attach failed\n", dev->name); dvb_frontend_detach(dev->dvb->frontend); - dvb_unregister_frontend(dev->dvb->frontend); dev->dvb->frontend = NULL; return -EINVAL; } -- cgit v1.2.3 From 0590d91c413fb5144608d69f50710064360aeec8 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 30 Apr 2008 18:14:36 -0300 Subject: V4L/DVB (7807): cx88: Fix error handling, when dvb_attach() fails Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/cx88/cx88-dvb.c | 251 +++++++++++++++++++----------------- 1 file changed, 134 insertions(+), 117 deletions(-) diff --git a/drivers/media/video/cx88/cx88-dvb.c b/drivers/media/video/cx88/cx88-dvb.c index 1c7fe6862a60..75e2e58349ef 100644 --- a/drivers/media/video/cx88/cx88-dvb.c +++ b/drivers/media/video/cx88/cx88-dvb.c @@ -509,9 +509,6 @@ static int attach_xc3028(u8 addr, struct cx8802_dev *dev) if (!fe) { printk(KERN_ERR "%s/2: xc3028 attach failed\n", dev->core->name); - dvb_frontend_detach(dev->dvb.frontend); - dvb_unregister_frontend(dev->dvb.frontend); - dev->dvb.frontend = NULL; return -EINVAL; } @@ -523,20 +520,23 @@ static int attach_xc3028(u8 addr, struct cx8802_dev *dev) static int dvb_register(struct cx8802_dev *dev) { + struct cx88_core *core = dev->core; + /* init struct videobuf_dvb */ - dev->dvb.name = dev->core->name; + dev->dvb.name = core->name; dev->ts_gen_cntrl = 0x0c; /* init frontend */ - switch (dev->core->boardnr) { + switch (core->boardnr) { case CX88_BOARD_HAUPPAUGE_DVB_T1: dev->dvb.frontend = dvb_attach(cx22702_attach, &connexant_refboard_config, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, - &dev->core->i2c_adap, - DVB_PLL_THOMSON_DTT759X); + if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, + 0x61, &core->i2c_adap, + DVB_PLL_THOMSON_DTT759X)) + goto frontend_detach; } break; case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1: @@ -545,11 +545,12 @@ static int dvb_register(struct cx8802_dev *dev) case CX88_BOARD_WINFAST_DTV1000: dev->dvb.frontend = dvb_attach(cx22702_attach, &connexant_refboard_config, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60, - &dev->core->i2c_adap, - DVB_PLL_THOMSON_DTT7579); + if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, + 0x60, &core->i2c_adap, + DVB_PLL_THOMSON_DTT7579)) + goto frontend_detach; } break; case CX88_BOARD_WINFAST_DTV2000H: @@ -559,29 +560,32 @@ static int dvb_register(struct cx8802_dev *dev) case CX88_BOARD_HAUPPAUGE_HVR3000: dev->dvb.frontend = dvb_attach(cx22702_attach, &hauppauge_hvr_config, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(simple_tuner_attach, dev->dvb.frontend, - &dev->core->i2c_adap, 0x61, - TUNER_PHILIPS_FMD1216ME_MK3); + if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, + &core->i2c_adap, 0x61, + TUNER_PHILIPS_FMD1216ME_MK3)) + goto frontend_detach; } break; case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS: dev->dvb.frontend = dvb_attach(mt352_attach, &dvico_fusionhdtv, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60, - NULL, DVB_PLL_THOMSON_DTT7579); + if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, + 0x60, NULL, DVB_PLL_THOMSON_DTT7579)) + goto frontend_detach; break; } /* ZL10353 replaces MT352 on later cards */ dev->dvb.frontend = dvb_attach(zl10353_attach, &dvico_fusionhdtv_plus_v1_1, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60, - NULL, DVB_PLL_THOMSON_DTT7579); + if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, + 0x60, NULL, DVB_PLL_THOMSON_DTT7579)) + goto frontend_detach; } break; case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL: @@ -589,28 +593,31 @@ static int dvb_register(struct cx8802_dev *dev) * compatible, with a slightly different MT352 AGC gain. */ dev->dvb.frontend = dvb_attach(mt352_attach, &dvico_fusionhdtv_dual, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, - NULL, DVB_PLL_THOMSON_DTT7579); + if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, + 0x61, NULL, DVB_PLL_THOMSON_DTT7579)) + goto frontend_detach; break; } /* ZL10353 replaces MT352 on later cards */ dev->dvb.frontend = dvb_attach(zl10353_attach, &dvico_fusionhdtv_plus_v1_1, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, - NULL, DVB_PLL_THOMSON_DTT7579); + if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, + 0x61, NULL, DVB_PLL_THOMSON_DTT7579)) + goto frontend_detach; } break; case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1: dev->dvb.frontend = dvb_attach(mt352_attach, &dvico_fusionhdtv, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, - NULL, DVB_PLL_LG_Z201); + if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, + 0x61, NULL, DVB_PLL_LG_Z201)) + goto frontend_detach; } break; case CX88_BOARD_KWORLD_DVB_T: @@ -618,10 +625,11 @@ static int dvb_register(struct cx8802_dev *dev) case CX88_BOARD_ADSTECH_DVB_T_PCI: dev->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_config, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61, - NULL, DVB_PLL_UNKNOWN_1); + if (!dvb_attach(dvb_pll_attach, dev->dvb.frontend, + 0x61, NULL, DVB_PLL_UNKNOWN_1)) + goto frontend_detach; } break; case CX88_BOARD_DNTV_LIVE_DVB_T_PRO: @@ -630,32 +638,35 @@ static int dvb_register(struct cx8802_dev *dev) dev->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config, &dev->vp3054->adap); if (dev->dvb.frontend != NULL) { - dvb_attach(simple_tuner_attach, dev->dvb.frontend, - &dev->core->i2c_adap, 0x61, - TUNER_PHILIPS_FMD1216ME_MK3); + if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, + &core->i2c_adap, 0x61, + TUNER_PHILIPS_FMD1216ME_MK3)) + goto frontend_detach; } #else - printk(KERN_ERR "%s/2: built without vp3054 support\n", dev->core->name); + printk(KERN_ERR "%s/2: built without vp3054 support\n", + core->name); #endif break; case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID: dev->dvb.frontend = dvb_attach(zl10353_attach, &dvico_fusionhdtv_hybrid, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(simple_tuner_attach, dev->dvb.frontend, - &dev->core->i2c_adap, 0x61, - TUNER_THOMSON_FE6600); + if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, + &core->i2c_adap, 0x61, + TUNER_THOMSON_FE6600)) + goto frontend_detach; } break; case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO: dev->dvb.frontend = dvb_attach(zl10353_attach, &dvico_fusionhdtv_xc3028, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend == NULL) dev->dvb.frontend = dvb_attach(mt352_attach, &dvico_fusionhdtv_mt352_xc3028, - &dev->core->i2c_adap); + &core->i2c_adap); /* * On this board, the demod provides the I2C bus pullup. * We must not permit gate_ctrl to be performed, or @@ -668,19 +679,18 @@ static int dvb_register(struct cx8802_dev *dev) break; case CX88_BOARD_PCHDTV_HD3000: dev->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(simple_tuner_attach, dev->dvb.frontend, - &dev->core->i2c_adap, 0x61, - TUNER_THOMSON_DTT761X); + if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, + &core->i2c_adap, 0x61, + TUNER_THOMSON_DTT761X)) + goto frontend_detach; } break; case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q: dev->ts_gen_cntrl = 0x08; - { - /* Do a hardware reset of chip before using it. */ - struct cx88_core *core = dev->core; + /* Do a hardware reset of chip before using it. */ cx_clear(MO_GP0_IO, 1); mdelay(100); cx_set(MO_GP0_IO, 1); @@ -690,139 +700,138 @@ static int dvb_register(struct cx8802_dev *dev) fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set; dev->dvb.frontend = dvb_attach(lgdt330x_attach, &fusionhdtv_3_gold, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(simple_tuner_attach, dev->dvb.frontend, - &dev->core->i2c_adap, 0x61, - TUNER_MICROTUNE_4042FI5); - } + if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, + &core->i2c_adap, 0x61, + TUNER_MICROTUNE_4042FI5)) + goto frontend_detach; } break; case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T: dev->ts_gen_cntrl = 0x08; - { - /* Do a hardware reset of chip before using it. */ - struct cx88_core *core = dev->core; + /* Do a hardware reset of chip before using it. */ cx_clear(MO_GP0_IO, 1); mdelay(100); cx_set(MO_GP0_IO, 9); mdelay(200); dev->dvb.frontend = dvb_attach(lgdt330x_attach, &fusionhdtv_3_gold, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(simple_tuner_attach, dev->dvb.frontend, - &dev->core->i2c_adap, 0x61, - TUNER_THOMSON_DTT761X); - } + if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, + &core->i2c_adap, 0x61, + TUNER_THOMSON_DTT761X)) + goto frontend_detach; } break; case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD: dev->ts_gen_cntrl = 0x08; - { - /* Do a hardware reset of chip before using it. */ - struct cx88_core *core = dev->core; + /* Do a hardware reset of chip before using it. */ cx_clear(MO_GP0_IO, 1); mdelay(100); cx_set(MO_GP0_IO, 1); mdelay(200); dev->dvb.frontend = dvb_attach(lgdt330x_attach, &fusionhdtv_5_gold, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(simple_tuner_attach, dev->dvb.frontend, - &dev->core->i2c_adap, 0x61, - TUNER_LG_TDVS_H06XF); - dvb_attach(tda9887_attach, dev->dvb.frontend, - &dev->core->i2c_adap, 0x43); - } + if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, + &core->i2c_adap, 0x61, + TUNER_LG_TDVS_H06XF)) + goto frontend_detach; + if (!dvb_attach(tda9887_attach, dev->dvb.frontend, + &core->i2c_adap, 0x43)) + goto frontend_detach; } break; case CX88_BOARD_PCHDTV_HD5500: dev->ts_gen_cntrl = 0x08; - { - /* Do a hardware reset of chip before using it. */ - struct cx88_core *core = dev->core; + /* Do a hardware reset of chip before using it. */ cx_clear(MO_GP0_IO, 1); mdelay(100); cx_set(MO_GP0_IO, 1); mdelay(200); dev->dvb.frontend = dvb_attach(lgdt330x_attach, &pchdtv_hd5500, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(simple_tuner_attach, dev->dvb.frontend, - &dev->core->i2c_adap, 0x61, - TUNER_LG_TDVS_H06XF); - dvb_attach(tda9887_attach, dev->dvb.frontend, - &dev->core->i2c_adap, 0x43); - } + if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, + &core->i2c_adap, 0x61, + TUNER_LG_TDVS_H06XF)) + goto frontend_detach; + if (!dvb_attach(tda9887_attach, dev->dvb.frontend, + &core->i2c_adap, 0x43)) + goto frontend_detach; } break; case CX88_BOARD_ATI_HDTVWONDER: dev->dvb.frontend = dvb_attach(nxt200x_attach, &ati_hdtvwonder, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { - dvb_attach(simple_tuner_attach, dev->dvb.frontend, - &dev->core->i2c_adap, 0x61, - TUNER_PHILIPS_TUV1236D); + if (!dvb_attach(simple_tuner_attach, dev->dvb.frontend, + &core->i2c_adap, 0x61, + TUNER_PHILIPS_TUV1236D)) + goto frontend_detach; } break; case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1: case CX88_BOARD_HAUPPAUGE_NOVASE2_S1: dev->dvb.frontend = dvb_attach(cx24123_attach, &hauppauge_novas_config, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend) { - dvb_attach(isl6421_attach, dev->dvb.frontend, - &dev->core->i2c_adap, 0x08, 0x00, 0x00); + if (!dvb_attach(isl6421_attach, dev->dvb.frontend, + &core->i2c_adap, 0x08, 0x00, 0x00)) + goto frontend_detach; } break; case CX88_BOARD_KWORLD_DVBS_100: dev->dvb.frontend = dvb_attach(cx24123_attach, &kworld_dvbs_100_config, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend) { - dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage; + core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage; dev->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage; } break; case CX88_BOARD_GENIATECH_DVBS: dev->dvb.frontend = dvb_attach(cx24123_attach, &geniatech_dvbs_config, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend) { - dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage; + core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage; dev->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage; } break; case CX88_BOARD_PINNACLE_PCTV_HD_800i: dev->dvb.frontend = dvb_attach(s5h1409_attach, &pinnacle_pctv_hd_800i_config, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { /* tuner_config.video_dev must point to * i2c_adap.algo_data */ pinnacle_pctv_hd_800i_tuner_config.priv = - dev->core->i2c_adap.algo_data; - dvb_attach(xc5000_attach, dev->dvb.frontend, - &dev->core->i2c_adap, - &pinnacle_pctv_hd_800i_tuner_config); + core->i2c_adap.algo_data; + if (!dvb_attach(xc5000_attach, dev->dvb.frontend, + &core->i2c_adap, + &pinnacle_pctv_hd_800i_tuner_config)) + goto frontend_detach; } break; case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO: dev->dvb.frontend = dvb_attach(s5h1409_attach, &dvico_hdtv5_pci_nano_config, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { struct dvb_frontend *fe; struct xc2028_config cfg = { - .i2c_adap = &dev->core->i2c_adap, + .i2c_adap = &core->i2c_adap, .i2c_addr = 0x61, .callback = cx88_pci_nano_callback, }; @@ -841,50 +850,51 @@ static int dvb_register(struct cx8802_dev *dev) case CX88_BOARD_PINNACLE_HYBRID_PCTV: dev->dvb.frontend = dvb_attach(zl10353_attach, &cx88_geniatech_x8000_mt, - &dev->core->i2c_adap); + &core->i2c_adap); if (attach_xc3028(0x61, dev) < 0) - return -EINVAL; + goto frontend_detach; break; case CX88_BOARD_GENIATECH_X8000_MT: dev->ts_gen_cntrl = 0x00; dev->dvb.frontend = dvb_attach(zl10353_attach, &cx88_geniatech_x8000_mt, - &dev->core->i2c_adap); + &core->i2c_adap); if (attach_xc3028(0x61, dev) < 0) - return -EINVAL; + goto frontend_detach; break; case CX88_BOARD_KWORLD_ATSC_120: dev->dvb.frontend = dvb_attach(s5h1409_attach, &kworld_atsc_120_config, - &dev->core->i2c_adap); + &core->i2c_adap); if (attach_xc3028(0x61, dev) < 0) - return -EINVAL; + goto frontend_detach; break; case CX88_BOARD_DVICO_FUSIONHDTV_7_GOLD: dev->dvb.frontend = dvb_attach(s5h1411_attach, &dvico_fusionhdtv7_config, - &dev->core->i2c_adap); + &core->i2c_adap); if (dev->dvb.frontend != NULL) { /* tuner_config.video_dev must point to * i2c_adap.algo_data */ dvico_fusionhdtv7_tuner_config.priv = - dev->core->i2c_adap.algo_data; - dvb_attach(xc5000_attach, dev->dvb.frontend, - &dev->core->i2c_adap, - &dvico_fusionhdtv7_tuner_config); + core->i2c_adap.algo_data; + if (!dvb_attach(xc5000_attach, dev->dvb.frontend, + &core->i2c_adap, + &dvico_fusionhdtv7_tuner_config)) + goto frontend_detach; } break; default: printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card isn't supported yet\n", - dev->core->name); + core->name); break; } if (NULL == dev->dvb.frontend) { printk(KERN_ERR "%s/2: frontend initialization failed\n", - dev->core->name); + core->name); return -EINVAL; } @@ -892,11 +902,18 @@ static int dvb_register(struct cx8802_dev *dev) dev->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl; /* Put the analog decoder in standby to keep it quiet */ - cx88_call_i2c_clients (dev->core, TUNER_SET_STANDBY, NULL); + cx88_call_i2c_clients(core, TUNER_SET_STANDBY, NULL); /* register everything */ return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, &dev->pci->dev, adapter_nr); + +frontend_detach: + if (dev->dvb.frontend) { + dvb_frontend_detach(dev->dvb.frontend); + dev->dvb.frontend = NULL; + } + return -EINVAL; } /* ----------------------------------------------------------- */ -- cgit v1.2.3 From b4edcc9083af9444b288ee9e14cab28b29dc3636 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Wed, 30 Apr 2008 12:36:09 -0300 Subject: V4L/DVB (7808): cx23885: fix kbuild dependencies Thanks to Ingo Molnar for finding this. Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/cx23885/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/video/cx23885/Kconfig b/drivers/media/video/cx23885/Kconfig index cadf936c3673..c50d45192efd 100644 --- a/drivers/media/video/cx23885/Kconfig +++ b/drivers/media/video/cx23885/Kconfig @@ -9,6 +9,8 @@ config VIDEO_CX23885 select VIDEO_IR select VIDEOBUF_DVB select VIDEO_CX25840 + select VIDEO_CX2341X + select DVB_DIB7000P if !DVB_FE_CUSTOMISE select MEDIA_TUNER_MT2131 if !DVB_FE_CUSTOMISE select DVB_S5H1409 if !DVB_FE_CUSTOMISE select DVB_LGDT330X if !DVB_FE_CUSTOMISE -- cgit v1.2.3 From b7eccc404f399ab93ed128e51ca5d6e0e5115dd2 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 30 Apr 2008 09:21:33 -0300 Subject: V4L/DVB (7810): soc_camera: mt9v022 and mt9m001 depend on I2C Both mt9v022 and mt9m001 cameras are controlled over the I2C bus. Respectively, their drivers require I2C to be built successfully. Thanks to Ingo Molnar for reporting the build-breakage. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig index fe743aa7f645..98e2e1a2a71d 100644 --- a/drivers/media/video/Kconfig +++ b/drivers/media/video/Kconfig @@ -906,7 +906,7 @@ config SOC_CAMERA config SOC_CAMERA_MT9M001 tristate "mt9m001 support" - depends on SOC_CAMERA + depends on SOC_CAMERA && I2C select GPIO_PCA953X if MT9M001_PCA9536_SWITCH help This driver supports MT9M001 cameras from Micron, monochrome @@ -921,7 +921,7 @@ config MT9M001_PCA9536_SWITCH config SOC_CAMERA_MT9V022 tristate "mt9v022 support" - depends on SOC_CAMERA + depends on SOC_CAMERA && I2C select GPIO_PCA953X if MT9V022_PCA9536_SWITCH help This driver supports MT9V022 cameras from Micron -- cgit v1.2.3 From ef69c8e88bafdeb896395fa5379a4b8c6a10bb08 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 1 May 2008 02:17:24 -0300 Subject: V4L/DVB (7813): Fix compilation, when V4L1_COMPAT is disabled This driver uses some sysfs helper functions that are available only for legacy drivers. It also requires linux/mm.h. This patch fixes compiliation when not in compat mode. Thanks to Ingo Molnar for identifying this issue. Acked-by: Jaime Velasco Juan Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/stk-webcam.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/media/video/stk-webcam.c b/drivers/media/video/stk-webcam.c index 9276ed997388..b12c60cf5a09 100644 --- a/drivers/media/video/stk-webcam.c +++ b/drivers/media/video/stk-webcam.c @@ -30,6 +30,7 @@ #include #include +#include #include #include #include @@ -245,6 +246,8 @@ static int stk_initialise(struct stk_camera *dev) return -1; } +#ifdef CONFIG_VIDEO_V4L1_COMPAT + /* sysfs functions */ /*FIXME cleanup this */ @@ -350,6 +353,10 @@ static void stk_remove_sysfs_files(struct video_device *vdev) video_device_remove_file(vdev, &dev_attr_vflip); } +#else +#define stk_create_sysfs_files(a) +#define stk_remove_sysfs_files(a) +#endif /* *********************************************** */ /* -- cgit v1.2.3 From 74ee05109c9d6ae2dfe1b462592d3854ddbf1f6a Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Thu, 1 May 2008 18:02:30 -0300 Subject: V4L/DVB (7823): em28xx: add additional usb subids for Hauppauge HVR-950 Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/CARDLIST.em28xx | 2 +- drivers/media/video/em28xx/em28xx-cards.c | 8 +++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/video4linux/CARDLIST.em28xx b/Documentation/video4linux/CARDLIST.em28xx index f40e09296f30..1d6a245c828f 100644 --- a/Documentation/video4linux/CARDLIST.em28xx +++ b/Documentation/video4linux/CARDLIST.em28xx @@ -14,4 +14,4 @@ 13 -> Terratec Prodigy XS (em2880) [0ccd:0047] 14 -> Pixelview Prolink PlayTV USB 2.0 (em2820/em2840) 15 -> V-Gear PocketTV (em2800) - 16 -> Hauppauge WinTV HVR 950 (em2880) [2040:6513] + 16 -> Hauppauge WinTV HVR 950 (em2880) [2040:6513,2040:6517,2040:651b,2040:651f] diff --git a/drivers/media/video/em28xx/em28xx-cards.c b/drivers/media/video/em28xx/em28xx-cards.c index 50ccf3771204..3e4f3c7e92e7 100644 --- a/drivers/media/video/em28xx/em28xx-cards.c +++ b/drivers/media/video/em28xx/em28xx-cards.c @@ -420,7 +420,13 @@ struct usb_device_id em28xx_id_table [] = { .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900 }, { USB_DEVICE(0x2040, 0x6502), .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900 }, - { USB_DEVICE(0x2040, 0x6513), + { USB_DEVICE(0x2040, 0x6513), /* HCW HVR-980 */ + .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950 }, + { USB_DEVICE(0x2040, 0x6517), /* HP HVR-950 */ + .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950 }, + { USB_DEVICE(0x2040, 0x651b), /* RP HVR-950 */ + .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950 }, + { USB_DEVICE(0x2040, 0x651f), /* HCW HVR-850 */ .driver_info = EM2880_BOARD_HAUPPAUGE_WINTV_HVR_950 }, { USB_DEVICE(0x0ccd, 0x0042), .driver_info = EM2880_BOARD_TERRATEC_HYBRID_XS }, -- cgit v1.2.3 From 3c3852cda6e0c557f5e0915b5451510c1acd64a2 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Fri, 2 May 2008 16:12:44 -0300 Subject: V4L/DVB (7827): cx23885: add missing subsystem ID for Hauppauge HVR-1200 OEM Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/CARDLIST.cx23885 | 2 +- drivers/media/video/cx23885/cx23885-cards.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/video4linux/CARDLIST.cx23885 b/Documentation/video4linux/CARDLIST.cx23885 index 929b90c8387f..191194ea1e25 100644 --- a/Documentation/video4linux/CARDLIST.cx23885 +++ b/Documentation/video4linux/CARDLIST.cx23885 @@ -5,6 +5,6 @@ 4 -> DViCO FusionHDTV5 Express [18ac:d500] 5 -> Hauppauge WinTV-HVR1500Q [0070:7790,0070:7797] 6 -> Hauppauge WinTV-HVR1500 [0070:7710,0070:7717] - 7 -> Hauppauge WinTV-HVR1200 [0070:71d1] + 7 -> Hauppauge WinTV-HVR1200 [0070:71d1,0070:71d3] 8 -> Hauppauge WinTV-HVR1700 [0070:8101] 9 -> Hauppauge WinTV-HVR1400 [0070:8010] diff --git a/drivers/media/video/cx23885/cx23885-cards.c b/drivers/media/video/cx23885/cx23885-cards.c index 6ebf58724a01..8c3801193283 100644 --- a/drivers/media/video/cx23885/cx23885-cards.c +++ b/drivers/media/video/cx23885/cx23885-cards.c @@ -198,6 +198,10 @@ struct cx23885_subid cx23885_subids[] = { .subvendor = 0x0070, .subdevice = 0x71d1, .card = CX23885_BOARD_HAUPPAUGE_HVR1200, + }, { + .subvendor = 0x0070, + .subdevice = 0x71d3, + .card = CX23885_BOARD_HAUPPAUGE_HVR1200, }, { .subvendor = 0x0070, .subdevice = 0x8101, -- cgit v1.2.3 From 36396c893272a577eafad40630a609ccd36d20ea Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Fri, 2 May 2008 16:14:33 -0300 Subject: V4L/DVB (7828): cx23885: update model matrix for Hauppauge WinTV HVR-1200 & WinTV HVR-1700 Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/cx23885/cx23885-cards.c | 32 ++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/media/video/cx23885/cx23885-cards.c b/drivers/media/video/cx23885/cx23885-cards.c index 8c3801193283..20e05f230546 100644 --- a/drivers/media/video/cx23885/cx23885-cards.c +++ b/drivers/media/video/cx23885/cx23885-cards.c @@ -249,6 +249,33 @@ static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data) /* Make sure we support the board model */ switch (tv.model) { + case 71009: + /* WinTV-HVR1200 (PCIe, Retail, full height) + * DVB-T and basic analog */ + case 71359: + /* WinTV-HVR1200 (PCIe, OEM, half height) + * DVB-T and basic analog */ + case 71439: + /* WinTV-HVR1200 (PCIe, OEM, half height) + * DVB-T and basic analog */ + case 71449: + /* WinTV-HVR1200 (PCIe, OEM, full height) + * DVB-T and basic analog */ + case 71939: + /* WinTV-HVR1200 (PCIe, OEM, half height) + * DVB-T and basic analog */ + case 71949: + /* WinTV-HVR1200 (PCIe, OEM, full height) + * DVB-T and basic analog */ + case 71959: + /* WinTV-HVR1200 (PCIe, OEM, full height) + * DVB-T and basic analog */ + case 71979: + /* WinTV-HVR1200 (PCIe, OEM, half height) + * DVB-T and basic analog */ + case 71999: + /* WinTV-HVR1200 (PCIe, OEM, full height) + * DVB-T and basic analog */ case 76601: /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual channel ATSC and MPEG2 HW Encoder */ case 77001: /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC and Basic analog */ case 77011: /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC and Basic analog */ @@ -267,8 +294,11 @@ static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data) case 80019: /* WinTV-HVR1400 (Express Card, Retail, IR, * DVB-T and Basic analog */ + case 81509: + /* WinTV-HVR1700 (PCIe, OEM, No IR, half height) + * DVB-T and MPEG2 HW Encoder */ case 81519: - /* WinTV-HVR1700 (PCIe, Retail, No IR, half height, + /* WinTV-HVR1700 (PCIe, OEM, No IR, full height) * DVB-T and MPEG2 HW Encoder */ break; default: -- cgit v1.2.3 From fa146c6dceffa68fa12f8d0b797ab9753fa1c792 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Fri, 2 May 2008 16:20:10 -0300 Subject: V4L/DVB (7829): cx23885: remove remaining references to dvb-pll The cx23885 driver used to use dvb-pll for LG-TDVS-H064F support on the FusionHDTV5 Express. This has since been converted to use tuner-simple instead, once digital tuning support was added to tuner-simple. Since cx23885 no longer uses dvb-pll, remove the #include "dvb-pll.h", and the DVB_PLL Kconfig selection. Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/cx23885/Kconfig | 1 - drivers/media/video/cx23885/cx23885-dvb.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/media/video/cx23885/Kconfig b/drivers/media/video/cx23885/Kconfig index c50d45192efd..013e18cf1052 100644 --- a/drivers/media/video/cx23885/Kconfig +++ b/drivers/media/video/cx23885/Kconfig @@ -14,7 +14,6 @@ config VIDEO_CX23885 select MEDIA_TUNER_MT2131 if !DVB_FE_CUSTOMISE select DVB_S5H1409 if !DVB_FE_CUSTOMISE select DVB_LGDT330X if !DVB_FE_CUSTOMISE - select DVB_PLL if !DVB_FE_CUSTOMISE select MEDIA_TUNER_XC2028 if !DVB_FE_CUSTOMIZE select MEDIA_TUNER_TDA8290 if !DVB_FE_CUSTOMIZE select MEDIA_TUNER_TDA18271 if !DVB_FE_CUSTOMIZE diff --git a/drivers/media/video/cx23885/cx23885-dvb.c b/drivers/media/video/cx23885/cx23885-dvb.c index f05649727b60..47e3f9e035f9 100644 --- a/drivers/media/video/cx23885/cx23885-dvb.c +++ b/drivers/media/video/cx23885/cx23885-dvb.c @@ -37,7 +37,6 @@ #include "lgdt330x.h" #include "xc5000.h" #include "tda10048.h" -#include "dvb-pll.h" #include "tuner-xc2028.h" #include "tuner-simple.h" #include "dib7000p.h" -- cgit v1.2.3 From 71a35fe2a345eb3704e1f1b4da65451d3e2b8c2e Mon Sep 17 00:00:00 2001 From: Robert Schedel Date: Sat, 3 May 2008 12:58:36 -0300 Subject: V4L/DVB (7830): dvb_ca_en50221: Fix High CPU load in 'top' due to budget_av slot polling This change addresses kernel bug #10459: In kernel 2.6.25 the budget_av driver polls for an CI slot in 100ms intervals (because no interrupt solution for budget_av cards is feasible due to HW reasons). If no CI/CAM is connected to the DVB card, polling times out only after 250ms. This periodic polling leads to high CPU load. The change increases the polling interval for empty slots from 100ms to 5s. Intervals for remaining slot states (invalid, in progress, ready) are unchanged, as they are either temporary conditions or no timeout should occur. Signed-off-by: Robert Schedel Signed-off-by: Oliver Endriss Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb/dvb-core/dvb_ca_en50221.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/media/dvb/dvb-core/dvb_ca_en50221.c b/drivers/media/dvb/dvb-core/dvb_ca_en50221.c index 8cbdb0ec67e2..588fbe105c27 100644 --- a/drivers/media/dvb/dvb-core/dvb_ca_en50221.c +++ b/drivers/media/dvb/dvb-core/dvb_ca_en50221.c @@ -910,15 +910,21 @@ static void dvb_ca_en50221_thread_update_delay(struct dvb_ca_private *ca) int curdelay = 100000000; int slot; + /* Beware of too high polling frequency, because one polling + * call might take several hundred milliseconds until timeout! + */ for (slot = 0; slot < ca->slot_count; slot++) { switch (ca->slot_info[slot].slot_state) { default: case DVB_CA_SLOTSTATE_NONE: + delay = HZ * 60; /* 60s */ + if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) + delay = HZ * 5; /* 5s */ + break; case DVB_CA_SLOTSTATE_INVALID: - delay = HZ * 60; - if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) { - delay = HZ / 10; - } + delay = HZ * 60; /* 60s */ + if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) + delay = HZ / 10; /* 100ms */ break; case DVB_CA_SLOTSTATE_UNINITIALISED: @@ -926,19 +932,17 @@ static void dvb_ca_en50221_thread_update_delay(struct dvb_ca_private *ca) case DVB_CA_SLOTSTATE_VALIDATE: case DVB_CA_SLOTSTATE_WAITFR: case DVB_CA_SLOTSTATE_LINKINIT: - delay = HZ / 10; + delay = HZ / 10; /* 100ms */ break; case DVB_CA_SLOTSTATE_RUNNING: - delay = HZ * 60; - if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) { - delay = HZ / 10; - } + delay = HZ * 60; /* 60s */ + if (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE)) + delay = HZ / 10; /* 100ms */ if (ca->open) { if ((!ca->slot_info[slot].da_irq_supported) || - (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_DA))) { - delay = HZ / 10; - } + (!(ca->flags & DVB_CA_EN50221_FLAG_IRQ_DA))) + delay = HZ / 10; /* 100ms */ } break; } -- cgit v1.2.3 From f686d8c3b53c7b105330b5292ff5d44bb04e4971 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Mon, 5 May 2008 21:08:28 -0300 Subject: V4L/DVB (7832): xc5000: MEDIA_TUNER_XC5000 must select FW_LOADER Fix the following build error: drivers/built-in.o: In function `xc_load_fw_and_init_tuner': xc5000.c:(.text+0x2dacd): undefined reference to `request_firmware' xc5000.c:(.text+0x2daf0): undefined reference to `release_firmware' xc5000.c:(.text+0x2db85): undefined reference to `release_firmware' make[1]: *** [.tmp_vmlinux1] Error 1 Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/common/tuners/Kconfig b/drivers/media/common/tuners/Kconfig index 5be85ff53e12..c0b472eaeb7d 100644 --- a/drivers/media/common/tuners/Kconfig +++ b/drivers/media/common/tuners/Kconfig @@ -142,6 +142,7 @@ config MEDIA_TUNER_XC2028 config MEDIA_TUNER_XC5000 tristate "Xceive XC5000 silicon tuner" depends on I2C + select FW_LOADER default m if DVB_FE_CUSTOMISE help A driver for the silicon tuner XC5000 from Xceive. -- cgit v1.2.3 From 28dd15b4334c2ded53d7738160861aa16304b8fd Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Sat, 3 May 2008 21:23:51 -0300 Subject: V4L/DVB (7834): build fix for drivers/media/video/au0828 x86.git testing found the following build failure in v2.6.26-rc1: MODPOST 424 modules ERROR: "tveeprom_hauppauge_analog" [drivers/media/video/au0828/au0828.ko] undefined! ERROR: "tveeprom_read" [drivers/media/video/au0828/au0828.ko] undefined! with this config: http://redhat.com/~mingo/misc/config-Sat_May__3_22_28_58_CEST_2008.bad this patch does what other video drivers do to utilize the VIDEO_TVEEPROM functionality (and this resolves the build problem) - but i have not checked it on real hardware and i have not checked whether the fix is complete. selections, so some items might still be missing - just not triggered with this specific config. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/au0828/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/video/au0828/Kconfig b/drivers/media/video/au0828/Kconfig index cab277fafa63..4d99b1aae4f8 100644 --- a/drivers/media/video/au0828/Kconfig +++ b/drivers/media/video/au0828/Kconfig @@ -3,6 +3,7 @@ config VIDEO_AU0828 tristate "Auvitek AU0828 support" depends on VIDEO_DEV && I2C && INPUT && DVB_CORE select I2C_ALGOBIT + select VIDEO_TVEEPROM select DVB_AU8522 if !DVB_FE_CUSTOMIZE select MEDIA_TUNER_XC5000 if !DVB_FE_CUSTOMIZE ---help--- -- cgit v1.2.3 From 696b9562df15795facf9ffbd470983e776fa6c19 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Mon, 5 May 2008 19:20:42 -0300 Subject: V4L/DVB (7835): multimedia/video: fix au0828 Kconfig Fix undefined references in au0828: depends on USB and select VIDEO_TVEEPROM Signed-off-by: Randy Dunlap Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/au0828/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/video/au0828/Kconfig b/drivers/media/video/au0828/Kconfig index 4d99b1aae4f8..def10d086373 100644 --- a/drivers/media/video/au0828/Kconfig +++ b/drivers/media/video/au0828/Kconfig @@ -1,7 +1,7 @@ config VIDEO_AU0828 tristate "Auvitek AU0828 support" - depends on VIDEO_DEV && I2C && INPUT && DVB_CORE + depends on VIDEO_DEV && I2C && INPUT && DVB_CORE && USB select I2C_ALGOBIT select VIDEO_TVEEPROM select DVB_AU8522 if !DVB_FE_CUSTOMIZE -- cgit v1.2.3 From dc9d522a1358bfb87e9ed8718cc1e4d5141a5468 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Sun, 4 May 2008 20:32:45 -0300 Subject: V4L/DVB (7836): cinergyT2 build fix x86.git testing found the following build bug in v2.6.26-rc1: drivers/built-in.o: In function `cinergyt2_probe': cinergyT2.c:(.text+0xb6117): undefined reference to `input_allocate_device' cinergyT2.c:(.text+0xb6230): undefined reference to `input_register_device' cinergyT2.c:(.text+0xb623d): undefined reference to `input_free_device' with the following config: http://redhat.com/~mingo/misc/config-Sun_May__4_22_06_54_CEST_2008.bad The reason for the bug is that the cinergyT2 driver depends on CONFIG_INPUT functionality, but if INPUT is modular it's still possible to build CONFIG_DVB_CINERGYT2=y - which leads to missing symbols. The solution is to make DVB_CINERGYT2 dependent on INPUT. [ This solves the build problem - i have not tested the driver on this card. ] Signed-off-by: Ingo Molnar Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb/cinergyT2/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/dvb/cinergyT2/Kconfig b/drivers/media/dvb/cinergyT2/Kconfig index 3d778c5aba68..c03513b2ccae 100644 --- a/drivers/media/dvb/cinergyT2/Kconfig +++ b/drivers/media/dvb/cinergyT2/Kconfig @@ -1,6 +1,6 @@ config DVB_CINERGYT2 tristate "Terratec CinergyT2/qanu USB2 DVB-T receiver" - depends on DVB_CORE && USB + depends on DVB_CORE && USB && INPUT help Support for "TerraTec CinergyT2" USB2.0 Highspeed DVB Receivers -- cgit v1.2.3 From d35fccaffd095e79691cd07a49a36867cb275b72 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sat, 3 May 2008 18:20:21 -0300 Subject: V4L/DVB (7837): tda18271: fix error handling in init and sleep paths Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/tda18271-common.c | 7 ++--- drivers/media/common/tuners/tda18271-fe.c | 38 ++++++++++++++++++--------- 2 files changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/media/common/tuners/tda18271-common.c b/drivers/media/common/tuners/tda18271-common.c index e27a7620a32f..9001d422cc1c 100644 --- a/drivers/media/common/tuners/tda18271-common.c +++ b/drivers/media/common/tuners/tda18271-common.c @@ -227,9 +227,8 @@ int tda18271_charge_pump_source(struct dvb_frontend *fe, regs[r_cp] &= ~0x20; regs[r_cp] |= ((force & 1) << 5); - tda18271_write_regs(fe, r_cp, 1); - return 0; + return tda18271_write_regs(fe, r_cp, 1); } int tda18271_init_regs(struct dvb_frontend *fe) @@ -494,9 +493,7 @@ int tda18271_set_standby_mode(struct dvb_frontend *fe, sm_lt ? (1 << 6) : 0 | sm_xt ? (1 << 5) : 0; - tda18271_write_regs(fe, R_EP3, 1); - - return 0; + return tda18271_write_regs(fe, R_EP3, 1); } /*---------------------------------------------------------------------*/ diff --git a/drivers/media/common/tuners/tda18271-fe.c b/drivers/media/common/tuners/tda18271-fe.c index b262100ae897..46c080089eb0 100644 --- a/drivers/media/common/tuners/tda18271-fe.c +++ b/drivers/media/common/tuners/tda18271-fe.c @@ -719,45 +719,56 @@ static int tda18271_ir_cal_init(struct dvb_frontend *fe) { struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; + int ret; - tda18271_read_regs(fe); + ret = tda18271_read_regs(fe); + if (ret < 0) + goto fail; /* test IR_CAL_OK to see if we need init */ if ((regs[R_EP1] & 0x08) == 0) - tda18271_init_regs(fe); - - return 0; + ret = tda18271_init_regs(fe); +fail: + return ret; } static int tda18271_init(struct dvb_frontend *fe) { struct tda18271_priv *priv = fe->tuner_priv; + int ret; mutex_lock(&priv->lock); /* power up */ - tda18271_set_standby_mode(fe, 0, 0, 0); + ret = tda18271_set_standby_mode(fe, 0, 0, 0); + if (ret < 0) + goto fail; /* initialization */ - tda18271_ir_cal_init(fe); + ret = tda18271_ir_cal_init(fe); + if (ret < 0) + goto fail; if (priv->id == TDA18271HDC2) tda18271c2_rf_cal_init(fe); - +fail: mutex_unlock(&priv->lock); - return 0; + return ret; } static int tda18271_tune(struct dvb_frontend *fe, struct tda18271_std_map_item *map, u32 freq, u32 bw) { struct tda18271_priv *priv = fe->tuner_priv; + int ret; tda_dbg("freq = %d, ifc = %d, bw = %d, agc_mode = %d, std = %d\n", freq, map->if_freq, bw, map->agc_mode, map->std); - tda18271_init(fe); + ret = tda18271_init(fe); + if (ret < 0) + goto fail; mutex_lock(&priv->lock); @@ -772,8 +783,8 @@ static int tda18271_tune(struct dvb_frontend *fe, tda18271_channel_configuration(fe, map, freq, bw); mutex_unlock(&priv->lock); - - return 0; +fail: + return ret; } /* ------------------------------------------------------------------ */ @@ -905,16 +916,17 @@ fail: static int tda18271_sleep(struct dvb_frontend *fe) { struct tda18271_priv *priv = fe->tuner_priv; + int ret; mutex_lock(&priv->lock); /* standby mode w/ slave tuner output * & loop thru & xtal oscillator on */ - tda18271_set_standby_mode(fe, 1, 0, 0); + ret = tda18271_set_standby_mode(fe, 1, 0, 0); mutex_unlock(&priv->lock); - return 0; + return ret; } static int tda18271_release(struct dvb_frontend *fe) -- cgit v1.2.3 From 24124f784bfec447f5cb9e64ed337afb57f0fca5 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sat, 3 May 2008 19:28:00 -0300 Subject: V4L/DVB (7838): tda18271: fix error handling in tda18271c2_rf_cal_init path fix error handling in tda18271c2_rf_cal_init immediate path Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/tda18271-fe.c | 68 +++++++++++++++++++++---------- 1 file changed, 47 insertions(+), 21 deletions(-) diff --git a/drivers/media/common/tuners/tda18271-fe.c b/drivers/media/common/tuners/tda18271-fe.c index 46c080089eb0..d4fdcd4a0e06 100644 --- a/drivers/media/common/tuners/tda18271-fe.c +++ b/drivers/media/common/tuners/tda18271-fe.c @@ -259,26 +259,33 @@ static int tda18271_por(struct dvb_frontend *fe) { struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; + int ret; /* power up detector 1 */ regs[R_EB12] &= ~0x20; - tda18271_write_regs(fe, R_EB12, 1); + ret = tda18271_write_regs(fe, R_EB12, 1); + if (ret < 0) + goto fail; regs[R_EB18] &= ~0x80; /* turn agc1 loop on */ regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */ - tda18271_write_regs(fe, R_EB18, 1); + ret = tda18271_write_regs(fe, R_EB18, 1); + if (ret < 0) + goto fail; regs[R_EB21] |= 0x03; /* set agc2_gain to -6 dB */ /* POR mode */ - tda18271_set_standby_mode(fe, 1, 0, 0); + ret = tda18271_set_standby_mode(fe, 1, 0, 0); + if (ret < 0) + goto fail; /* disable 1.5 MHz low pass filter */ regs[R_EB23] &= ~0x04; /* forcelp_fc2_en = 0 */ regs[R_EB23] &= ~0x02; /* XXX: lp_fc[2] = 0 */ - tda18271_write_regs(fe, R_EB21, 3); - - return 0; + ret = tda18271_write_regs(fe, R_EB21, 3); +fail: + return ret; } static int tda18271_calibrate_rf(struct dvb_frontend *fe, u32 freq) @@ -389,7 +396,7 @@ static int tda18271_powerscan(struct dvb_frontend *fe, { struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; - int sgn, bcal, count, wait; + int sgn, bcal, count, wait, ret; u8 cid_target; u16 count_limit; u32 freq; @@ -421,7 +428,9 @@ static int tda18271_powerscan(struct dvb_frontend *fe, tda18271_write_regs(fe, R_EP2, 1); /* read power detection info, stored in EB10 */ - tda18271_read_extended(fe); + ret = tda18271_read_extended(fe); + if (ret < 0) + return ret; /* algorithm initialization */ sgn = 1; @@ -447,7 +456,9 @@ static int tda18271_powerscan(struct dvb_frontend *fe, tda18271_write_regs(fe, R_EP2, 1); /* read power detection info, stored in EB10 */ - tda18271_read_extended(fe); + ret = tda18271_read_extended(fe); + if (ret < 0) + return ret; count += 200; @@ -478,6 +489,7 @@ static int tda18271_powerscan_init(struct dvb_frontend *fe) { struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; + int ret; /* set standard to digital */ regs[R_EP3] &= ~0x1f; /* clear std bits */ @@ -489,10 +501,14 @@ static int tda18271_powerscan_init(struct dvb_frontend *fe) /* update IF output level & IF notch frequency */ regs[R_EP4] &= ~0x1c; /* clear if level bits */ - tda18271_write_regs(fe, R_EP3, 2); + ret = tda18271_write_regs(fe, R_EP3, 2); + if (ret < 0) + goto fail; regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */ - tda18271_write_regs(fe, R_EB18, 1); + ret = tda18271_write_regs(fe, R_EB18, 1); + if (ret < 0) + goto fail; regs[R_EB21] &= ~0x03; /* set agc2_gain to -15 dB */ @@ -500,9 +516,9 @@ static int tda18271_powerscan_init(struct dvb_frontend *fe) regs[R_EB23] |= 0x04; /* forcelp_fc2_en = 1 */ regs[R_EB23] |= 0x02; /* lp_fc[2] = 1 */ - tda18271_write_regs(fe, R_EB21, 3); - - return 0; + ret = tda18271_write_regs(fe, R_EB21, 3); +fail: + return ret; } static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq) @@ -535,6 +551,8 @@ static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq) /* look for optimized calibration frequency */ bcal = tda18271_powerscan(fe, &rf_default[rf], &rf_freq[rf]); + if (bcal < 0) + return bcal; tda18271_calc_rf_cal(fe, &rf_freq[rf]); prog_tab[rf] = regs[R_EB14]; @@ -575,13 +593,16 @@ static int tda18271_calc_rf_filter_curve(struct dvb_frontend *fe) { struct tda18271_priv *priv = fe->tuner_priv; unsigned int i; + int ret; tda_info("tda18271: performing RF tracking filter calibration\n"); /* wait for die temperature stabilization */ msleep(200); - tda18271_powerscan_init(fe); + ret = tda18271_powerscan_init(fe); + if (ret < 0) + goto fail; /* rf band calibration */ for (i = 0; priv->rf_cal_state[i].rfmax != 0; i++) @@ -589,8 +610,8 @@ static int tda18271_calc_rf_filter_curve(struct dvb_frontend *fe) priv->rf_cal_state[i].rfmax); priv->tm_rfcal = tda18271_read_thermometer(fe); - - return 0; +fail: + return ret; } /* ------------------------------------------------------------------ */ @@ -599,6 +620,7 @@ static int tda18271c2_rf_cal_init(struct dvb_frontend *fe) { struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; + int ret; /* test RF_CAL_OK to see if we need init */ if ((regs[R_EP1] & 0x10) == 0) @@ -607,15 +629,19 @@ static int tda18271c2_rf_cal_init(struct dvb_frontend *fe) if (priv->cal_initialized) return 0; - tda18271_calc_rf_filter_curve(fe); + ret = tda18271_calc_rf_filter_curve(fe); + if (ret < 0) + goto fail; - tda18271_por(fe); + ret = tda18271_por(fe); + if (ret < 0) + goto fail; tda_info("tda18271: RF tracking filter calibration complete\n"); priv->cal_initialized = true; - - return 0; +fail: + return ret; } static int tda18271c1_rf_tracking_filter_calibration(struct dvb_frontend *fe, -- cgit v1.2.3 From c151c32fd7d8f5ca7dcd35430f2e625181c48d66 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sun, 4 May 2008 17:54:23 -0300 Subject: V4L/DVB (7839): tda18271: abort rf band calibration loop on errors Abort rf band calibration loop for the TDA18271HD/C2 if an error is detected. Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/tda18271-fe.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/media/common/tuners/tda18271-fe.c b/drivers/media/common/tuners/tda18271-fe.c index d4fdcd4a0e06..3f7ca45bba9b 100644 --- a/drivers/media/common/tuners/tda18271-fe.c +++ b/drivers/media/common/tuners/tda18271-fe.c @@ -605,9 +605,13 @@ static int tda18271_calc_rf_filter_curve(struct dvb_frontend *fe) goto fail; /* rf band calibration */ - for (i = 0; priv->rf_cal_state[i].rfmax != 0; i++) + for (i = 0; priv->rf_cal_state[i].rfmax != 0; i++) { + ret = tda18271_rf_tracking_filters_init(fe, 1000 * priv->rf_cal_state[i].rfmax); + if (ret < 0) + goto fail; + } priv->tm_rfcal = tda18271_read_thermometer(fe); fail: @@ -640,7 +644,10 @@ static int tda18271c2_rf_cal_init(struct dvb_frontend *fe) tda_info("tda18271: RF tracking filter calibration complete\n"); priv->cal_initialized = true; + goto end; fail: + tda_info("tda18271: RF tracking filter calibration failed!\n"); +end: return ret; } -- cgit v1.2.3 From 9c41d456e2936ea3aafa07d431c5963799f9659e Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sun, 4 May 2008 18:18:48 -0300 Subject: V4L/DVB (7840): tda18271: make tda18271_set_standby_mode less verbose for basic debug Only show debug from tda18271_set_standby_mode if DBG_ADV is set. Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/tda18271-common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/common/tuners/tda18271-common.c b/drivers/media/common/tuners/tda18271-common.c index 9001d422cc1c..d6938fc2c4c6 100644 --- a/drivers/media/common/tuners/tda18271-common.c +++ b/drivers/media/common/tuners/tda18271-common.c @@ -486,7 +486,8 @@ int tda18271_set_standby_mode(struct dvb_frontend *fe, struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; - tda_dbg("sm = %d, sm_lt = %d, sm_xt = %d\n", sm, sm_lt, sm_xt); + if (tda18271_debug & DBG_ADV) + tda_dbg("sm = %d, sm_lt = %d, sm_xt = %d\n", sm, sm_lt, sm_xt); regs[R_EP3] &= ~0xe0; /* clear sm, sm_lt, sm_xt */ regs[R_EP3] |= sm ? (1 << 7) : 0 | -- cgit v1.2.3 From 31940e3966b6cf3bb3e535ffa1cb97b16edd555b Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sun, 4 May 2008 19:37:27 -0300 Subject: V4L/DVB (7841): tda18271: fix error handling in tda18271_channel_configuration Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/tda18271-fe.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/media/common/tuners/tda18271-fe.c b/drivers/media/common/tuners/tda18271-fe.c index 3f7ca45bba9b..2c1bb380112d 100644 --- a/drivers/media/common/tuners/tda18271-fe.c +++ b/drivers/media/common/tuners/tda18271-fe.c @@ -51,6 +51,7 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, { struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; + int ret; u32 N; /* update TV broadcast parameters */ @@ -85,7 +86,9 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, /* update rf top / if top */ regs[R_EB22] = 0x00; regs[R_EB22] |= map->rfagc_top; - tda18271_write_regs(fe, R_EB22, 1); + ret = tda18271_write_regs(fe, R_EB22, 1); + if (ret < 0) + goto fail; /* --------------------------------------------------------------- */ @@ -121,7 +124,9 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, /* agc1 has priority on agc2 */ regs[R_EB1] &= ~0x01; - tda18271_write_regs(fe, R_EB1, 1); + ret = tda18271_write_regs(fe, R_EB1, 1); + if (ret < 0) + goto fail; /* --------------------------------------------------------------- */ @@ -141,7 +146,9 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, break; } - tda18271_write_regs(fe, R_TM, 7); + ret = tda18271_write_regs(fe, R_TM, 7); + if (ret < 0) + goto fail; /* force charge pump source */ charge_pump_source(fe, 1); @@ -158,9 +165,9 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, regs[R_EP3] &= ~0x04; else regs[R_EP3] |= 0x04; - tda18271_write_regs(fe, R_EP3, 1); - - return 0; + ret = tda18271_write_regs(fe, R_EP3, 1); +fail: + return ret; } static int tda18271_read_thermometer(struct dvb_frontend *fe) @@ -813,7 +820,7 @@ static int tda18271_tune(struct dvb_frontend *fe, tda18271c2_rf_tracking_filters_correction(fe, freq); break; } - tda18271_channel_configuration(fe, map, freq, bw); + ret = tda18271_channel_configuration(fe, map, freq, bw); mutex_unlock(&priv->lock); fail: -- cgit v1.2.3 From 20f4206379260e3ca02c8ee57bc3da9b0c7d09da Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sun, 4 May 2008 19:57:06 -0300 Subject: V4L/DVB (7842): tda18271: fix error handling in tda18271c2_rf_tracking_filters_correction Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/tda18271-fe.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/media/common/tuners/tda18271-fe.c b/drivers/media/common/tuners/tda18271-fe.c index 2c1bb380112d..8b44d4c62bfe 100644 --- a/drivers/media/common/tuners/tda18271-fe.c +++ b/drivers/media/common/tuners/tda18271-fe.c @@ -220,11 +220,13 @@ static int tda18271c2_rf_tracking_filters_correction(struct dvb_frontend *fe, struct tda18271_priv *priv = fe->tuner_priv; struct tda18271_rf_tracking_filter_cal *map = priv->rf_cal_state; unsigned char *regs = priv->tda18271_regs; - int tm_current, rfcal_comp, approx, i; + int tm_current, rfcal_comp, approx, i, ret; u8 dc_over_dt, rf_tab; /* power up */ - tda18271_set_standby_mode(fe, 0, 0, 0); + ret = tda18271_set_standby_mode(fe, 0, 0, 0); + if (ret < 0) + goto fail; /* read die current temperature */ tm_current = tda18271_read_thermometer(fe); @@ -257,9 +259,9 @@ static int tda18271c2_rf_tracking_filters_correction(struct dvb_frontend *fe, rfcal_comp = dc_over_dt * (tm_current - priv->tm_rfcal); regs[R_EB14] = approx + rfcal_comp; - tda18271_write_regs(fe, R_EB14, 1); - - return 0; + ret = tda18271_write_regs(fe, R_EB14, 1); +fail: + return ret; } static int tda18271_por(struct dvb_frontend *fe) -- cgit v1.2.3 From 10ed0bf4af00c25590e8bfca344d8dec5c3637ae Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sun, 4 May 2008 20:26:47 -0300 Subject: V4L/DVB (7843): tda18271: fix error handling in tda18271c1_rf_tracking_filter_calibration Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/tda18271-fe.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/media/common/tuners/tda18271-fe.c b/drivers/media/common/tuners/tda18271-fe.c index 8b44d4c62bfe..13d651c987a3 100644 --- a/drivers/media/common/tuners/tda18271-fe.c +++ b/drivers/media/common/tuners/tda18271-fe.c @@ -665,6 +665,7 @@ static int tda18271c1_rf_tracking_filter_calibration(struct dvb_frontend *fe, { struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; + int ret; u32 N = 0; /* calculate bp filter */ @@ -713,7 +714,10 @@ static int tda18271c1_rf_tracking_filter_calibration(struct dvb_frontend *fe, tda18271_calc_main_pll(fe, N); - tda18271_write_regs(fe, R_EP3, 11); + ret = tda18271_write_regs(fe, R_EP3, 11); + if (ret < 0) + return ret; + msleep(5); /* RF tracking filter calibration initialization */ /* search for K,M,CO for RF calibration */ -- cgit v1.2.3 From 4bd5d1071ddbb35ae545c7738e6411e50ce28b17 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sun, 4 May 2008 21:32:21 -0300 Subject: V4L/DVB (7844): tda18271: add tda_fail macro to log error cases Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/tda18271-common.c | 14 +++---- drivers/media/common/tuners/tda18271-fe.c | 56 +++++++++++++-------------- drivers/media/common/tuners/tda18271-priv.h | 9 +++++ 3 files changed, 44 insertions(+), 35 deletions(-) diff --git a/drivers/media/common/tuners/tda18271-common.c b/drivers/media/common/tuners/tda18271-common.c index d6938fc2c4c6..42b5f5d4bfe6 100644 --- a/drivers/media/common/tuners/tda18271-common.c +++ b/drivers/media/common/tuners/tda18271-common.c @@ -508,7 +508,7 @@ int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq) u32 div; int ret = tda18271_lookup_pll_map(fe, MAIN_PLL, &freq, &pd, &d); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_MPD] = (0x77 & pd); @@ -540,7 +540,7 @@ int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq) u32 div; int ret = tda18271_lookup_pll_map(fe, CAL_PLL, &freq, &pd, &d); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_CPD] = pd; @@ -564,7 +564,7 @@ int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq) u8 val; int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EP1] &= ~0x07; /* clear bp filter bits */ @@ -581,7 +581,7 @@ int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq) u8 val; int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EB13] &= ~0x7c; /* clear k & m bits */ @@ -598,7 +598,7 @@ int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq) u8 val; int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EP2] &= ~0xe0; /* clear rf band bits */ @@ -615,7 +615,7 @@ int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq) u8 val; int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EP2] &= ~0x1f; /* clear gain taper bits */ @@ -632,7 +632,7 @@ int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq) u8 val; int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EP5] &= ~0x07; diff --git a/drivers/media/common/tuners/tda18271-fe.c b/drivers/media/common/tuners/tda18271-fe.c index 13d651c987a3..89c01fb1f859 100644 --- a/drivers/media/common/tuners/tda18271-fe.c +++ b/drivers/media/common/tuners/tda18271-fe.c @@ -87,7 +87,7 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, regs[R_EB22] = 0x00; regs[R_EB22] |= map->rfagc_top; ret = tda18271_write_regs(fe, R_EB22, 1); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* --------------------------------------------------------------- */ @@ -125,7 +125,7 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, regs[R_EB1] &= ~0x01; ret = tda18271_write_regs(fe, R_EB1, 1); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* --------------------------------------------------------------- */ @@ -147,7 +147,7 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, } ret = tda18271_write_regs(fe, R_TM, 7); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* force charge pump source */ @@ -225,7 +225,7 @@ static int tda18271c2_rf_tracking_filters_correction(struct dvb_frontend *fe, /* power up */ ret = tda18271_set_standby_mode(fe, 0, 0, 0); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* read die current temperature */ @@ -237,8 +237,8 @@ static int tda18271c2_rf_tracking_filters_correction(struct dvb_frontend *fe, rf_tab = regs[R_EB14]; i = tda18271_lookup_rf_band(fe, &freq, NULL); - if (i < 0) - return -EINVAL; + if (tda_fail(i)) + return i; if ((0 == map[i].rf3) || (freq / 1000 < map[i].rf2)) { approx = map[i].rf_a1 * @@ -273,20 +273,20 @@ static int tda18271_por(struct dvb_frontend *fe) /* power up detector 1 */ regs[R_EB12] &= ~0x20; ret = tda18271_write_regs(fe, R_EB12, 1); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EB18] &= ~0x80; /* turn agc1 loop on */ regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */ ret = tda18271_write_regs(fe, R_EB18, 1); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EB21] |= 0x03; /* set agc2_gain to -6 dB */ /* POR mode */ ret = tda18271_set_standby_mode(fe, 1, 0, 0); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* disable 1.5 MHz low pass filter */ @@ -438,7 +438,7 @@ static int tda18271_powerscan(struct dvb_frontend *fe, /* read power detection info, stored in EB10 */ ret = tda18271_read_extended(fe); - if (ret < 0) + if (tda_fail(ret)) return ret; /* algorithm initialization */ @@ -466,7 +466,7 @@ static int tda18271_powerscan(struct dvb_frontend *fe, /* read power detection info, stored in EB10 */ ret = tda18271_read_extended(fe); - if (ret < 0) + if (tda_fail(ret)) return ret; count += 200; @@ -511,12 +511,12 @@ static int tda18271_powerscan_init(struct dvb_frontend *fe) regs[R_EP4] &= ~0x1c; /* clear if level bits */ ret = tda18271_write_regs(fe, R_EP3, 2); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */ ret = tda18271_write_regs(fe, R_EB18, 1); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EB21] &= ~0x03; /* set agc2_gain to -15 dB */ @@ -546,7 +546,7 @@ static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq) i = tda18271_lookup_rf_band(fe, &freq, NULL); - if (i < 0) + if (tda_fail(i)) return i; rf_default[RF1] = 1000 * map[i].rf1_def; @@ -560,7 +560,7 @@ static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq) /* look for optimized calibration frequency */ bcal = tda18271_powerscan(fe, &rf_default[rf], &rf_freq[rf]); - if (bcal < 0) + if (tda_fail(bcal)) return bcal; tda18271_calc_rf_cal(fe, &rf_freq[rf]); @@ -610,7 +610,7 @@ static int tda18271_calc_rf_filter_curve(struct dvb_frontend *fe) msleep(200); ret = tda18271_powerscan_init(fe); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* rf band calibration */ @@ -618,7 +618,7 @@ static int tda18271_calc_rf_filter_curve(struct dvb_frontend *fe) ret = tda18271_rf_tracking_filters_init(fe, 1000 * priv->rf_cal_state[i].rfmax); - if (ret < 0) + if (tda_fail(ret)) goto fail; } @@ -643,11 +643,11 @@ static int tda18271c2_rf_cal_init(struct dvb_frontend *fe) return 0; ret = tda18271_calc_rf_filter_curve(fe); - if (ret < 0) + if (tda_fail(ret)) goto fail; ret = tda18271_por(fe); - if (ret < 0) + if (tda_fail(ret)) goto fail; tda_info("tda18271: RF tracking filter calibration complete\n"); @@ -715,7 +715,7 @@ static int tda18271c1_rf_tracking_filter_calibration(struct dvb_frontend *fe, tda18271_calc_main_pll(fe, N); ret = tda18271_write_regs(fe, R_EP3, 11); - if (ret < 0) + if (tda_fail(ret)) return ret; msleep(5); /* RF tracking filter calibration initialization */ @@ -768,7 +768,7 @@ static int tda18271_ir_cal_init(struct dvb_frontend *fe) int ret; ret = tda18271_read_regs(fe); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* test IR_CAL_OK to see if we need init */ @@ -787,12 +787,12 @@ static int tda18271_init(struct dvb_frontend *fe) /* power up */ ret = tda18271_set_standby_mode(fe, 0, 0, 0); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* initialization */ ret = tda18271_ir_cal_init(fe); - if (ret < 0) + if (tda_fail(ret)) goto fail; if (priv->id == TDA18271HDC2) @@ -813,7 +813,7 @@ static int tda18271_tune(struct dvb_frontend *fe, freq, map->if_freq, bw, map->agc_mode, map->std); ret = tda18271_init(fe); - if (ret < 0) + if (tda_fail(ret)) goto fail; mutex_lock(&priv->lock); @@ -894,7 +894,7 @@ static int tda18271_set_params(struct dvb_frontend *fe, ret = tda18271_tune(fe, map, freq, bw); - if (ret < 0) + if (tda_fail(ret)) goto fail; priv->frequency = freq; @@ -950,7 +950,7 @@ static int tda18271_set_analog_params(struct dvb_frontend *fe, ret = tda18271_tune(fe, map, freq, 0); - if (ret < 0) + if (tda_fail(ret)) goto fail; priv->frequency = freq; @@ -1153,10 +1153,10 @@ struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr, if (cfg) priv->small_i2c = cfg->small_i2c; - if (tda18271_get_id(fe) < 0) + if (tda_fail(tda18271_get_id(fe))) goto fail; - if (tda18271_assign_map_layout(fe) < 0) + if (tda_fail(tda18271_assign_map_layout(fe))) goto fail; mutex_lock(&priv->lock); diff --git a/drivers/media/common/tuners/tda18271-priv.h b/drivers/media/common/tuners/tda18271-priv.h index 2bc5eb368ea2..81a739365f8c 100644 --- a/drivers/media/common/tuners/tda18271-priv.h +++ b/drivers/media/common/tuners/tda18271-priv.h @@ -153,6 +153,15 @@ extern int tda18271_debug; #define tda_reg(fmt, arg...) dprintk(KERN_DEBUG, DBG_REG, fmt, ##arg) #define tda_cal(fmt, arg...) dprintk(KERN_DEBUG, DBG_CAL, fmt, ##arg) +#define tda_fail(ret) \ +({ \ + int __ret; \ + __ret = (ret < 0); \ + if (__ret) \ + tda_printk(KERN_ERR, "error %d on line %d\n", ret, __LINE__);\ + __ret; \ +}) + /*---------------------------------------------------------------------*/ enum tda18271_map_type { -- cgit v1.2.3 From fdbbfb092cee0d826cba96df51f56c0e22cae579 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 6 May 2008 12:35:58 -0300 Subject: V4L/DVB (7846): Re-creates VIDEO_TUNER VIDEO_TUNER is responsible for compilation of tuners.ko module. This were the previous behaviour before the creation of MEDIA_TUNER. Before this patch, tuner.ko were created even for drivers that don't need a tuner (like webcam drivers). Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/Kconfig | 6 +++++- drivers/media/video/Makefile | 2 +- drivers/media/video/bt8xx/Kconfig | 2 +- drivers/media/video/cx18/Kconfig | 2 +- drivers/media/video/cx23885/Kconfig | 2 +- drivers/media/video/cx88/Kconfig | 2 +- drivers/media/video/em28xx/Kconfig | 2 +- drivers/media/video/ivtv/Kconfig | 2 +- drivers/media/video/pvrusb2/Kconfig | 2 +- drivers/media/video/saa7134/Kconfig | 2 +- drivers/media/video/usbvision/Kconfig | 2 +- 11 files changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig index 98e2e1a2a71d..89d8d37838a3 100644 --- a/drivers/media/video/Kconfig +++ b/drivers/media/video/Kconfig @@ -44,6 +44,10 @@ config VIDEO_TVEEPROM tristate depends on I2C +config VIDEO_TUNER + tristate + depends on MEDIA_TUNER + # # Multimedia Video device configuration # @@ -690,7 +694,7 @@ config VIDEO_MXB tristate "Siemens-Nixdorf 'Multimedia eXtension Board'" depends on PCI && VIDEO_V4L1 && I2C select VIDEO_SAA7146_VV - select MEDIA_TUNER + select VIDEO_TUNER select VIDEO_SAA7111 if VIDEO_HELPER_CHIPS_AUTO select VIDEO_TDA9840 if VIDEO_HELPER_CHIPS_AUTO select VIDEO_TEA6415C if VIDEO_HELPER_CHIPS_AUTO diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile index a352c6e31f0c..dff0d6abe917 100644 --- a/drivers/media/video/Makefile +++ b/drivers/media/video/Makefile @@ -84,7 +84,7 @@ obj-$(CONFIG_VIDEO_HEXIUM_GEMINI) += hexium_gemini.o obj-$(CONFIG_VIDEO_DPC) += dpc7146.o obj-$(CONFIG_TUNER_3036) += tuner-3036.o -obj-$(CONFIG_MEDIA_TUNER) += tuner.o +obj-$(CONFIG_VIDEO_TUNER) += tuner.o obj-$(CONFIG_VIDEOBUF_GEN) += videobuf-core.o obj-$(CONFIG_VIDEOBUF_DMA_SG) += videobuf-dma-sg.o diff --git a/drivers/media/video/bt8xx/Kconfig b/drivers/media/video/bt8xx/Kconfig index 7431ef6de9f1..cfc822bb502a 100644 --- a/drivers/media/video/bt8xx/Kconfig +++ b/drivers/media/video/bt8xx/Kconfig @@ -6,7 +6,7 @@ config VIDEO_BT848 select VIDEO_BTCX select VIDEOBUF_DMA_SG select VIDEO_IR - select MEDIA_TUNER + select VIDEO_TUNER select VIDEO_TVEEPROM select VIDEO_MSP3400 if VIDEO_HELPER_CHIPS_AUTO select VIDEO_TVAUDIO if VIDEO_HELPER_CHIPS_AUTO diff --git a/drivers/media/video/cx18/Kconfig b/drivers/media/video/cx18/Kconfig index acc4b47f1d1d..be654a27bd3c 100644 --- a/drivers/media/video/cx18/Kconfig +++ b/drivers/media/video/cx18/Kconfig @@ -4,7 +4,7 @@ config VIDEO_CX18 select I2C_ALGOBIT select FW_LOADER select VIDEO_IR - select MEDIA_TUNER + select VIDEO_TUNER select VIDEO_TVEEPROM select VIDEO_CX2341X select VIDEO_CS5345 diff --git a/drivers/media/video/cx23885/Kconfig b/drivers/media/video/cx23885/Kconfig index 013e18cf1052..491a0052993f 100644 --- a/drivers/media/video/cx23885/Kconfig +++ b/drivers/media/video/cx23885/Kconfig @@ -4,7 +4,7 @@ config VIDEO_CX23885 select I2C_ALGOBIT select FW_LOADER select VIDEO_BTCX - select MEDIA_TUNER + select VIDEO_TUNER select VIDEO_TVEEPROM select VIDEO_IR select VIDEOBUF_DVB diff --git a/drivers/media/video/cx88/Kconfig b/drivers/media/video/cx88/Kconfig index b0d7d6a7a4cc..f1e799141256 100644 --- a/drivers/media/video/cx88/Kconfig +++ b/drivers/media/video/cx88/Kconfig @@ -5,7 +5,7 @@ config VIDEO_CX88 select FW_LOADER select VIDEO_BTCX select VIDEOBUF_DMA_SG - select MEDIA_TUNER + select VIDEO_TUNER select VIDEO_TVEEPROM select VIDEO_IR select VIDEO_WM8775 if VIDEO_HELPER_CHIPS_AUTO diff --git a/drivers/media/video/em28xx/Kconfig b/drivers/media/video/em28xx/Kconfig index c7c2896bbd8b..9caffed2b6b8 100644 --- a/drivers/media/video/em28xx/Kconfig +++ b/drivers/media/video/em28xx/Kconfig @@ -1,7 +1,7 @@ config VIDEO_EM28XX tristate "Empia EM28xx USB video capture support" depends on VIDEO_DEV && I2C && INPUT - select MEDIA_TUNER + select VIDEO_TUNER select VIDEO_TVEEPROM select VIDEO_IR select VIDEOBUF_VMALLOC diff --git a/drivers/media/video/ivtv/Kconfig b/drivers/media/video/ivtv/Kconfig index eec115bf9517..b6171702c4d0 100644 --- a/drivers/media/video/ivtv/Kconfig +++ b/drivers/media/video/ivtv/Kconfig @@ -4,7 +4,7 @@ config VIDEO_IVTV select I2C_ALGOBIT select FW_LOADER select VIDEO_IR - select MEDIA_TUNER + select VIDEO_TUNER select VIDEO_TVEEPROM select VIDEO_CX2341X select VIDEO_CX25840 diff --git a/drivers/media/video/pvrusb2/Kconfig b/drivers/media/video/pvrusb2/Kconfig index 9620c67fae77..31634f6ce627 100644 --- a/drivers/media/video/pvrusb2/Kconfig +++ b/drivers/media/video/pvrusb2/Kconfig @@ -2,7 +2,7 @@ config VIDEO_PVRUSB2 tristate "Hauppauge WinTV-PVR USB2 support" depends on VIDEO_V4L2 && I2C select FW_LOADER - select MEDIA_TUNER + select VIDEO_TUNER select VIDEO_TVEEPROM select VIDEO_CX2341X select VIDEO_SAA711X diff --git a/drivers/media/video/saa7134/Kconfig b/drivers/media/video/saa7134/Kconfig index 40e4c3bd2cb9..dbdfbaaaed24 100644 --- a/drivers/media/video/saa7134/Kconfig +++ b/drivers/media/video/saa7134/Kconfig @@ -3,7 +3,7 @@ config VIDEO_SAA7134 depends on VIDEO_DEV && PCI && I2C && INPUT select VIDEOBUF_DMA_SG select VIDEO_IR - select MEDIA_TUNER + select VIDEO_TUNER select VIDEO_TVEEPROM select CRC32 ---help--- diff --git a/drivers/media/video/usbvision/Kconfig b/drivers/media/video/usbvision/Kconfig index 74e1d3075a20..fc24ef05b3f3 100644 --- a/drivers/media/video/usbvision/Kconfig +++ b/drivers/media/video/usbvision/Kconfig @@ -1,7 +1,7 @@ config VIDEO_USBVISION tristate "USB video devices based on Nogatech NT1003/1004/1005" depends on I2C && VIDEO_V4L2 - select MEDIA_TUNER + select VIDEO_TUNER select VIDEO_SAA711X if VIDEO_HELPER_CHIPS_AUTO ---help--- There are more than 50 different USB video devices based on -- cgit v1.2.3 From 3929c0f9acc62a2fee99387b3cb58fd2a3668cd3 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 6 May 2008 12:38:24 -0300 Subject: V4L/DVB (7847): Simplifies Kconfig rules Since all tuners are dependent of I2C, move I2C dependency to MEDIA_TUNER. Also, simplifies the dependencies for the other Kconfig items. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/Kconfig | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/drivers/media/common/tuners/Kconfig b/drivers/media/common/tuners/Kconfig index c0b472eaeb7d..ecbccc3cdc54 100644 --- a/drivers/media/common/tuners/Kconfig +++ b/drivers/media/common/tuners/Kconfig @@ -19,8 +19,8 @@ config MEDIA_ATTACH config MEDIA_TUNER tristate - default DVB_CORE || VIDEO_DEV - depends on DVB_CORE || VIDEO_DEV + default VIDEO_MEDIA && I2C + depends on VIDEO_MEDIA && I2C select MEDIA_TUNER_XC2028 if !MEDIA_TUNER_CUSTOMIZE select MEDIA_TUNER_XC5000 if !MEDIA_TUNER_CUSTOMIZE select MEDIA_TUNER_MT20XX if !MEDIA_TUNER_CUSTOMIZE @@ -46,7 +46,6 @@ if MEDIA_TUNER_CUSTOMIZE config MEDIA_TUNER_SIMPLE tristate "Simple tuner support" - depends on I2C select MEDIA_TUNER_TDA9887 default m if MEDIA_TUNER_CUSTOMIZE help @@ -54,7 +53,6 @@ config MEDIA_TUNER_SIMPLE config MEDIA_TUNER_TDA8290 tristate "TDA 8290/8295 + 8275(a)/18271 tuner combo" - depends on I2C select MEDIA_TUNER_TDA827X select MEDIA_TUNER_TDA18271 default m if MEDIA_TUNER_CUSTOMIZE @@ -63,21 +61,18 @@ config MEDIA_TUNER_TDA8290 config MEDIA_TUNER_TDA827X tristate "Philips TDA827X silicon tuner" - depends on DVB_CORE && I2C default m if DVB_FE_CUSTOMISE help A DVB-T silicon tuner module. Say Y when you want to support this tuner. config MEDIA_TUNER_TDA18271 tristate "NXP TDA18271 silicon tuner" - depends on I2C default m if DVB_FE_CUSTOMISE help A silicon tuner module. Say Y when you want to support this tuner. config MEDIA_TUNER_TDA9887 tristate "TDA 9885/6/7 analog IF demodulator" - depends on I2C default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for Philips TDA9885/6/7 @@ -85,63 +80,56 @@ config MEDIA_TUNER_TDA9887 config MEDIA_TUNER_TEA5761 tristate "TEA 5761 radio tuner (EXPERIMENTAL)" - depends on I2C && EXPERIMENTAL + depends on EXPERIMENTAL default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the Philips TEA5761 radio tuner. config MEDIA_TUNER_TEA5767 tristate "TEA 5767 radio tuner" - depends on I2C default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the Philips TEA5767 radio tuner. config MEDIA_TUNER_MT20XX tristate "Microtune 2032 / 2050 tuners" - depends on I2C default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the MT2032 / MT2050 tuner. config MEDIA_TUNER_MT2060 tristate "Microtune MT2060 silicon IF tuner" - depends on I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon IF tuner MT2060 from Microtune. config MEDIA_TUNER_MT2266 tristate "Microtune MT2266 silicon tuner" - depends on I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon baseband tuner MT2266 from Microtune. config MEDIA_TUNER_MT2131 tristate "Microtune MT2131 silicon tuner" - depends on I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon baseband tuner MT2131 from Microtune. config MEDIA_TUNER_QT1010 tristate "Quantek QT1010 silicon tuner" - depends on DVB_CORE && I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon tuner QT1010 from Quantek. config MEDIA_TUNER_XC2028 tristate "XCeive xc2028/xc3028 tuners" - depends on I2C && FW_LOADER + depends on FW_LOADER default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the xc2028/xc3028 tuners. config MEDIA_TUNER_XC5000 tristate "Xceive XC5000 silicon tuner" - depends on I2C select FW_LOADER default m if DVB_FE_CUSTOMISE help -- cgit v1.2.3 From eabcaf32041fcd04672049e76124bd4cd63b1cbf Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 6 May 2008 13:44:03 -0300 Subject: V4L/DVB (7848): Fix dependencies for tuner-xc2028 and em28xx-dvb em28xx-dvb doesn't need FW_LOADER. Instead, tuner-xc2028 needs to select FW_LOADER. Also, this can happen only if HOTPLUG is selected, since FW_LOADER is dependent on HOTPLUG. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/Kconfig | 5 +++-- drivers/media/video/em28xx/Kconfig | 1 - 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/common/tuners/Kconfig b/drivers/media/common/tuners/Kconfig index ecbccc3cdc54..4fb77bc71394 100644 --- a/drivers/media/common/tuners/Kconfig +++ b/drivers/media/common/tuners/Kconfig @@ -21,7 +21,7 @@ config MEDIA_TUNER tristate default VIDEO_MEDIA && I2C depends on VIDEO_MEDIA && I2C - select MEDIA_TUNER_XC2028 if !MEDIA_TUNER_CUSTOMIZE + select MEDIA_TUNER_XC2028 if !MEDIA_TUNER_CUSTOMIZE && HOTPLUG select MEDIA_TUNER_XC5000 if !MEDIA_TUNER_CUSTOMIZE select MEDIA_TUNER_MT20XX if !MEDIA_TUNER_CUSTOMIZE select MEDIA_TUNER_TDA8290 if !MEDIA_TUNER_CUSTOMIZE @@ -123,7 +123,8 @@ config MEDIA_TUNER_QT1010 config MEDIA_TUNER_XC2028 tristate "XCeive xc2028/xc3028 tuners" - depends on FW_LOADER + depends on HOTPLUG + select FW_LOADER default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the xc2028/xc3028 tuners. diff --git a/drivers/media/video/em28xx/Kconfig b/drivers/media/video/em28xx/Kconfig index 9caffed2b6b8..16a5af30e9d1 100644 --- a/drivers/media/video/em28xx/Kconfig +++ b/drivers/media/video/em28xx/Kconfig @@ -35,7 +35,6 @@ config VIDEO_EM28XX_DVB select DVB_LGDT330X if !DVB_FE_CUSTOMISE select DVB_ZL10353 if !DVB_FE_CUSTOMISE select VIDEOBUF_DVB - select FW_LOADER ---help--- This adds support for DVB cards based on the Empiatech em28xx chips. -- cgit v1.2.3 From ec44c9aed0eddceaef3c6b4d23f6d7702ec57b4d Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 6 May 2008 13:46:12 -0300 Subject: V4L/DVB (7849): cx88: fix Kconfig depencencies for FW_LOADER cx88 doesn't need support for FW_LOADER. Instead, this is required only for cx88-blackbird. Also, cx88-blackbird depends on HOTPLUG, due to FW_LOADER dependency. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/cx88/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/video/cx88/Kconfig b/drivers/media/video/cx88/Kconfig index f1e799141256..10e20d8196dc 100644 --- a/drivers/media/video/cx88/Kconfig +++ b/drivers/media/video/cx88/Kconfig @@ -2,7 +2,6 @@ config VIDEO_CX88 tristate "Conexant 2388x (bt878 successor) support" depends on VIDEO_DEV && PCI && I2C && INPUT select I2C_ALGOBIT - select FW_LOADER select VIDEO_BTCX select VIDEOBUF_DMA_SG select VIDEO_TUNER @@ -34,8 +33,9 @@ config VIDEO_CX88_ALSA config VIDEO_CX88_BLACKBIRD tristate "Blackbird MPEG encoder support (cx2388x + cx23416)" - depends on VIDEO_CX88 + depends on VIDEO_CX88 && HOTPLUG select VIDEO_CX2341X + select FW_LOADER ---help--- This adds support for MPEG encoder cards based on the Blackbird reference design, using the Conexant 2388x -- cgit v1.2.3 From 755a18baad393836c88ce92c3b7198c70e2e3205 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 6 May 2008 14:09:01 -0300 Subject: V4L/DVB (7851): Fix FW_LOADER depencency at v4l/dvb Since: 1) FW_LOADER is defined as: config FW_LOADER tristate "Userspace firmware loading support" depends on HOTPLUG 2) several V4L/DVB driver just selects it; 3) select is not smart enough to auto-select HOTPLUG, if select FW_LOADER. So, All drivers that select FW_LOADER should also depend on HOTPLUG. An easier solution (for the end-user perspective) would be to "select HOTPLUG". However, live is not simple. This would cause recursive dependency issues like this one: drivers/usb/Kconfig:62:error: found recursive dependency: USB -> USB_OHCI_HCD -> I2C -> MEDIA_TUNER -> MEDIA_TUNER_XC2028 -> HOTPLUG -> PCCARD -> PCMCIA -> USB_ARCH_HAS_HCD -> MOUSE_APPLETOUCH -> USB Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/Kconfig | 1 + drivers/media/dvb/bt8xx/Kconfig | 1 + drivers/media/dvb/dvb-usb/Kconfig | 1 + drivers/media/dvb/frontends/Kconfig | 16 ++++++++-------- drivers/media/dvb/ttpci/Kconfig | 2 ++ drivers/media/dvb/ttusb-dec/Kconfig | 1 + drivers/media/video/bt8xx/Kconfig | 1 + drivers/media/video/cx18/Kconfig | 2 ++ drivers/media/video/cx23885/Kconfig | 1 + drivers/media/video/cx25840/Kconfig | 1 + drivers/media/video/ivtv/Kconfig | 2 ++ drivers/media/video/pvrusb2/Kconfig | 1 + drivers/media/video/saa7134/Kconfig | 1 + 13 files changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/media/common/tuners/Kconfig b/drivers/media/common/tuners/Kconfig index 4fb77bc71394..10f12bad1044 100644 --- a/drivers/media/common/tuners/Kconfig +++ b/drivers/media/common/tuners/Kconfig @@ -131,6 +131,7 @@ config MEDIA_TUNER_XC2028 config MEDIA_TUNER_XC5000 tristate "Xceive XC5000 silicon tuner" + depends on HOTPLUG select FW_LOADER default m if DVB_FE_CUSTOMISE help diff --git a/drivers/media/dvb/bt8xx/Kconfig b/drivers/media/dvb/bt8xx/Kconfig index d1239b8342f8..7588db1319d0 100644 --- a/drivers/media/dvb/bt8xx/Kconfig +++ b/drivers/media/dvb/bt8xx/Kconfig @@ -1,6 +1,7 @@ config DVB_BT8XX tristate "BT8xx based PCI cards" depends on DVB_CORE && PCI && I2C && VIDEO_BT848 + depends on HOTPLUG # due to FW_LOADER select DVB_MT352 if !DVB_FE_CUSTOMISE select DVB_SP887X if !DVB_FE_CUSTOMISE select DVB_NXT6000 if !DVB_FE_CUSTOMISE diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig index 4c1cff9feb2e..cf4584e48b6d 100644 --- a/drivers/media/dvb/dvb-usb/Kconfig +++ b/drivers/media/dvb/dvb-usb/Kconfig @@ -1,6 +1,7 @@ config DVB_USB tristate "Support for various USB DVB devices" depends on DVB_CORE && USB && I2C + depends on HOTPLUG # due to FW_LOADER select FW_LOADER help By enabling this you will be able to choose the various supported diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig index 6d2384605927..47d0215084c6 100644 --- a/drivers/media/dvb/frontends/Kconfig +++ b/drivers/media/dvb/frontends/Kconfig @@ -97,7 +97,7 @@ comment "DVB-T (terrestrial) frontends" config DVB_SP8870 tristate "Spase sp8870 based" - depends on DVB_CORE && I2C + depends on DVB_CORE && I2C && HOTPLUG default m if DVB_FE_CUSTOMISE select FW_LOADER help @@ -110,7 +110,7 @@ config DVB_SP8870 config DVB_SP887X tristate "Spase sp887x based" - depends on DVB_CORE && I2C + depends on DVB_CORE && I2C && HOTPLUG default m if DVB_FE_CUSTOMISE select FW_LOADER help @@ -144,7 +144,7 @@ config DVB_L64781 config DVB_TDA1004X tristate "Philips TDA10045H/TDA10046H based" - depends on DVB_CORE && I2C + depends on DVB_CORE && I2C && HOTPLUG default m if DVB_FE_CUSTOMISE select FW_LOADER help @@ -211,7 +211,7 @@ config DVB_DIB7000P config DVB_TDA10048 tristate "Philips TDA10048HN based" - depends on DVB_CORE && I2C + depends on DVB_CORE && I2C && HOTPLUG default m if DVB_FE_CUSTOMISE select FW_LOADER help @@ -253,7 +253,7 @@ comment "ATSC (North American/Korean Terrestrial/Cable DTV) frontends" config DVB_NXT200X tristate "NxtWave Communications NXT2002/NXT2004 based" - depends on DVB_CORE && I2C + depends on DVB_CORE && I2C && HOTPLUG default m if DVB_FE_CUSTOMISE select FW_LOADER help @@ -268,7 +268,7 @@ config DVB_NXT200X config DVB_OR51211 tristate "Oren OR51211 based" - depends on DVB_CORE && I2C + depends on DVB_CORE && I2C && HOTPLUG default m if DVB_FE_CUSTOMISE select FW_LOADER help @@ -281,7 +281,7 @@ config DVB_OR51211 config DVB_OR51132 tristate "Oren OR51132 based" - depends on DVB_CORE && I2C + depends on DVB_CORE && I2C && HOTPLUG default m if DVB_FE_CUSTOMISE select FW_LOADER help @@ -297,7 +297,7 @@ config DVB_OR51132 config DVB_BCM3510 tristate "Broadcom BCM3510" - depends on DVB_CORE && I2C + depends on DVB_CORE && I2C && HOTPLUG default m if DVB_FE_CUSTOMISE select FW_LOADER help diff --git a/drivers/media/dvb/ttpci/Kconfig b/drivers/media/dvb/ttpci/Kconfig index ae882432dd3d..d4339b1b3b68 100644 --- a/drivers/media/dvb/ttpci/Kconfig +++ b/drivers/media/dvb/ttpci/Kconfig @@ -5,6 +5,7 @@ config TTPCI_EEPROM config DVB_AV7110 tristate "AV7110 cards" depends on DVB_CORE && PCI && I2C + depends on HOTPLUG select FW_LOADER if !DVB_AV7110_FIRMWARE select TTPCI_EEPROM select VIDEO_SAA7146_VV @@ -123,6 +124,7 @@ config DVB_BUDGET_AV depends on DVB_BUDGET_CORE && I2C select VIDEO_SAA7146_VV depends on VIDEO_DEV # dependencies of VIDEO_SAA7146_VV + depends on HOTPLUG # dependency of FW_LOADER select DVB_PLL if !DVB_FE_CUSTOMISE select DVB_STV0299 if !DVB_FE_CUSTOMISE select DVB_TDA1004X if !DVB_FE_CUSTOMISE diff --git a/drivers/media/dvb/ttusb-dec/Kconfig b/drivers/media/dvb/ttusb-dec/Kconfig index 83611012ef34..0712899e39a4 100644 --- a/drivers/media/dvb/ttusb-dec/Kconfig +++ b/drivers/media/dvb/ttusb-dec/Kconfig @@ -1,6 +1,7 @@ config DVB_TTUSB_DEC tristate "Technotrend/Hauppauge USB DEC devices" depends on DVB_CORE && USB + depends on HOTPLUG # due to FW_LOADER select FW_LOADER select CRC32 help diff --git a/drivers/media/video/bt8xx/Kconfig b/drivers/media/video/bt8xx/Kconfig index cfc822bb502a..24a34fc1f2b3 100644 --- a/drivers/media/video/bt8xx/Kconfig +++ b/drivers/media/video/bt8xx/Kconfig @@ -1,6 +1,7 @@ config VIDEO_BT848 tristate "BT848 Video For Linux" depends on VIDEO_DEV && PCI && I2C && VIDEO_V4L2 && INPUT + depends on HOTPLUG # due to FW_LOADER select I2C_ALGOBIT select FW_LOADER select VIDEO_BTCX diff --git a/drivers/media/video/cx18/Kconfig b/drivers/media/video/cx18/Kconfig index be654a27bd3c..35a55998a8d3 100644 --- a/drivers/media/video/cx18/Kconfig +++ b/drivers/media/video/cx18/Kconfig @@ -1,6 +1,8 @@ config VIDEO_CX18 tristate "Conexant cx23418 MPEG encoder support" depends on VIDEO_V4L2 && DVB_CORE && PCI && I2C && EXPERIMENTAL + depends on INPUT # due to VIDEO_IR + depends on HOTPLUG # due to FW_LOADER select I2C_ALGOBIT select FW_LOADER select VIDEO_IR diff --git a/drivers/media/video/cx23885/Kconfig b/drivers/media/video/cx23885/Kconfig index 491a0052993f..7bf14c9a15c7 100644 --- a/drivers/media/video/cx23885/Kconfig +++ b/drivers/media/video/cx23885/Kconfig @@ -1,6 +1,7 @@ config VIDEO_CX23885 tristate "Conexant cx23885 (2388x successor) support" depends on DVB_CORE && VIDEO_DEV && PCI && I2C && INPUT + depends on HOTPLUG # due to FW_LOADER select I2C_ALGOBIT select FW_LOADER select VIDEO_BTCX diff --git a/drivers/media/video/cx25840/Kconfig b/drivers/media/video/cx25840/Kconfig index 7cf29a03ed63..448f4cd0ce34 100644 --- a/drivers/media/video/cx25840/Kconfig +++ b/drivers/media/video/cx25840/Kconfig @@ -1,6 +1,7 @@ config VIDEO_CX25840 tristate "Conexant CX2584x audio/video decoders" depends on VIDEO_V4L2 && I2C && EXPERIMENTAL + depends on HOTPLUG # due to FW_LOADER select FW_LOADER ---help--- Support for the Conexant CX2584x audio/video decoders. diff --git a/drivers/media/video/ivtv/Kconfig b/drivers/media/video/ivtv/Kconfig index b6171702c4d0..5d7ee8fcdd50 100644 --- a/drivers/media/video/ivtv/Kconfig +++ b/drivers/media/video/ivtv/Kconfig @@ -1,6 +1,8 @@ config VIDEO_IVTV tristate "Conexant cx23416/cx23415 MPEG encoder/decoder support" depends on VIDEO_V4L1 && VIDEO_V4L2 && PCI && I2C && EXPERIMENTAL + depends on INPUT # due to VIDEO_IR + depends on HOTPLUG # due to FW_LOADER select I2C_ALGOBIT select FW_LOADER select VIDEO_IR diff --git a/drivers/media/video/pvrusb2/Kconfig b/drivers/media/video/pvrusb2/Kconfig index 31634f6ce627..e2a7a508c2e9 100644 --- a/drivers/media/video/pvrusb2/Kconfig +++ b/drivers/media/video/pvrusb2/Kconfig @@ -1,6 +1,7 @@ config VIDEO_PVRUSB2 tristate "Hauppauge WinTV-PVR USB2 support" depends on VIDEO_V4L2 && I2C + depends on HOTPLUG # due to FW_LOADER select FW_LOADER select VIDEO_TUNER select VIDEO_TVEEPROM diff --git a/drivers/media/video/saa7134/Kconfig b/drivers/media/video/saa7134/Kconfig index dbdfbaaaed24..83f076abce35 100644 --- a/drivers/media/video/saa7134/Kconfig +++ b/drivers/media/video/saa7134/Kconfig @@ -27,6 +27,7 @@ config VIDEO_SAA7134_ALSA config VIDEO_SAA7134_DVB tristate "DVB/ATSC Support for saa7134 based TV cards" depends on VIDEO_SAA7134 && DVB_CORE + depends on HOTPLUG # due to FW_LOADER select VIDEOBUF_DVB select FW_LOADER select DVB_PLL if !DVB_FE_CUSTOMISE -- cgit v1.2.3 From feb5bce24ed4d90c0a5710a669072c778a2c5148 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Thu, 1 May 2008 09:22:13 -0300 Subject: V4L/DVB (7852): ivtv: prefix ivtv external functions with ivtv_ Fix conflict with cx18 driver. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/ivtv/ivtv-controls.c | 4 ++-- drivers/media/video/ivtv/ivtv-ioctl.c | 16 ++++++++-------- drivers/media/video/ivtv/ivtv-ioctl.h | 6 +++--- drivers/media/video/ivtv/ivtv-vbi.c | 3 ++- 4 files changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/media/video/ivtv/ivtv-controls.c b/drivers/media/video/ivtv/ivtv-controls.c index 8c02fa661591..c7e449f6397b 100644 --- a/drivers/media/video/ivtv/ivtv-controls.c +++ b/drivers/media/video/ivtv/ivtv-controls.c @@ -181,12 +181,12 @@ static int ivtv_setup_vbi_fmt(struct ivtv *itv, enum v4l2_mpeg_stream_vbi_fmt fm return 0; } /* Need sliced data for mpeg insertion */ - if (get_service_set(itv->vbi.sliced_in) == 0) { + if (ivtv_get_service_set(itv->vbi.sliced_in) == 0) { if (itv->is_60hz) itv->vbi.sliced_in->service_set = V4L2_SLICED_CAPTION_525; else itv->vbi.sliced_in->service_set = V4L2_SLICED_WSS_625; - expand_service_set(itv->vbi.sliced_in, itv->is_50hz); + ivtv_expand_service_set(itv->vbi.sliced_in, itv->is_50hz); } return 0; } diff --git a/drivers/media/video/ivtv/ivtv-ioctl.c b/drivers/media/video/ivtv/ivtv-ioctl.c index d508b5d0538c..26cc0f6699fd 100644 --- a/drivers/media/video/ivtv/ivtv-ioctl.c +++ b/drivers/media/video/ivtv/ivtv-ioctl.c @@ -38,7 +38,7 @@ #include #include -u16 service2vbi(int type) +u16 ivtv_service2vbi(int type) { switch (type) { case V4L2_SLICED_TELETEXT_B: @@ -88,7 +88,7 @@ static u16 select_service_from_set(int field, int line, u16 set, int is_pal) return 0; } -void expand_service_set(struct v4l2_sliced_vbi_format *fmt, int is_pal) +void ivtv_expand_service_set(struct v4l2_sliced_vbi_format *fmt, int is_pal) { u16 set = fmt->service_set; int f, l; @@ -115,7 +115,7 @@ static int check_service_set(struct v4l2_sliced_vbi_format *fmt, int is_pal) return set != 0; } -u16 get_service_set(struct v4l2_sliced_vbi_format *fmt) +u16 ivtv_get_service_set(struct v4l2_sliced_vbi_format *fmt) { int f, l; u16 set = 0; @@ -466,7 +466,7 @@ static int ivtv_get_fmt(struct ivtv *itv, int streamtype, struct v4l2_format *fm vbifmt->service_lines[0][23] = V4L2_SLICED_WSS_625; vbifmt->service_lines[0][16] = V4L2_SLICED_VPS; } - vbifmt->service_set = get_service_set(vbifmt); + vbifmt->service_set = ivtv_get_service_set(vbifmt); break; } @@ -481,12 +481,12 @@ static int ivtv_get_fmt(struct ivtv *itv, int streamtype, struct v4l2_format *fm if (streamtype == IVTV_DEC_STREAM_TYPE_VBI) { vbifmt->service_set = itv->is_50hz ? V4L2_SLICED_VBI_625 : V4L2_SLICED_VBI_525; - expand_service_set(vbifmt, itv->is_50hz); + ivtv_expand_service_set(vbifmt, itv->is_50hz); break; } itv->video_dec_func(itv, VIDIOC_G_FMT, fmt); - vbifmt->service_set = get_service_set(vbifmt); + vbifmt->service_set = ivtv_get_service_set(vbifmt); break; } case V4L2_BUF_TYPE_VBI_OUTPUT: @@ -640,9 +640,9 @@ static int ivtv_try_or_set_fmt(struct ivtv *itv, int streamtype, memset(vbifmt->reserved, 0, sizeof(vbifmt->reserved)); if (vbifmt->service_set) - expand_service_set(vbifmt, itv->is_50hz); + ivtv_expand_service_set(vbifmt, itv->is_50hz); set = check_service_set(vbifmt, itv->is_50hz); - vbifmt->service_set = get_service_set(vbifmt); + vbifmt->service_set = ivtv_get_service_set(vbifmt); if (!set_fmt) return 0; diff --git a/drivers/media/video/ivtv/ivtv-ioctl.h b/drivers/media/video/ivtv/ivtv-ioctl.h index a03351b6853d..4e67f0ed1fc0 100644 --- a/drivers/media/video/ivtv/ivtv-ioctl.h +++ b/drivers/media/video/ivtv/ivtv-ioctl.h @@ -21,9 +21,9 @@ #ifndef IVTV_IOCTL_H #define IVTV_IOCTL_H -u16 service2vbi(int type); -void expand_service_set(struct v4l2_sliced_vbi_format *fmt, int is_pal); -u16 get_service_set(struct v4l2_sliced_vbi_format *fmt); +u16 ivtv_service2vbi(int type); +void ivtv_expand_service_set(struct v4l2_sliced_vbi_format *fmt, int is_pal); +u16 ivtv_get_service_set(struct v4l2_sliced_vbi_format *fmt); int ivtv_v4l2_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); int ivtv_v4l2_ioctls(struct ivtv *itv, struct file *filp, unsigned int cmd, void *arg); diff --git a/drivers/media/video/ivtv/ivtv-vbi.c b/drivers/media/video/ivtv/ivtv-vbi.c index c151bcf5519a..71798f0da27f 100644 --- a/drivers/media/video/ivtv/ivtv-vbi.c +++ b/drivers/media/video/ivtv/ivtv-vbi.c @@ -169,7 +169,8 @@ static void copy_vbi_data(struct ivtv *itv, int lines, u32 pts_stamp) linemask[0] |= (1 << l); else linemask[1] |= (1 << (l - 32)); - dst[sd + 12 + line * 43] = service2vbi(itv->vbi.sliced_data[i].id); + dst[sd + 12 + line * 43] = + ivtv_service2vbi(itv->vbi.sliced_data[i].id); memcpy(dst + sd + 12 + line * 43 + 1, itv->vbi.sliced_data[i].data, 42); line++; } -- cgit v1.2.3 From 6a4a79355bfa9ae6977556595a68f2e3a0e143f7 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Thu, 1 May 2008 09:34:54 -0300 Subject: V4L/DVB (7853): ivtv/cx18: fix compile warnings Fix compile warnings if MODULE is not defined. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/cx18/cx18-driver.c | 4 ++++ drivers/media/video/ivtv/ivtv-driver.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c index 3f55d47bc4b9..7813380dce3f 100644 --- a/drivers/media/video/cx18/cx18-driver.c +++ b/drivers/media/video/cx18/cx18-driver.c @@ -548,6 +548,7 @@ static int cx18_setup_pci(struct cx18 *cx, struct pci_dev *dev, return 0; } +#ifdef MODULE static u32 cx18_request_module(struct cx18 *cx, u32 hw, const char *name, u32 id) { @@ -560,18 +561,21 @@ static u32 cx18_request_module(struct cx18 *cx, u32 hw, CX18_DEBUG_INFO("Loaded module %s\n", name); return hw; } +#endif static void cx18_load_and_init_modules(struct cx18 *cx) { u32 hw = cx->card->hw_all; int i; +#ifdef MODULE /* load modules */ #ifndef CONFIG_MEDIA_TUNER hw = cx18_request_module(cx, hw, "tuner", CX18_HW_TUNER); #endif #ifndef CONFIG_VIDEO_CS5345 hw = cx18_request_module(cx, hw, "cs5345", CX18_HW_CS5345); +#endif #endif /* check which i2c devices are actually found */ diff --git a/drivers/media/video/ivtv/ivtv-driver.c b/drivers/media/video/ivtv/ivtv-driver.c index ed020f722b05..a0756a9235d8 100644 --- a/drivers/media/video/ivtv/ivtv-driver.c +++ b/drivers/media/video/ivtv/ivtv-driver.c @@ -853,6 +853,7 @@ static int ivtv_setup_pci(struct ivtv *itv, struct pci_dev *dev, return 0; } +#ifdef MODULE static u32 ivtv_request_module(struct ivtv *itv, u32 hw, const char *name, u32 id) { @@ -865,12 +866,14 @@ static u32 ivtv_request_module(struct ivtv *itv, u32 hw, IVTV_DEBUG_INFO("Loaded module %s\n", name); return hw; } +#endif static void ivtv_load_and_init_modules(struct ivtv *itv) { u32 hw = itv->card->hw_all; unsigned i; +#ifdef MODULE /* load modules */ #ifndef CONFIG_MEDIA_TUNER hw = ivtv_request_module(itv, hw, "tuner", IVTV_HW_TUNER); @@ -910,6 +913,7 @@ static void ivtv_load_and_init_modules(struct ivtv *itv) #endif #ifndef CONFIG_VIDEO_M52790 hw = ivtv_request_module(itv, hw, "m52790", IVTV_HW_M52790); +#endif #endif /* check which i2c devices are actually found */ -- cgit v1.2.3 From 3f98387efa9333c5765d36e144c47c107d6ba64a Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Thu, 1 May 2008 10:31:12 -0300 Subject: V4L/DVB (7854): cx18/ivtv: improve and fix out-of-memory handling - don't show kernel backtrace when the allocation of the buffers fails: the normal ivtv/cx18 messages are clear enough and the backtrace scares users. - fix cleanup after the buffer allocation fails (caused kernel panic). Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/cx18/cx18-driver.c | 4 ++-- drivers/media/video/cx18/cx18-queue.c | 6 +++--- drivers/media/video/cx18/cx18-streams.c | 13 ++++++++----- drivers/media/video/cx18/cx18-streams.h | 2 +- drivers/media/video/ivtv/ivtv-driver.c | 4 ++-- drivers/media/video/ivtv/ivtv-queue.c | 12 +++++++----- drivers/media/video/ivtv/ivtv-streams.c | 13 ++++++++----- drivers/media/video/ivtv/ivtv-streams.h | 2 +- drivers/media/video/ivtv/ivtv-yuv.c | 2 +- drivers/media/video/ivtv/ivtvfb.c | 6 ++++-- 10 files changed, 37 insertions(+), 27 deletions(-) diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c index 7813380dce3f..9453223a3dea 100644 --- a/drivers/media/video/cx18/cx18-driver.c +++ b/drivers/media/video/cx18/cx18-driver.c @@ -805,7 +805,7 @@ static int __devinit cx18_probe(struct pci_dev *dev, return 0; free_streams: - cx18_streams_cleanup(cx); + cx18_streams_cleanup(cx, 1); free_irq: free_irq(cx->dev->irq, (void *)cx); free_i2c: @@ -908,7 +908,7 @@ static void cx18_remove(struct pci_dev *pci_dev) cx18_halt_firmware(cx); - cx18_streams_cleanup(cx); + cx18_streams_cleanup(cx, 1); exit_cx18_i2c(cx); diff --git a/drivers/media/video/cx18/cx18-queue.c b/drivers/media/video/cx18/cx18-queue.c index 65af1bb507ca..4ef6996b2048 100644 --- a/drivers/media/video/cx18/cx18-queue.c +++ b/drivers/media/video/cx18/cx18-queue.c @@ -239,12 +239,12 @@ int cx18_stream_alloc(struct cx18_stream *s) /* allocate stream buffers. Initially all buffers are in q_free. */ for (i = 0; i < s->buffers; i++) { - struct cx18_buffer *buf = - kzalloc(sizeof(struct cx18_buffer), GFP_KERNEL); + struct cx18_buffer *buf = kzalloc(sizeof(struct cx18_buffer), + GFP_KERNEL|__GFP_NOWARN); if (buf == NULL) break; - buf->buf = kmalloc(s->buf_size, GFP_KERNEL); + buf->buf = kmalloc(s->buf_size, GFP_KERNEL|__GFP_NOWARN); if (buf->buf == NULL) { kfree(buf); break; diff --git a/drivers/media/video/cx18/cx18-streams.c b/drivers/media/video/cx18/cx18-streams.c index afb141b2027a..4ca9d847f1b1 100644 --- a/drivers/media/video/cx18/cx18-streams.c +++ b/drivers/media/video/cx18/cx18-streams.c @@ -218,7 +218,7 @@ int cx18_streams_setup(struct cx18 *cx) return 0; /* One or more streams could not be initialized. Clean 'em all up. */ - cx18_streams_cleanup(cx); + cx18_streams_cleanup(cx, 0); return -ENOMEM; } @@ -296,12 +296,12 @@ int cx18_streams_register(struct cx18 *cx) return 0; /* One or more streams could not be initialized. Clean 'em all up. */ - cx18_streams_cleanup(cx); + cx18_streams_cleanup(cx, 1); return -ENOMEM; } /* Unregister v4l2 devices */ -void cx18_streams_cleanup(struct cx18 *cx) +void cx18_streams_cleanup(struct cx18 *cx, int unregister) { struct video_device *vdev; int type; @@ -319,8 +319,11 @@ void cx18_streams_cleanup(struct cx18 *cx) cx18_stream_free(&cx->streams[type]); - /* Unregister device */ - video_unregister_device(vdev); + /* Unregister or release device */ + if (unregister) + video_unregister_device(vdev); + else + video_device_release(vdev); } } diff --git a/drivers/media/video/cx18/cx18-streams.h b/drivers/media/video/cx18/cx18-streams.h index 8c7ba7d2fa79..f327e947b24f 100644 --- a/drivers/media/video/cx18/cx18-streams.h +++ b/drivers/media/video/cx18/cx18-streams.h @@ -24,7 +24,7 @@ u32 cx18_find_handle(struct cx18 *cx); int cx18_streams_setup(struct cx18 *cx); int cx18_streams_register(struct cx18 *cx); -void cx18_streams_cleanup(struct cx18 *cx); +void cx18_streams_cleanup(struct cx18 *cx, int unregister); /* Capture related */ int cx18_start_v4l2_encode_stream(struct cx18_stream *s); diff --git a/drivers/media/video/ivtv/ivtv-driver.c b/drivers/media/video/ivtv/ivtv-driver.c index a0756a9235d8..797e636771da 100644 --- a/drivers/media/video/ivtv/ivtv-driver.c +++ b/drivers/media/video/ivtv/ivtv-driver.c @@ -1232,7 +1232,7 @@ static int __devinit ivtv_probe(struct pci_dev *dev, return 0; free_streams: - ivtv_streams_cleanup(itv); + ivtv_streams_cleanup(itv, 1); free_irq: free_irq(itv->dev->irq, (void *)itv); free_i2c: @@ -1377,7 +1377,7 @@ static void ivtv_remove(struct pci_dev *pci_dev) flush_workqueue(itv->irq_work_queues); destroy_workqueue(itv->irq_work_queues); - ivtv_streams_cleanup(itv); + ivtv_streams_cleanup(itv, 1); ivtv_udma_free(itv); exit_ivtv_i2c(itv); diff --git a/drivers/media/video/ivtv/ivtv-queue.c b/drivers/media/video/ivtv/ivtv-queue.c index 3e1deec67a5e..fc8b1eaa333b 100644 --- a/drivers/media/video/ivtv/ivtv-queue.c +++ b/drivers/media/video/ivtv/ivtv-queue.c @@ -203,14 +203,14 @@ int ivtv_stream_alloc(struct ivtv_stream *s) s->dma != PCI_DMA_NONE ? "DMA " : "", s->name, s->buffers, s->buf_size, s->buffers * s->buf_size / 1024); - s->sg_pending = kzalloc(SGsize, GFP_KERNEL); + s->sg_pending = kzalloc(SGsize, GFP_KERNEL|__GFP_NOWARN); if (s->sg_pending == NULL) { IVTV_ERR("Could not allocate sg_pending for %s stream\n", s->name); return -ENOMEM; } s->sg_pending_size = 0; - s->sg_processing = kzalloc(SGsize, GFP_KERNEL); + s->sg_processing = kzalloc(SGsize, GFP_KERNEL|__GFP_NOWARN); if (s->sg_processing == NULL) { IVTV_ERR("Could not allocate sg_processing for %s stream\n", s->name); kfree(s->sg_pending); @@ -219,7 +219,8 @@ int ivtv_stream_alloc(struct ivtv_stream *s) } s->sg_processing_size = 0; - s->sg_dma = kzalloc(sizeof(struct ivtv_sg_element), GFP_KERNEL); + s->sg_dma = kzalloc(sizeof(struct ivtv_sg_element), + GFP_KERNEL|__GFP_NOWARN); if (s->sg_dma == NULL) { IVTV_ERR("Could not allocate sg_dma for %s stream\n", s->name); kfree(s->sg_pending); @@ -235,11 +236,12 @@ int ivtv_stream_alloc(struct ivtv_stream *s) /* allocate stream buffers. Initially all buffers are in q_free. */ for (i = 0; i < s->buffers; i++) { - struct ivtv_buffer *buf = kzalloc(sizeof(struct ivtv_buffer), GFP_KERNEL); + struct ivtv_buffer *buf = kzalloc(sizeof(struct ivtv_buffer), + GFP_KERNEL|__GFP_NOWARN); if (buf == NULL) break; - buf->buf = kmalloc(s->buf_size + 256, GFP_KERNEL); + buf->buf = kmalloc(s->buf_size + 256, GFP_KERNEL|__GFP_NOWARN); if (buf->buf == NULL) { kfree(buf); break; diff --git a/drivers/media/video/ivtv/ivtv-streams.c b/drivers/media/video/ivtv/ivtv-streams.c index 4ab8d36831ba..c47c2b945147 100644 --- a/drivers/media/video/ivtv/ivtv-streams.c +++ b/drivers/media/video/ivtv/ivtv-streams.c @@ -244,7 +244,7 @@ int ivtv_streams_setup(struct ivtv *itv) return 0; /* One or more streams could not be initialized. Clean 'em all up. */ - ivtv_streams_cleanup(itv); + ivtv_streams_cleanup(itv, 0); return -ENOMEM; } @@ -304,12 +304,12 @@ int ivtv_streams_register(struct ivtv *itv) return 0; /* One or more streams could not be initialized. Clean 'em all up. */ - ivtv_streams_cleanup(itv); + ivtv_streams_cleanup(itv, 1); return -ENOMEM; } /* Unregister v4l2 devices */ -void ivtv_streams_cleanup(struct ivtv *itv) +void ivtv_streams_cleanup(struct ivtv *itv, int unregister) { int type; @@ -322,8 +322,11 @@ void ivtv_streams_cleanup(struct ivtv *itv) continue; ivtv_stream_free(&itv->streams[type]); - /* Unregister device */ - video_unregister_device(vdev); + /* Unregister or release device */ + if (unregister) + video_unregister_device(vdev); + else + video_device_release(vdev); } } diff --git a/drivers/media/video/ivtv/ivtv-streams.h b/drivers/media/video/ivtv/ivtv-streams.h index 3d76a415fbd8..a653a5136417 100644 --- a/drivers/media/video/ivtv/ivtv-streams.h +++ b/drivers/media/video/ivtv/ivtv-streams.h @@ -23,7 +23,7 @@ int ivtv_streams_setup(struct ivtv *itv); int ivtv_streams_register(struct ivtv *itv); -void ivtv_streams_cleanup(struct ivtv *itv); +void ivtv_streams_cleanup(struct ivtv *itv, int unregister); /* Capture related */ int ivtv_start_v4l2_encode_stream(struct ivtv_stream *s); diff --git a/drivers/media/video/ivtv/ivtv-yuv.c b/drivers/media/video/ivtv/ivtv-yuv.c index 62f70bd5e3cb..a9417f6e4087 100644 --- a/drivers/media/video/ivtv/ivtv-yuv.c +++ b/drivers/media/video/ivtv/ivtv-yuv.c @@ -908,7 +908,7 @@ static void ivtv_yuv_init(struct ivtv *itv) } /* We need a buffer for blanking when Y plane is offset - non-fatal if we can't get one */ - yi->blanking_ptr = kzalloc(720 * 16, GFP_KERNEL); + yi->blanking_ptr = kzalloc(720 * 16, GFP_KERNEL|__GFP_NOWARN); if (yi->blanking_ptr) { yi->blanking_dmaptr = pci_map_single(itv->dev, yi->blanking_ptr, 720*16, PCI_DMA_TODEVICE); } else { diff --git a/drivers/media/video/ivtv/ivtvfb.c b/drivers/media/video/ivtv/ivtvfb.c index df789f683e63..73be154f7f05 100644 --- a/drivers/media/video/ivtv/ivtvfb.c +++ b/drivers/media/video/ivtv/ivtvfb.c @@ -948,7 +948,8 @@ static int ivtvfb_init_vidmode(struct ivtv *itv) } /* Allocate the pseudo palette */ - oi->ivtvfb_info.pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL); + oi->ivtvfb_info.pseudo_palette = + kmalloc(sizeof(u32) * 16, GFP_KERNEL|__GFP_NOWARN); if (!oi->ivtvfb_info.pseudo_palette) { IVTVFB_ERR("abort, unable to alloc pseudo pallete\n"); @@ -1056,7 +1057,8 @@ static int ivtvfb_init_card(struct ivtv *itv) return -EBUSY; } - itv->osd_info = kzalloc(sizeof(struct osd_info), GFP_ATOMIC); + itv->osd_info = kzalloc(sizeof(struct osd_info), + GFP_ATOMIC|__GFP_NOWARN); if (itv->osd_info == NULL) { IVTVFB_ERR("Failed to allocate memory for osd_info\n"); return -ENOMEM; -- cgit v1.2.3 From 50510993e0452e0941fd03f63aa08256dd9c7fdc Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Mon, 5 May 2008 18:25:22 -0300 Subject: V4L/DVB (7856): cx18/: possible cleanups This patch contains the following possible cleanups: - cx18-i2c.c should #include "cx18-i2c.h" for getting the prototypes of it's global functions - make the following needlessly global functions static: - cx18-fileops.c:cx18_claim_stream() - cx18-fileops.c:cx18_release_stream() - cx18-queue.c:cx18_queue_move() - remove the following unused functions: - cx18-driver.c:cx18_waitq() - cx18-queue.c:cx18_buf_copy_from_user() Signed-off-by: Adrian Bunk Reviewed-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/cx18/cx18-driver.c | 10 ---------- drivers/media/video/cx18/cx18-driver.h | 3 --- drivers/media/video/cx18/cx18-fileops.c | 4 ++-- drivers/media/video/cx18/cx18-fileops.h | 9 --------- drivers/media/video/cx18/cx18-i2c.c | 1 + drivers/media/video/cx18/cx18-queue.c | 16 +++------------- drivers/media/video/cx18/cx18-queue.h | 4 ---- 7 files changed, 6 insertions(+), 41 deletions(-) diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c index 9453223a3dea..3e9979eff3e0 100644 --- a/drivers/media/video/cx18/cx18-driver.c +++ b/drivers/media/video/cx18/cx18-driver.c @@ -164,16 +164,6 @@ MODULE_LICENSE("GPL"); MODULE_VERSION(CX18_VERSION); -int cx18_waitq(wait_queue_head_t *waitq) -{ - DEFINE_WAIT(wait); - - prepare_to_wait(waitq, &wait, TASK_INTERRUPTIBLE); - schedule(); - finish_wait(waitq, &wait); - return signal_pending(current) ? -EINTR : 0; -} - /* Generic utility functions */ int cx18_msleep_timeout(unsigned int msecs, int intr) { diff --git a/drivers/media/video/cx18/cx18-driver.h b/drivers/media/video/cx18/cx18-driver.h index 2ee939193bb7..a2a6c58d12fe 100644 --- a/drivers/media/video/cx18/cx18-driver.h +++ b/drivers/media/video/cx18/cx18-driver.h @@ -444,9 +444,6 @@ extern spinlock_t cx18_cards_lock; /* Return non-zero if a signal is pending */ int cx18_msleep_timeout(unsigned int msecs, int intr); -/* Wait on queue, returns -EINTR if interrupted */ -int cx18_waitq(wait_queue_head_t *waitq); - /* Read Hauppauge eeprom */ struct tveeprom; /* forward reference */ void cx18_read_eeprom(struct cx18 *cx, struct tveeprom *tv); diff --git a/drivers/media/video/cx18/cx18-fileops.c b/drivers/media/video/cx18/cx18-fileops.c index 69303065a294..91eff6e671a7 100644 --- a/drivers/media/video/cx18/cx18-fileops.c +++ b/drivers/media/video/cx18/cx18-fileops.c @@ -39,7 +39,7 @@ associated VBI streams are also automatically claimed. Possible error returns: -EBUSY if someone else has claimed the stream or 0 on success. */ -int cx18_claim_stream(struct cx18_open_id *id, int type) +static int cx18_claim_stream(struct cx18_open_id *id, int type) { struct cx18 *cx = id->cx; struct cx18_stream *s = &cx->streams[type]; @@ -87,7 +87,7 @@ int cx18_claim_stream(struct cx18_open_id *id, int type) /* This function releases a previously claimed stream. It will take into account associated VBI streams. */ -void cx18_release_stream(struct cx18_stream *s) +static void cx18_release_stream(struct cx18_stream *s) { struct cx18 *cx = s->cx; struct cx18_stream *s_vbi; diff --git a/drivers/media/video/cx18/cx18-fileops.h b/drivers/media/video/cx18/cx18-fileops.h index 16cdafbd24c5..46da0282fc7d 100644 --- a/drivers/media/video/cx18/cx18-fileops.h +++ b/drivers/media/video/cx18/cx18-fileops.h @@ -34,12 +34,3 @@ void cx18_stop_capture(struct cx18_open_id *id, int gop_end); void cx18_mute(struct cx18 *cx); void cx18_unmute(struct cx18 *cx); -/* Utilities */ - -/* Try to claim a stream for the filehandle. Return 0 on success, - -EBUSY if stream already claimed. Once a stream is claimed, it - remains claimed until the associated filehandle is closed. */ -int cx18_claim_stream(struct cx18_open_id *id, int type); - -/* Release a previously claimed stream. */ -void cx18_release_stream(struct cx18_stream *s); diff --git a/drivers/media/video/cx18/cx18-i2c.c b/drivers/media/video/cx18/cx18-i2c.c index 18c88d1e4833..4f08a4058d1a 100644 --- a/drivers/media/video/cx18/cx18-i2c.c +++ b/drivers/media/video/cx18/cx18-i2c.c @@ -25,6 +25,7 @@ #include "cx18-cards.h" #include "cx18-gpio.h" #include "cx18-av-core.h" +#include "cx18-i2c.h" #include diff --git a/drivers/media/video/cx18/cx18-queue.c b/drivers/media/video/cx18/cx18-queue.c index 4ef6996b2048..6990b77c6200 100644 --- a/drivers/media/video/cx18/cx18-queue.c +++ b/drivers/media/video/cx18/cx18-queue.c @@ -26,17 +26,6 @@ #include "cx18-queue.h" #include "cx18-scb.h" -int cx18_buf_copy_from_user(struct cx18_stream *s, struct cx18_buffer *buf, - const char __user *src, int copybytes) -{ - if (s->buf_size - buf->bytesused < copybytes) - copybytes = s->buf_size - buf->bytesused; - if (copy_from_user(buf->buf + buf->bytesused, src, copybytes)) - return -EFAULT; - buf->bytesused += copybytes; - return copybytes; -} - void cx18_buf_swap(struct cx18_buffer *buf) { int i; @@ -159,8 +148,9 @@ static void cx18_queue_move_buf(struct cx18_stream *s, struct cx18_queue *from, -ENOMEM is returned if the buffers could not be obtained, 0 if all buffers where obtained from the 'from' list and if non-zero then the number of stolen buffers is returned. */ -int cx18_queue_move(struct cx18_stream *s, struct cx18_queue *from, - struct cx18_queue *steal, struct cx18_queue *to, int needed_bytes) +static int cx18_queue_move(struct cx18_stream *s, struct cx18_queue *from, + struct cx18_queue *steal, struct cx18_queue *to, + int needed_bytes) { unsigned long flags; int rc = 0; diff --git a/drivers/media/video/cx18/cx18-queue.h b/drivers/media/video/cx18/cx18-queue.h index f86c8a6fa6e7..91423b9863a4 100644 --- a/drivers/media/video/cx18/cx18-queue.h +++ b/drivers/media/video/cx18/cx18-queue.h @@ -39,8 +39,6 @@ static inline void cx18_buf_sync_for_device(struct cx18_stream *s, s->buf_size, s->dma); } -int cx18_buf_copy_from_user(struct cx18_stream *s, struct cx18_buffer *buf, - const char __user *src, int copybytes); void cx18_buf_swap(struct cx18_buffer *buf); /* cx18_queue utility functions */ @@ -48,8 +46,6 @@ void cx18_queue_init(struct cx18_queue *q); void cx18_enqueue(struct cx18_stream *s, struct cx18_buffer *buf, struct cx18_queue *q); struct cx18_buffer *cx18_dequeue(struct cx18_stream *s, struct cx18_queue *q); -int cx18_queue_move(struct cx18_stream *s, struct cx18_queue *from, - struct cx18_queue *steal, struct cx18_queue *to, int needed_bytes); struct cx18_buffer *cx18_queue_find_buf(struct cx18_stream *s, u32 id, u32 bytesused); void cx18_flush_queues(struct cx18_stream *s); -- cgit v1.2.3 From 4ed83b51d3669628d970c2fea604064d2e0ac6af Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Mon, 28 Apr 2008 15:39:09 -0300 Subject: V4L/DVB (7857): make itd1000_fre_values[] static const itd1000_fre_values[] can become static const. Signed-off-by: Adrian Bunk Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb/frontends/itd1000.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/dvb/frontends/itd1000.c b/drivers/media/dvb/frontends/itd1000.c index 04c562ccf990..600dad6b41ea 100644 --- a/drivers/media/dvb/frontends/itd1000.c +++ b/drivers/media/dvb/frontends/itd1000.c @@ -195,7 +195,7 @@ static void itd1000_set_vco(struct itd1000_state *state, u32 freq_khz) } } -struct { +static const struct { u32 freq; u8 values[10]; /* RFTR, RFST1 - RFST9 */ } itd1000_fre_values[] = { -- cgit v1.2.3 From 91e64c884295c7347f9ea78347d5a5e2df2441f6 Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Mon, 5 May 2008 13:57:50 -0300 Subject: V4L/DVB (7858): video: build fix for drivers/media/video/mt9v022.c x86.git testing found the following build bug on latest -git: CC [M] drivers/media/video/mt9v022.o drivers/media/video/mt9v022.c: In function 'bus_switch_request': drivers/media/video/mt9v022.c:199: error: implicit declaration of function 'gpio_is_valid' drivers/media/video/mt9v022.c:201: error: implicit declaration of function 'gpio_request' drivers/media/video/mt9v022.c:207: error: implicit declaration of function 'gpio_direction_output' drivers/media/video/mt9v022.c:211: error: implicit declaration of function 'gpio_free' drivers/media/video/mt9v022.c: In function 'bus_switch_act': drivers/media/video/mt9v022.c:237: error: implicit declaration of function 'gpio_set_value_cansleep' make[2]: *** [drivers/media/video] Error 2 make[1]: *** [drivers/media] Error 2 make[1]: *** Waiting for unfinished jobs.... make: *** [drivers] Error 2 with this config: http://redhat.com/~mingo/misc/config-Sat_May__3_16_08_39_CEST_2008.bad the bug was that the driver uses GPIO functionality but only includes the GPIO interface definitions for the CONFIG_MT9M001_PCA9536_SWITCH case, which was not set in this config. The quick fix seems to be to include linux/gpio.h unconditionally. (this seems like a small cleanup as well as it removes and #ifdef is more robust than an inclusion of asm/gpio.h) Not tested too much yet, so please have another look in any case. Signed-off-by: Ingo Molnar Signed-off-by: Guennadi Liakhovetski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/mt9m001.c | 5 +---- drivers/media/video/mt9v022.c | 5 +---- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/media/video/mt9m001.c b/drivers/media/video/mt9m001.c index 179e47049a45..ee43499544c1 100644 --- a/drivers/media/video/mt9m001.c +++ b/drivers/media/video/mt9m001.c @@ -12,15 +12,12 @@ #include #include #include +#include #include #include #include -#ifdef CONFIG_MT9M001_PCA9536_SWITCH -#include -#endif - /* mt9m001 i2c address 0x5d * The platform has to define i2c_board_info * and call i2c_register_board_info() */ diff --git a/drivers/media/video/mt9v022.c b/drivers/media/video/mt9v022.c index d1391ac55096..80f7668f3f46 100644 --- a/drivers/media/video/mt9v022.c +++ b/drivers/media/video/mt9v022.c @@ -13,15 +13,12 @@ #include #include #include +#include #include #include #include -#ifdef CONFIG_MT9M001_PCA9536_SWITCH -#include -#endif - /* mt9v022 i2c address 0x48, 0x4c, 0x58, 0x5c * The platform has to define i2c_board_info * and call i2c_register_board_info() */ -- cgit v1.2.3 From 7fb0fd05b2f03065ca4743e8c7446ec86329c4c8 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Mon, 5 May 2008 14:12:30 -0300 Subject: V4L/DVB (7859): mt9v022: fix a copy-paste error in comment Signed-off-by: Guennadi Liakhovetski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/mt9v022.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/video/mt9v022.c b/drivers/media/video/mt9v022.c index 80f7668f3f46..1658fe590392 100644 --- a/drivers/media/video/mt9v022.c +++ b/drivers/media/video/mt9v022.c @@ -88,7 +88,7 @@ static const struct soc_camera_data_format mt9v022_monochrome_formats[] = { struct mt9v022 { struct i2c_client *client; struct soc_camera_device icd; - int model; /* V4L2_IDENT_MT9M001* codes from v4l2-chip-ident.h */ + int model; /* V4L2_IDENT_MT9V022* codes from v4l2-chip-ident.h */ int switch_gpio; u16 chip_control; unsigned char datawidth; -- cgit v1.2.3 From 6d8425b1e38f69e349818299f245d35fb5c3a7d5 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 5 May 2008 18:25:22 -0300 Subject: V4L/DVB (7860a): Add MAINTAINERS for cx18 Signed-off-by: Hans Verkuil Signed-off-by: Andy Walls Signed-off-by: Mauro Carvalho Chehab --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b18242f8d96b..bc1c0088dc49 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1230,6 +1230,15 @@ P: Jaya Kumar M: jayakumar.alsa@gmail.com S: Maintained +CX18 VIDEO4LINUX DRIVER +P: Hans Verkuil, Andy Walls +M: hverkuil@xs4all.nl, awalls@radix.net +L: ivtv-devel@ivtvdriver.org +L: ivtv-users@ivtvdriver.org +L: video4linux-list@redhat.com +W: http://linuxtv.org +S: Maintained + CYBERPRO FB DRIVER P: Russell King M: rmk@arm.linux.org.uk -- cgit v1.2.3 From e4671b6bc0b5b488adc5acbcfcbfa6661abec94e Mon Sep 17 00:00:00 2001 From: Matthias Schwarzott Date: Wed, 30 Apr 2008 12:21:04 -0300 Subject: V4L/DVB (7861): mt312: Prefix functions only with mt312_, Add zl10313 to kconfig description This patch does some small cleanup to mt312. It changes kconfig description to also list the ZL10313. It does change some strange symbol names to be consistent with module name mt312 and naming of all other functions in there. * vp310_mt312_ops -> mt312_ops * vp310_mt312_attach -> mt312_attach Adds a MODULE_AUTHOR for me Signed-off-by: Matthias Schwarzott Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb/b2c2/flexcop-fe-tuner.c | 2 +- drivers/media/dvb/frontends/Kconfig | 2 +- drivers/media/dvb/frontends/mt312.c | 9 +++++---- drivers/media/dvb/frontends/mt312.h | 4 ++-- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/media/dvb/b2c2/flexcop-fe-tuner.c b/drivers/media/dvb/b2c2/flexcop-fe-tuner.c index 7b0ea3bdfafb..f9d087669d5d 100644 --- a/drivers/media/dvb/b2c2/flexcop-fe-tuner.c +++ b/drivers/media/dvb/b2c2/flexcop-fe-tuner.c @@ -634,7 +634,7 @@ int flexcop_frontend_init(struct flexcop_device *fc) } /* try the sky v2.3 (vp310/Samsung tbdu18132(tsa5059)) */ - fc->fe = dvb_attach(vp310_mt312_attach, + fc->fe = dvb_attach(mt312_attach, &skystar23_samsung_tbdu18132_config, i2c); if (fc->fe != NULL) { ops = &fc->fe->ops; diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig index 47d0215084c6..c20553c4da1f 100644 --- a/drivers/media/dvb/frontends/Kconfig +++ b/drivers/media/dvb/frontends/Kconfig @@ -30,7 +30,7 @@ config DVB_CX24123 A DVB-S tuner module. Say Y when you want to support this frontend. config DVB_MT312 - tristate "Zarlink VP310/MT312 based" + tristate "Zarlink VP310/MT312/ZL10313 based" depends on DVB_CORE && I2C default m if DVB_FE_CUSTOMISE help diff --git a/drivers/media/dvb/frontends/mt312.c b/drivers/media/dvb/frontends/mt312.c index 081ca3398c76..5ac9b15920f8 100644 --- a/drivers/media/dvb/frontends/mt312.c +++ b/drivers/media/dvb/frontends/mt312.c @@ -737,7 +737,7 @@ static void mt312_release(struct dvb_frontend *fe) } #define MT312_SYS_CLK 90000000UL /* 90 MHz */ -static struct dvb_frontend_ops vp310_mt312_ops = { +static struct dvb_frontend_ops mt312_ops = { .info = { .name = "Zarlink ???? DVB-S", @@ -776,7 +776,7 @@ static struct dvb_frontend_ops vp310_mt312_ops = { .set_voltage = mt312_set_voltage, }; -struct dvb_frontend *vp310_mt312_attach(const struct mt312_config *config, +struct dvb_frontend *mt312_attach(const struct mt312_config *config, struct i2c_adapter *i2c) { struct mt312_state *state = NULL; @@ -795,7 +795,7 @@ struct dvb_frontend *vp310_mt312_attach(const struct mt312_config *config, goto error; /* create dvb_frontend */ - memcpy(&state->frontend.ops, &vp310_mt312_ops, + memcpy(&state->frontend.ops, &mt312_ops, sizeof(struct dvb_frontend_ops)); state->frontend.demodulator_priv = state; @@ -827,12 +827,13 @@ error: kfree(state); return NULL; } -EXPORT_SYMBOL(vp310_mt312_attach); +EXPORT_SYMBOL(mt312_attach); module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver"); MODULE_AUTHOR("Andreas Oberritter "); +MODULE_AUTHOR("Matthias Schwarzott "); MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb/frontends/mt312.h b/drivers/media/dvb/frontends/mt312.h index de796eab3911..29e3bb5496b8 100644 --- a/drivers/media/dvb/frontends/mt312.h +++ b/drivers/media/dvb/frontends/mt312.h @@ -37,10 +37,10 @@ struct mt312_config { }; #if defined(CONFIG_DVB_MT312) || (defined(CONFIG_DVB_MT312_MODULE) && defined(MODULE)) -struct dvb_frontend *vp310_mt312_attach(const struct mt312_config *config, +struct dvb_frontend *mt312_attach(const struct mt312_config *config, struct i2c_adapter *i2c); #else -static inline struct dvb_frontend *vp310_mt312_attach( +static inline struct dvb_frontend *mt312_attach( const struct mt312_config *config, struct i2c_adapter *i2c) { printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); -- cgit v1.2.3 From 52c99bda04d8bb1fb390821695b0f9efc1e1db44 Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 04:57:01 -0300 Subject: V4L/DVB (7862): Add mxl5505s driver for MaxiLinear 5505 chipsets Initial check-in of the original driver to establish history. Signed-off-by: Chia-Ling Lu Developer Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 4989 ++++++++++++++++++++++++++++++++ drivers/media/common/tuners/mxl5005s.h | 718 +++++ 2 files changed, 5707 insertions(+) create mode 100644 drivers/media/common/tuners/mxl5005s.c create mode 100644 drivers/media/common/tuners/mxl5005s.h diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c new file mode 100644 index 000000000000..a32475fa1472 --- /dev/null +++ b/drivers/media/common/tuners/mxl5005s.c @@ -0,0 +1,4989 @@ +/* + * For the Realtek RTL chip RTL2831U + * Realtek Release Date: 2008-03-14, ver 080314 + * Realtek version RTL2831 Linux driver version 080314 + * ver 080314 + * + * for linux kernel version 2.6.21.4 - 2.6.22-14 + * support MXL5005s and MT2060 tuners (support tuner auto-detecting) + * support two IR types -- RC5 and NEC + * + * Known boards with Realtek RTL chip RTL2821U + * Freecom USB stick 14aa:0160 (version 4) + * Conceptronic CTVDIGRCU + * + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ + + +/** + +@file + +@brief MxL5005S tuner module definition + +One can manipulate MxL5005S tuner through MxL5005S module. +MxL5005S module is derived from tuner module. + +*/ + + +#include "tuner_mxl5005s.h" +#include "tuner_demod_io.h" + + + + + + +/** + +@defgroup MXL5005S_TUNER_MODULE MxL5005S tuner module + +MxL5005S tuner module is drived from tuner base module. + +@see TUNER_BASE_MODULE + +*/ + + + + + +/** + +@defgroup MXL5005S_MODULE_BUILDER MxL5005S module builder +@ingroup MXL5005S_TUNER_MODULE + +One should call MxL5005S module builder before using MxL5005S module. + +*/ +/// @{ + + + + + +/** + +@brief MxL5005S tuner module builder + +Use BuildMxl5005sModule() to build MxL5005S module, set all module function pointers with the corresponding functions, +and initialize module private variables. + + +@param [in] ppTuner Pointer to MxL5005S tuner module pointer +@param [in] pTunerModuleMemory Pointer to an allocated tuner module memory +@param [in] pMxl5005sExtraModuleMemory Pointer to an allocated MxL5005S extra module memory +@param [in] pI2cBridgeModuleMemory Pointer to an allocated I2C bridge module memory +@param [in] DeviceAddr MxL5005S I2C device address +@param [in] CrystalFreqHz MxL5005S crystal frequency in Hz + + +@note \n + -# One should call BuildMxl5005sModule() to build MxL5005S module before using it. + +*/ +void +BuildMxl5005sModule( + TUNER_MODULE **ppTuner, + TUNER_MODULE *pTunerModuleMemory, + MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory, + BASE_INTERFACE_MODULE *pBaseInterfaceModuleMemory, + I2C_BRIDGE_MODULE *pI2cBridgeModuleMemory, + unsigned char DeviceAddr, + int StandardMode + ) +{ + MXL5005S_EXTRA_MODULE *pExtra; + + int MxlModMode; + int MxlIfMode; + unsigned long MxlBandwitdh; + unsigned long MxlIfFreqHz; + unsigned long MxlCrystalFreqHz; + int MxlAgcMode; + unsigned short MxlTop; + unsigned short MxlIfOutputLoad; + int MxlClockOut; + int MxlDivOut; + int MxlCapSel; + int MxlRssiOnOff; + unsigned char MxlStandard; + unsigned char MxlTfType; + + + + // Set tuner module pointer, tuner extra module pointer, and I2C bridge module pointer. + *ppTuner = pTunerModuleMemory; + (*ppTuner)->pExtra = pMxl5005sExtraModuleMemory; + (*ppTuner)->pBaseInterface = pBaseInterfaceModuleMemory; + (*ppTuner)->pI2cBridge = pI2cBridgeModuleMemory; + + // Get tuner extra module pointer. + pExtra = (MXL5005S_EXTRA_MODULE *)(*ppTuner)->pExtra; + + + // Set I2C bridge tuner arguments. + mxl5005s_SetI2cBridgeModuleTunerArg(*ppTuner); + + + // Set tuner module manipulating function pointers. + (*ppTuner)->SetDeviceAddr = mxl5005s_SetDeviceAddr; + + (*ppTuner)->GetTunerType = mxl5005s_GetTunerType; + (*ppTuner)->GetDeviceAddr = mxl5005s_GetDeviceAddr; + + (*ppTuner)->Initialize = mxl5005s_Initialize; + (*ppTuner)->SetRfFreqHz = mxl5005s_SetRfFreqHz; + (*ppTuner)->GetRfFreqHz = mxl5005s_GetRfFreqHz; + + + // Set tuner extra module manipulating function pointers. + pExtra->SetRegsWithTable = mxl5005s_SetRegsWithTable; + pExtra->SetRegMaskBits = mxl5005s_SetRegMaskBits; + pExtra->SetSpectrumMode = mxl5005s_SetSpectrumMode; + pExtra->SetBandwidthHz = mxl5005s_SetBandwidthHz; + + + // Initialize tuner parameter setting status. + (*ppTuner)->IsDeviceAddrSet = NO; + (*ppTuner)->IsRfFreqHzSet = NO; + + + // Set MxL5005S parameters. + MxlModMode = MXL_DIGITAL_MODE; + MxlIfMode = MXL_ZERO_IF; + MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; + MxlIfFreqHz = IF_FREQ_4570000HZ; + MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; + MxlAgcMode = MXL_SINGLE_AGC; + MxlTop = MXL5005S_TOP_25P2; + MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; + MxlClockOut = MXL_CLOCK_OUT_DISABLE; + MxlDivOut = MXL_DIV_OUT_4; + MxlCapSel = MXL_CAP_SEL_ENABLE; + MxlRssiOnOff = MXL_RSSI_ENABLE; + MxlTfType = MXL_TF_C_H; + + + // Set MxL5005S parameters according to standard mode + switch(StandardMode) + { + default: + case MXL5005S_STANDARD_DVBT: MxlStandard = MXL_DVBT; break; + case MXL5005S_STANDARD_ATSC: MxlStandard = MXL_ATSC; break; + } + + + // Set MxL5005S extra module. + pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; + + MXL5005_TunerConfig(&pExtra->MxlDefinedTunerStructure, (unsigned char)MxlModMode, (unsigned char)MxlIfMode, + MxlBandwitdh, MxlIfFreqHz, MxlCrystalFreqHz, (unsigned char)MxlAgcMode, MxlTop, MxlIfOutputLoad, + (unsigned char)MxlClockOut, (unsigned char)MxlDivOut, (unsigned char)MxlCapSel, (unsigned char)MxlRssiOnOff, + MxlStandard, MxlTfType); + + + + // Note: Need to set all module arguments before using module functions. + + + // Set tuner type. + (*ppTuner)->TunerType = TUNER_TYPE_MXL5005S; + + // Set tuner I2C device address. + (*ppTuner)->SetDeviceAddr(*ppTuner, DeviceAddr); + + + return; +} + + + + + +/// @} + + + + + +/** + +@defgroup MXL5005S_MANIPULATING_FUNCTIONS MxL5005S manipulating functions derived from tuner base module +@ingroup MXL5005S_TUNER_MODULE + +One can use the MxL5005S tuner module manipulating interface implemented by MxL5005S manipulating functions to +manipulate MxL5005S tuner. + +*/ +/// @{ + + + + + +/** + +@brief Set MxL5005S tuner I2C device address. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_SET_DEVICE_ADDR() function pointer with mxl5005s_SetDeviceAddr(). + +@see TUNER_FP_SET_DEVICE_ADDR + +*/ +void +mxl5005s_SetDeviceAddr( + TUNER_MODULE *pTuner, + unsigned char DeviceAddr + ) +{ + // Set tuner I2C device address. + pTuner->DeviceAddr = DeviceAddr; + pTuner->IsDeviceAddrSet = YES; + + + return; +} + + + + + +/** + +@brief Get MxL5005S tuner type. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_GET_TUNER_TYPE() function pointer with mxl5005s_GetTunerType(). + +@see TUNER_FP_GET_TUNER_TYPE + +*/ +void +mxl5005s_GetTunerType( + TUNER_MODULE *pTuner, + int *pTunerType + ) +{ + // Get tuner type from tuner module. + *pTunerType = pTuner->TunerType; + + + return; +} + + + + + +/** + +@brief Get MxL5005S tuner I2C device address. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_GET_DEVICE_ADDR() function pointer with mxl5005s_GetDeviceAddr(). + +@see TUNER_FP_GET_DEVICE_ADDR + +*/ +int +mxl5005s_GetDeviceAddr( + TUNER_MODULE *pTuner, + unsigned char *pDeviceAddr + ) +{ + // Get tuner I2C device address from tuner module. + if(pTuner->IsDeviceAddrSet != YES) + goto error_status_get_tuner_i2c_device_addr; + + *pDeviceAddr = pTuner->DeviceAddr; + + + return FUNCTION_SUCCESS; + + +error_status_get_tuner_i2c_device_addr: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Initialize MxL5005S tuner. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_INITIALIZE() function pointer with mxl5005s_Initialize(). + +@see TUNER_FP_INITIALIZE + +*/ +int +mxl5005s_Initialize( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner + ) +{ + MXL5005S_EXTRA_MODULE *pExtra; + + unsigned char AgcMasterByte; + unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + int TableLen; + + + + // Get tuner extra module. + pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; + + + // Get AGC master byte + AgcMasterByte = pExtra->AgcMasterByte; + + + // Initialize MxL5005S tuner according to MxL5005S tuner example code. + + // Tuner initialization stage 0 + MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); + AddrTable[0] = MASTER_CONTROL_ADDR; + ByteTable[0] |= AgcMasterByte; + + if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + // Tuner initialization stage 1 + MXL_GetInitRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen); + + if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Set MxL5005S tuner RF frequency in Hz. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_SET_RF_FREQ_HZ() function pointer with mxl5005s_SetRfFreqHz(). + +@see TUNER_FP_SET_RF_FREQ_HZ + +*/ +int +mxl5005s_SetRfFreqHz( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long RfFreqHz + ) +{ + MXL5005S_EXTRA_MODULE *pExtra; + BASE_INTERFACE_MODULE *pBaseInterface; + + unsigned char AgcMasterByte; + unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + int TableLen; + + unsigned long IfDivval; + unsigned char MasterControlByte; + + + + // Get tuner extra module and base interface module. + pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; + pBaseInterface = pTuner->pBaseInterface; + + + // Get AGC master byte + AgcMasterByte = pExtra->AgcMasterByte; + + + // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code. + + // Tuner RF frequency setting stage 0 + MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ; + AddrTable[0] = MASTER_CONTROL_ADDR; + ByteTable[0] |= AgcMasterByte; + + if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + // Tuner RF frequency setting stage 1 + MXL_TuneRF(&pExtra->MxlDefinedTunerStructure, RfFreqHz); + + MXL_ControlRead(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, &IfDivval); + + MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 0); + MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_EXTPOWERUP, 1); + MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, 8); + + MXL_GetCHRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ; + + MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; + AddrTable[TableLen] = MASTER_CONTROL_ADDR ; + ByteTable[TableLen] = MasterControlByte | AgcMasterByte; + TableLen += 1; + + if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + // Wait 30 ms. + pBaseInterface->WaitMs(pBaseInterface, 30); + + + // Tuner RF frequency setting stage 2 + MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 1) ; + MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, IfDivval) ; + MXL_GetCHRegister_ZeroIF(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ; + + MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; + AddrTable[TableLen] = MASTER_CONTROL_ADDR ; + ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; + TableLen += 1; + + if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + // Set tuner RF frequency parameter. + pTuner->RfFreqHz = RfFreqHz; + pTuner->IsRfFreqHzSet = YES; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Get MxL5005S tuner RF frequency in Hz. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_GET_RF_FREQ_HZ() function pointer with mxl5005s_GetRfFreqHz(). + +@see TUNER_FP_GET_RF_FREQ_HZ + +*/ +int +mxl5005s_GetRfFreqHz( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long *pRfFreqHz + ) +{ + // Get tuner RF frequency in Hz from tuner module. + if(pTuner->IsRfFreqHzSet != YES) + goto error_status_get_tuner_rf_frequency; + + *pRfFreqHz = pTuner->RfFreqHz; + + + return FUNCTION_SUCCESS; + + +error_status_get_tuner_rf_frequency: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Set MxL5005S tuner registers with table. + +*/ +/* +int +mxl5005s_SetRegsWithTable( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char *pAddrTable, + unsigned char *pByteTable, + int TableLen + ) +{ + BASE_INTERFACE_MODULE *pBaseInterface; + I2C_BRIDGE_MODULE *pI2cBridge; + unsigned char WritingByteNumMax; + + int i; + unsigned char WritingBuffer[I2C_BUFFER_LEN]; + unsigned char WritingIndex; + + + + // Get base interface, I2C bridge, and maximum writing byte number. + pBaseInterface = pTuner->pBaseInterface; + pI2cBridge = pTuner->pI2cBridge; + WritingByteNumMax = pBaseInterface->I2cWritingByteNumMax; + + + // Set registers with table. + // Note: 1. The I2C format of MxL5005S is described as follows: + // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * n + stop_bit + // ... + // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * m + latch_byte + stop_bit + // 2. The latch_byte is 0xfe. + // 3. The following writing byte separating scheme takes latch_byte as two byte data. + for(i = 0, WritingIndex = 0; i < TableLen; i++) + { + // Put register address and register byte value into writing buffer. + WritingBuffer[WritingIndex] = pAddrTable[i]; + WritingBuffer[WritingIndex + 1] = pByteTable[i]; + WritingIndex += 2; + + // If writing buffer is full, send the I2C writing command with writing buffer. + if(WritingIndex > (WritingByteNumMax - 2)) + { + if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + WritingIndex = 0; + } + } + + + // Send the last I2C writing command with writing buffer and latch byte. + WritingBuffer[WritingIndex] = MXL5005S_LATCH_BYTE; + WritingIndex += 1; + + if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} +*/ + + +int +mxl5005s_SetRegsWithTable( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char *pAddrTable, + unsigned char *pByteTable, + int TableLen + ) +{ + int i; + u8 end_two_bytes_buf[]={ 0 , 0 }; + u8 tuner_addr=0x00; + + pTuner->GetDeviceAddr(pTuner , &tuner_addr); + + for( i = 0 ; i < TableLen - 1 ; i++) + { + if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , &pByteTable[i] , 1 ) ) + return FUNCTION_ERROR; + } + + end_two_bytes_buf[0] = pByteTable[i]; + end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; + + if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , end_two_bytes_buf , 2 ) ) + return FUNCTION_ERROR; + + return FUNCTION_SUCCESS; +} + + + + + +/** + +@brief Set MxL5005S tuner register bits. + +*/ +int +mxl5005s_SetRegMaskBits( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char RegAddr, + unsigned char Msb, + unsigned char Lsb, + const unsigned char WritingValue + ) +{ + MXL5005S_EXTRA_MODULE *pExtra; + + int i; + + unsigned char Mask; + unsigned char Shift; + + unsigned char RegByte; + + + + // Get tuner extra module. + pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; + + + // Generate mask and shift according to MSB and LSB. + Mask = 0; + for(i = Lsb; i < (unsigned char)(Msb + 1); i++) + Mask |= 0x1 << i; + + Shift = Lsb; + + + // Get tuner register byte according to register adddress. + MXL_RegRead(&pExtra->MxlDefinedTunerStructure, RegAddr, &RegByte); + + + // Reserve register byte unmask bit with mask and inlay writing value into it. + RegByte &= ~Mask; + RegByte |= (WritingValue << Shift) & Mask; + + + // Update tuner register byte table. + MXL_RegWrite(&pExtra->MxlDefinedTunerStructure, RegAddr, RegByte); + + + // Write tuner register byte with writing byte. + if(pExtra->SetRegsWithTable( dib, pTuner, &RegAddr, &RegByte, LEN_1_BYTE) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Set MxL5005S tuner spectrum mode. + +*/ +int +mxl5005s_SetSpectrumMode( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + int SpectrumMode + ) +{ + static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] = + { + // BB_IQSWAP + 0, // Normal spectrum + 1, // Inverse spectrum + }; + + + MXL5005S_EXTRA_MODULE *pExtra; + + + + // Get tuner extra module. + pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; + + + // Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. + if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_IQSWAP_ADDR, MXL5005S_BB_IQSWAP_MSB, + MXL5005S_BB_IQSWAP_LSB, BbIqswapTable[SpectrumMode]) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Set MxL5005S tuner bandwidth in Hz. + +*/ +int +mxl5005s_SetBandwidthHz( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long BandwidthHz + ) +{ + MXL5005S_EXTRA_MODULE *pExtra; + + unsigned char BbDlpfBandsel; + + + + // Get tuner extra module. + pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; + + + // Set BB_DLPF_BANDSEL according to bandwidth. + switch(BandwidthHz) + { + default: + case MXL5005S_BANDWIDTH_6MHZ: BbDlpfBandsel = 3; break; + case MXL5005S_BANDWIDTH_7MHZ: BbDlpfBandsel = 2; break; + case MXL5005S_BANDWIDTH_8MHZ: BbDlpfBandsel = 0; break; + } + + if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB, + MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} + + + + + +/// @} + + + + + +/** + +@defgroup MXL5005S_DEPENDENCE MxL5005S dependence +@ingroup MXL5005S_TUNER_MODULE + +MxL5005S dependence is the related functions for MxL5005S tuner module interface. +One should not use MxL5005S dependence directly. + +*/ +/// @{ + + + + + +/** + +@brief Set I2C bridge module tuner arguments. + +MxL5005S builder will use mxl5005s_SetI2cBridgeModuleTunerArg() to set I2C bridge module tuner arguments. + + +@param [in] pTuner The tuner module pointer + + +@see BuildMxl5005sModule() + +*/ +void +mxl5005s_SetI2cBridgeModuleTunerArg( + TUNER_MODULE *pTuner + ) +{ + I2C_BRIDGE_MODULE *pI2cBridge; + + + + // Get I2C bridge module. + pI2cBridge = pTuner->pI2cBridge; + + // Set I2C bridge module tuner arguments. + pI2cBridge->pTunerDeviceAddr = &pTuner->DeviceAddr; + + + return; +} + + + + + +/// @} + + + + + + + + + + + + + + + + + + + + + + + +// The following context is source code provided by MaxLinear. + + + + + +// MaxLinear source code - MXL5005_Initialize.cpp + + + +//#ifdef _MXL_HEADER +//#include "stdafx.h" +//#endif +//#include "MXL5005_c.h" + +_u16 MXL5005_RegisterInit (Tuner_struct * Tuner) +{ + Tuner->TunerRegs_Num = TUNER_REGS_NUM ; +// Tuner->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; + + Tuner->TunerRegs[0].Reg_Num = 9 ; + Tuner->TunerRegs[0].Reg_Val = 0x40 ; + + Tuner->TunerRegs[1].Reg_Num = 11 ; + Tuner->TunerRegs[1].Reg_Val = 0x19 ; + + Tuner->TunerRegs[2].Reg_Num = 12 ; + Tuner->TunerRegs[2].Reg_Val = 0x60 ; + + Tuner->TunerRegs[3].Reg_Num = 13 ; + Tuner->TunerRegs[3].Reg_Val = 0x00 ; + + Tuner->TunerRegs[4].Reg_Num = 14 ; + Tuner->TunerRegs[4].Reg_Val = 0x00 ; + + Tuner->TunerRegs[5].Reg_Num = 15 ; + Tuner->TunerRegs[5].Reg_Val = 0xC0 ; + + Tuner->TunerRegs[6].Reg_Num = 16 ; + Tuner->TunerRegs[6].Reg_Val = 0x00 ; + + Tuner->TunerRegs[7].Reg_Num = 17 ; + Tuner->TunerRegs[7].Reg_Val = 0x00 ; + + Tuner->TunerRegs[8].Reg_Num = 18 ; + Tuner->TunerRegs[8].Reg_Val = 0x00 ; + + Tuner->TunerRegs[9].Reg_Num = 19 ; + Tuner->TunerRegs[9].Reg_Val = 0x34 ; + + Tuner->TunerRegs[10].Reg_Num = 21 ; + Tuner->TunerRegs[10].Reg_Val = 0x00 ; + + Tuner->TunerRegs[11].Reg_Num = 22 ; + Tuner->TunerRegs[11].Reg_Val = 0x6B ; + + Tuner->TunerRegs[12].Reg_Num = 23 ; + Tuner->TunerRegs[12].Reg_Val = 0x35 ; + + Tuner->TunerRegs[13].Reg_Num = 24 ; + Tuner->TunerRegs[13].Reg_Val = 0x70 ; + + Tuner->TunerRegs[14].Reg_Num = 25 ; + Tuner->TunerRegs[14].Reg_Val = 0x3E ; + + Tuner->TunerRegs[15].Reg_Num = 26 ; + Tuner->TunerRegs[15].Reg_Val = 0x82 ; + + Tuner->TunerRegs[16].Reg_Num = 31 ; + Tuner->TunerRegs[16].Reg_Val = 0x00 ; + + Tuner->TunerRegs[17].Reg_Num = 32 ; + Tuner->TunerRegs[17].Reg_Val = 0x40 ; + + Tuner->TunerRegs[18].Reg_Num = 33 ; + Tuner->TunerRegs[18].Reg_Val = 0x53 ; + + Tuner->TunerRegs[19].Reg_Num = 34 ; + Tuner->TunerRegs[19].Reg_Val = 0x81 ; + + Tuner->TunerRegs[20].Reg_Num = 35 ; + Tuner->TunerRegs[20].Reg_Val = 0xC9 ; + + Tuner->TunerRegs[21].Reg_Num = 36 ; + Tuner->TunerRegs[21].Reg_Val = 0x01 ; + + Tuner->TunerRegs[22].Reg_Num = 37 ; + Tuner->TunerRegs[22].Reg_Val = 0x00 ; + + Tuner->TunerRegs[23].Reg_Num = 41 ; + Tuner->TunerRegs[23].Reg_Val = 0x00 ; + + Tuner->TunerRegs[24].Reg_Num = 42 ; + Tuner->TunerRegs[24].Reg_Val = 0xF8 ; + + Tuner->TunerRegs[25].Reg_Num = 43 ; + Tuner->TunerRegs[25].Reg_Val = 0x43 ; + + Tuner->TunerRegs[26].Reg_Num = 44 ; + Tuner->TunerRegs[26].Reg_Val = 0x20 ; + + Tuner->TunerRegs[27].Reg_Num = 45 ; + Tuner->TunerRegs[27].Reg_Val = 0x80 ; + + Tuner->TunerRegs[28].Reg_Num = 46 ; + Tuner->TunerRegs[28].Reg_Val = 0x88 ; + + Tuner->TunerRegs[29].Reg_Num = 47 ; + Tuner->TunerRegs[29].Reg_Val = 0x86 ; + + Tuner->TunerRegs[30].Reg_Num = 48 ; + Tuner->TunerRegs[30].Reg_Val = 0x00 ; + + Tuner->TunerRegs[31].Reg_Num = 49 ; + Tuner->TunerRegs[31].Reg_Val = 0x00 ; + + Tuner->TunerRegs[32].Reg_Num = 53 ; + Tuner->TunerRegs[32].Reg_Val = 0x94 ; + + Tuner->TunerRegs[33].Reg_Num = 54 ; + Tuner->TunerRegs[33].Reg_Val = 0xFA ; + + Tuner->TunerRegs[34].Reg_Num = 55 ; + Tuner->TunerRegs[34].Reg_Val = 0x92 ; + + Tuner->TunerRegs[35].Reg_Num = 56 ; + Tuner->TunerRegs[35].Reg_Val = 0x80 ; + + Tuner->TunerRegs[36].Reg_Num = 57 ; + Tuner->TunerRegs[36].Reg_Val = 0x41 ; + + Tuner->TunerRegs[37].Reg_Num = 58 ; + Tuner->TunerRegs[37].Reg_Val = 0xDB ; + + Tuner->TunerRegs[38].Reg_Num = 59 ; + Tuner->TunerRegs[38].Reg_Val = 0x00 ; + + Tuner->TunerRegs[39].Reg_Num = 60 ; + Tuner->TunerRegs[39].Reg_Val = 0x00 ; + + Tuner->TunerRegs[40].Reg_Num = 61 ; + Tuner->TunerRegs[40].Reg_Val = 0x00 ; + + Tuner->TunerRegs[41].Reg_Num = 62 ; + Tuner->TunerRegs[41].Reg_Val = 0x00 ; + + Tuner->TunerRegs[42].Reg_Num = 65 ; + Tuner->TunerRegs[42].Reg_Val = 0xF8 ; + + Tuner->TunerRegs[43].Reg_Num = 66 ; + Tuner->TunerRegs[43].Reg_Val = 0xE4 ; + + Tuner->TunerRegs[44].Reg_Num = 67 ; + Tuner->TunerRegs[44].Reg_Val = 0x90 ; + + Tuner->TunerRegs[45].Reg_Num = 68 ; + Tuner->TunerRegs[45].Reg_Val = 0xC0 ; + + Tuner->TunerRegs[46].Reg_Num = 69 ; + Tuner->TunerRegs[46].Reg_Val = 0x01 ; + + Tuner->TunerRegs[47].Reg_Num = 70 ; + Tuner->TunerRegs[47].Reg_Val = 0x50 ; + + Tuner->TunerRegs[48].Reg_Num = 71 ; + Tuner->TunerRegs[48].Reg_Val = 0x06 ; + + Tuner->TunerRegs[49].Reg_Num = 72 ; + Tuner->TunerRegs[49].Reg_Val = 0x00 ; + + Tuner->TunerRegs[50].Reg_Num = 73 ; + Tuner->TunerRegs[50].Reg_Val = 0x20 ; + + Tuner->TunerRegs[51].Reg_Num = 76 ; + Tuner->TunerRegs[51].Reg_Val = 0xBB ; + + Tuner->TunerRegs[52].Reg_Num = 77 ; + Tuner->TunerRegs[52].Reg_Val = 0x13 ; + + Tuner->TunerRegs[53].Reg_Num = 81 ; + Tuner->TunerRegs[53].Reg_Val = 0x04 ; + + Tuner->TunerRegs[54].Reg_Num = 82 ; + Tuner->TunerRegs[54].Reg_Val = 0x75 ; + + Tuner->TunerRegs[55].Reg_Num = 83 ; + Tuner->TunerRegs[55].Reg_Val = 0x00 ; + + Tuner->TunerRegs[56].Reg_Num = 84 ; + Tuner->TunerRegs[56].Reg_Val = 0x00 ; + + Tuner->TunerRegs[57].Reg_Num = 85 ; + Tuner->TunerRegs[57].Reg_Val = 0x00 ; + + Tuner->TunerRegs[58].Reg_Num = 91 ; + Tuner->TunerRegs[58].Reg_Val = 0x70 ; + + Tuner->TunerRegs[59].Reg_Num = 92 ; + Tuner->TunerRegs[59].Reg_Val = 0x00 ; + + Tuner->TunerRegs[60].Reg_Num = 93 ; + Tuner->TunerRegs[60].Reg_Val = 0x00 ; + + Tuner->TunerRegs[61].Reg_Num = 94 ; + Tuner->TunerRegs[61].Reg_Val = 0x00 ; + + Tuner->TunerRegs[62].Reg_Num = 95 ; + Tuner->TunerRegs[62].Reg_Val = 0x0C ; + + Tuner->TunerRegs[63].Reg_Num = 96 ; + Tuner->TunerRegs[63].Reg_Val = 0x00 ; + + Tuner->TunerRegs[64].Reg_Num = 97 ; + Tuner->TunerRegs[64].Reg_Val = 0x00 ; + + Tuner->TunerRegs[65].Reg_Num = 98 ; + Tuner->TunerRegs[65].Reg_Val = 0xE2 ; + + Tuner->TunerRegs[66].Reg_Num = 99 ; + Tuner->TunerRegs[66].Reg_Val = 0x00 ; + + Tuner->TunerRegs[67].Reg_Num = 100 ; + Tuner->TunerRegs[67].Reg_Val = 0x00 ; + + Tuner->TunerRegs[68].Reg_Num = 101 ; + Tuner->TunerRegs[68].Reg_Val = 0x12 ; + + Tuner->TunerRegs[69].Reg_Num = 102 ; + Tuner->TunerRegs[69].Reg_Val = 0x80 ; + + Tuner->TunerRegs[70].Reg_Num = 103 ; + Tuner->TunerRegs[70].Reg_Val = 0x32 ; + + Tuner->TunerRegs[71].Reg_Num = 104 ; + Tuner->TunerRegs[71].Reg_Val = 0xB4 ; + + Tuner->TunerRegs[72].Reg_Num = 105 ; + Tuner->TunerRegs[72].Reg_Val = 0x60 ; + + Tuner->TunerRegs[73].Reg_Num = 106 ; + Tuner->TunerRegs[73].Reg_Val = 0x83 ; + + Tuner->TunerRegs[74].Reg_Num = 107 ; + Tuner->TunerRegs[74].Reg_Val = 0x84 ; + + Tuner->TunerRegs[75].Reg_Num = 108 ; + Tuner->TunerRegs[75].Reg_Val = 0x9C ; + + Tuner->TunerRegs[76].Reg_Num = 109 ; + Tuner->TunerRegs[76].Reg_Val = 0x02 ; + + Tuner->TunerRegs[77].Reg_Num = 110 ; + Tuner->TunerRegs[77].Reg_Val = 0x81 ; + + Tuner->TunerRegs[78].Reg_Num = 111 ; + Tuner->TunerRegs[78].Reg_Val = 0xC0 ; + + Tuner->TunerRegs[79].Reg_Num = 112 ; + Tuner->TunerRegs[79].Reg_Val = 0x10 ; + + Tuner->TunerRegs[80].Reg_Num = 131 ; + Tuner->TunerRegs[80].Reg_Val = 0x8A ; + + Tuner->TunerRegs[81].Reg_Num = 132 ; + Tuner->TunerRegs[81].Reg_Val = 0x10 ; + + Tuner->TunerRegs[82].Reg_Num = 133 ; + Tuner->TunerRegs[82].Reg_Val = 0x24 ; + + Tuner->TunerRegs[83].Reg_Num = 134 ; + Tuner->TunerRegs[83].Reg_Val = 0x00 ; + + Tuner->TunerRegs[84].Reg_Num = 135 ; + Tuner->TunerRegs[84].Reg_Val = 0x00 ; + + Tuner->TunerRegs[85].Reg_Num = 136 ; + Tuner->TunerRegs[85].Reg_Val = 0x7E ; + + Tuner->TunerRegs[86].Reg_Num = 137 ; + Tuner->TunerRegs[86].Reg_Val = 0x40 ; + + Tuner->TunerRegs[87].Reg_Num = 138 ; + Tuner->TunerRegs[87].Reg_Val = 0x38 ; + + Tuner->TunerRegs[88].Reg_Num = 146 ; + Tuner->TunerRegs[88].Reg_Val = 0xF6 ; + + Tuner->TunerRegs[89].Reg_Num = 147 ; + Tuner->TunerRegs[89].Reg_Val = 0x1A ; + + Tuner->TunerRegs[90].Reg_Num = 148 ; + Tuner->TunerRegs[90].Reg_Val = 0x62 ; + + Tuner->TunerRegs[91].Reg_Num = 149 ; + Tuner->TunerRegs[91].Reg_Val = 0x33 ; + + Tuner->TunerRegs[92].Reg_Num = 150 ; + Tuner->TunerRegs[92].Reg_Val = 0x80 ; + + Tuner->TunerRegs[93].Reg_Num = 156 ; + Tuner->TunerRegs[93].Reg_Val = 0x56 ; + + Tuner->TunerRegs[94].Reg_Num = 157 ; + Tuner->TunerRegs[94].Reg_Val = 0x17 ; + + Tuner->TunerRegs[95].Reg_Num = 158 ; + Tuner->TunerRegs[95].Reg_Val = 0xA9 ; + + Tuner->TunerRegs[96].Reg_Num = 159 ; + Tuner->TunerRegs[96].Reg_Val = 0x00 ; + + Tuner->TunerRegs[97].Reg_Num = 160 ; + Tuner->TunerRegs[97].Reg_Val = 0x00 ; + + Tuner->TunerRegs[98].Reg_Num = 161 ; + Tuner->TunerRegs[98].Reg_Val = 0x00 ; + + Tuner->TunerRegs[99].Reg_Num = 162 ; + Tuner->TunerRegs[99].Reg_Val = 0x40 ; + + Tuner->TunerRegs[100].Reg_Num = 166 ; + Tuner->TunerRegs[100].Reg_Val = 0xAE ; + + Tuner->TunerRegs[101].Reg_Num = 167 ; + Tuner->TunerRegs[101].Reg_Val = 0x1B ; + + Tuner->TunerRegs[102].Reg_Num = 168 ; + Tuner->TunerRegs[102].Reg_Val = 0xF2 ; + + Tuner->TunerRegs[103].Reg_Num = 195 ; + Tuner->TunerRegs[103].Reg_Val = 0x00 ; + + return 0 ; +} + +_u16 MXL5005_ControlInit (Tuner_struct *Tuner) +{ + Tuner->Init_Ctrl_Num = INITCTRL_NUM ; + + Tuner->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; + Tuner->Init_Ctrl[0].size = 1 ; + Tuner->Init_Ctrl[0].addr[0] = 73; + Tuner->Init_Ctrl[0].bit[0] = 7; + Tuner->Init_Ctrl[0].val[0] = 0; + + Tuner->Init_Ctrl[1].Ctrl_Num = BB_MODE ; + Tuner->Init_Ctrl[1].size = 1 ; + Tuner->Init_Ctrl[1].addr[0] = 53; + Tuner->Init_Ctrl[1].bit[0] = 2; + Tuner->Init_Ctrl[1].val[0] = 1; + + Tuner->Init_Ctrl[2].Ctrl_Num = BB_BUF ; + Tuner->Init_Ctrl[2].size = 2 ; + Tuner->Init_Ctrl[2].addr[0] = 53; + Tuner->Init_Ctrl[2].bit[0] = 1; + Tuner->Init_Ctrl[2].val[0] = 0; + Tuner->Init_Ctrl[2].addr[1] = 57; + Tuner->Init_Ctrl[2].bit[1] = 0; + Tuner->Init_Ctrl[2].val[1] = 1; + + Tuner->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ; + Tuner->Init_Ctrl[3].size = 1 ; + Tuner->Init_Ctrl[3].addr[0] = 53; + Tuner->Init_Ctrl[3].bit[0] = 0; + Tuner->Init_Ctrl[3].val[0] = 0; + + Tuner->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ; + Tuner->Init_Ctrl[4].size = 3 ; + Tuner->Init_Ctrl[4].addr[0] = 53; + Tuner->Init_Ctrl[4].bit[0] = 5; + Tuner->Init_Ctrl[4].val[0] = 0; + Tuner->Init_Ctrl[4].addr[1] = 53; + Tuner->Init_Ctrl[4].bit[1] = 6; + Tuner->Init_Ctrl[4].val[1] = 0; + Tuner->Init_Ctrl[4].addr[2] = 53; + Tuner->Init_Ctrl[4].bit[2] = 7; + Tuner->Init_Ctrl[4].val[2] = 1; + + Tuner->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ; + Tuner->Init_Ctrl[5].size = 1 ; + Tuner->Init_Ctrl[5].addr[0] = 59; + Tuner->Init_Ctrl[5].bit[0] = 0; + Tuner->Init_Ctrl[5].val[0] = 0; + + Tuner->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ; + Tuner->Init_Ctrl[6].size = 2 ; + Tuner->Init_Ctrl[6].addr[0] = 53; + Tuner->Init_Ctrl[6].bit[0] = 3; + Tuner->Init_Ctrl[6].val[0] = 0; + Tuner->Init_Ctrl[6].addr[1] = 53; + Tuner->Init_Ctrl[6].bit[1] = 4; + Tuner->Init_Ctrl[6].val[1] = 1; + + Tuner->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ; + Tuner->Init_Ctrl[7].size = 4 ; + Tuner->Init_Ctrl[7].addr[0] = 22; + Tuner->Init_Ctrl[7].bit[0] = 4; + Tuner->Init_Ctrl[7].val[0] = 0; + Tuner->Init_Ctrl[7].addr[1] = 22; + Tuner->Init_Ctrl[7].bit[1] = 5; + Tuner->Init_Ctrl[7].val[1] = 1; + Tuner->Init_Ctrl[7].addr[2] = 22; + Tuner->Init_Ctrl[7].bit[2] = 6; + Tuner->Init_Ctrl[7].val[2] = 1; + Tuner->Init_Ctrl[7].addr[3] = 22; + Tuner->Init_Ctrl[7].bit[3] = 7; + Tuner->Init_Ctrl[7].val[3] = 0; + + Tuner->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ; + Tuner->Init_Ctrl[8].size = 1 ; + Tuner->Init_Ctrl[8].addr[0] = 22; + Tuner->Init_Ctrl[8].bit[0] = 2; + Tuner->Init_Ctrl[8].val[0] = 0; + + Tuner->Init_Ctrl[9].Ctrl_Num = AGC_IF ; + Tuner->Init_Ctrl[9].size = 4 ; + Tuner->Init_Ctrl[9].addr[0] = 76; + Tuner->Init_Ctrl[9].bit[0] = 0; + Tuner->Init_Ctrl[9].val[0] = 1; + Tuner->Init_Ctrl[9].addr[1] = 76; + Tuner->Init_Ctrl[9].bit[1] = 1; + Tuner->Init_Ctrl[9].val[1] = 1; + Tuner->Init_Ctrl[9].addr[2] = 76; + Tuner->Init_Ctrl[9].bit[2] = 2; + Tuner->Init_Ctrl[9].val[2] = 0; + Tuner->Init_Ctrl[9].addr[3] = 76; + Tuner->Init_Ctrl[9].bit[3] = 3; + Tuner->Init_Ctrl[9].val[3] = 1; + + Tuner->Init_Ctrl[10].Ctrl_Num = AGC_RF ; + Tuner->Init_Ctrl[10].size = 4 ; + Tuner->Init_Ctrl[10].addr[0] = 76; + Tuner->Init_Ctrl[10].bit[0] = 4; + Tuner->Init_Ctrl[10].val[0] = 1; + Tuner->Init_Ctrl[10].addr[1] = 76; + Tuner->Init_Ctrl[10].bit[1] = 5; + Tuner->Init_Ctrl[10].val[1] = 1; + Tuner->Init_Ctrl[10].addr[2] = 76; + Tuner->Init_Ctrl[10].bit[2] = 6; + Tuner->Init_Ctrl[10].val[2] = 0; + Tuner->Init_Ctrl[10].addr[3] = 76; + Tuner->Init_Ctrl[10].bit[3] = 7; + Tuner->Init_Ctrl[10].val[3] = 1; + + Tuner->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ; + Tuner->Init_Ctrl[11].size = 5 ; + Tuner->Init_Ctrl[11].addr[0] = 43; + Tuner->Init_Ctrl[11].bit[0] = 3; + Tuner->Init_Ctrl[11].val[0] = 0; + Tuner->Init_Ctrl[11].addr[1] = 43; + Tuner->Init_Ctrl[11].bit[1] = 4; + Tuner->Init_Ctrl[11].val[1] = 0; + Tuner->Init_Ctrl[11].addr[2] = 43; + Tuner->Init_Ctrl[11].bit[2] = 5; + Tuner->Init_Ctrl[11].val[2] = 0; + Tuner->Init_Ctrl[11].addr[3] = 43; + Tuner->Init_Ctrl[11].bit[3] = 6; + Tuner->Init_Ctrl[11].val[3] = 1; + Tuner->Init_Ctrl[11].addr[4] = 43; + Tuner->Init_Ctrl[11].bit[4] = 7; + Tuner->Init_Ctrl[11].val[4] = 0; + + Tuner->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ; + Tuner->Init_Ctrl[12].size = 6 ; + Tuner->Init_Ctrl[12].addr[0] = 44; + Tuner->Init_Ctrl[12].bit[0] = 2; + Tuner->Init_Ctrl[12].val[0] = 0; + Tuner->Init_Ctrl[12].addr[1] = 44; + Tuner->Init_Ctrl[12].bit[1] = 3; + Tuner->Init_Ctrl[12].val[1] = 0; + Tuner->Init_Ctrl[12].addr[2] = 44; + Tuner->Init_Ctrl[12].bit[2] = 4; + Tuner->Init_Ctrl[12].val[2] = 0; + Tuner->Init_Ctrl[12].addr[3] = 44; + Tuner->Init_Ctrl[12].bit[3] = 5; + Tuner->Init_Ctrl[12].val[3] = 1; + Tuner->Init_Ctrl[12].addr[4] = 44; + Tuner->Init_Ctrl[12].bit[4] = 6; + Tuner->Init_Ctrl[12].val[4] = 0; + Tuner->Init_Ctrl[12].addr[5] = 44; + Tuner->Init_Ctrl[12].bit[5] = 7; + Tuner->Init_Ctrl[12].val[5] = 0; + + Tuner->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ; + Tuner->Init_Ctrl[13].size = 7 ; + Tuner->Init_Ctrl[13].addr[0] = 11; + Tuner->Init_Ctrl[13].bit[0] = 0; + Tuner->Init_Ctrl[13].val[0] = 1; + Tuner->Init_Ctrl[13].addr[1] = 11; + Tuner->Init_Ctrl[13].bit[1] = 1; + Tuner->Init_Ctrl[13].val[1] = 0; + Tuner->Init_Ctrl[13].addr[2] = 11; + Tuner->Init_Ctrl[13].bit[2] = 2; + Tuner->Init_Ctrl[13].val[2] = 0; + Tuner->Init_Ctrl[13].addr[3] = 11; + Tuner->Init_Ctrl[13].bit[3] = 3; + Tuner->Init_Ctrl[13].val[3] = 1; + Tuner->Init_Ctrl[13].addr[4] = 11; + Tuner->Init_Ctrl[13].bit[4] = 4; + Tuner->Init_Ctrl[13].val[4] = 1; + Tuner->Init_Ctrl[13].addr[5] = 11; + Tuner->Init_Ctrl[13].bit[5] = 5; + Tuner->Init_Ctrl[13].val[5] = 0; + Tuner->Init_Ctrl[13].addr[6] = 11; + Tuner->Init_Ctrl[13].bit[6] = 6; + Tuner->Init_Ctrl[13].val[6] = 0; + + Tuner->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ; + Tuner->Init_Ctrl[14].size = 16 ; + Tuner->Init_Ctrl[14].addr[0] = 13; + Tuner->Init_Ctrl[14].bit[0] = 0; + Tuner->Init_Ctrl[14].val[0] = 0; + Tuner->Init_Ctrl[14].addr[1] = 13; + Tuner->Init_Ctrl[14].bit[1] = 1; + Tuner->Init_Ctrl[14].val[1] = 0; + Tuner->Init_Ctrl[14].addr[2] = 13; + Tuner->Init_Ctrl[14].bit[2] = 2; + Tuner->Init_Ctrl[14].val[2] = 0; + Tuner->Init_Ctrl[14].addr[3] = 13; + Tuner->Init_Ctrl[14].bit[3] = 3; + Tuner->Init_Ctrl[14].val[3] = 0; + Tuner->Init_Ctrl[14].addr[4] = 13; + Tuner->Init_Ctrl[14].bit[4] = 4; + Tuner->Init_Ctrl[14].val[4] = 0; + Tuner->Init_Ctrl[14].addr[5] = 13; + Tuner->Init_Ctrl[14].bit[5] = 5; + Tuner->Init_Ctrl[14].val[5] = 0; + Tuner->Init_Ctrl[14].addr[6] = 13; + Tuner->Init_Ctrl[14].bit[6] = 6; + Tuner->Init_Ctrl[14].val[6] = 0; + Tuner->Init_Ctrl[14].addr[7] = 13; + Tuner->Init_Ctrl[14].bit[7] = 7; + Tuner->Init_Ctrl[14].val[7] = 0; + Tuner->Init_Ctrl[14].addr[8] = 12; + Tuner->Init_Ctrl[14].bit[8] = 0; + Tuner->Init_Ctrl[14].val[8] = 0; + Tuner->Init_Ctrl[14].addr[9] = 12; + Tuner->Init_Ctrl[14].bit[9] = 1; + Tuner->Init_Ctrl[14].val[9] = 0; + Tuner->Init_Ctrl[14].addr[10] = 12; + Tuner->Init_Ctrl[14].bit[10] = 2; + Tuner->Init_Ctrl[14].val[10] = 0; + Tuner->Init_Ctrl[14].addr[11] = 12; + Tuner->Init_Ctrl[14].bit[11] = 3; + Tuner->Init_Ctrl[14].val[11] = 0; + Tuner->Init_Ctrl[14].addr[12] = 12; + Tuner->Init_Ctrl[14].bit[12] = 4; + Tuner->Init_Ctrl[14].val[12] = 0; + Tuner->Init_Ctrl[14].addr[13] = 12; + Tuner->Init_Ctrl[14].bit[13] = 5; + Tuner->Init_Ctrl[14].val[13] = 1; + Tuner->Init_Ctrl[14].addr[14] = 12; + Tuner->Init_Ctrl[14].bit[14] = 6; + Tuner->Init_Ctrl[14].val[14] = 1; + Tuner->Init_Ctrl[14].addr[15] = 12; + Tuner->Init_Ctrl[14].bit[15] = 7; + Tuner->Init_Ctrl[14].val[15] = 0; + + Tuner->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ; + Tuner->Init_Ctrl[15].size = 3 ; + Tuner->Init_Ctrl[15].addr[0] = 147; + Tuner->Init_Ctrl[15].bit[0] = 2; + Tuner->Init_Ctrl[15].val[0] = 0; + Tuner->Init_Ctrl[15].addr[1] = 147; + Tuner->Init_Ctrl[15].bit[1] = 3; + Tuner->Init_Ctrl[15].val[1] = 1; + Tuner->Init_Ctrl[15].addr[2] = 147; + Tuner->Init_Ctrl[15].bit[2] = 4; + Tuner->Init_Ctrl[15].val[2] = 1; + + Tuner->Init_Ctrl[16].Ctrl_Num = I_DRIVER ; + Tuner->Init_Ctrl[16].size = 2 ; + Tuner->Init_Ctrl[16].addr[0] = 147; + Tuner->Init_Ctrl[16].bit[0] = 0; + Tuner->Init_Ctrl[16].val[0] = 0; + Tuner->Init_Ctrl[16].addr[1] = 147; + Tuner->Init_Ctrl[16].bit[1] = 1; + Tuner->Init_Ctrl[16].val[1] = 1; + + Tuner->Init_Ctrl[17].Ctrl_Num = EN_AAF ; + Tuner->Init_Ctrl[17].size = 1 ; + Tuner->Init_Ctrl[17].addr[0] = 147; + Tuner->Init_Ctrl[17].bit[0] = 7; + Tuner->Init_Ctrl[17].val[0] = 0; + + Tuner->Init_Ctrl[18].Ctrl_Num = EN_3P ; + Tuner->Init_Ctrl[18].size = 1 ; + Tuner->Init_Ctrl[18].addr[0] = 147; + Tuner->Init_Ctrl[18].bit[0] = 6; + Tuner->Init_Ctrl[18].val[0] = 0; + + Tuner->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ; + Tuner->Init_Ctrl[19].size = 1 ; + Tuner->Init_Ctrl[19].addr[0] = 156; + Tuner->Init_Ctrl[19].bit[0] = 0; + Tuner->Init_Ctrl[19].val[0] = 0; + + Tuner->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ; + Tuner->Init_Ctrl[20].size = 1 ; + Tuner->Init_Ctrl[20].addr[0] = 147; + Tuner->Init_Ctrl[20].bit[0] = 5; + Tuner->Init_Ctrl[20].val[0] = 0; + + Tuner->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ; + Tuner->Init_Ctrl[21].size = 1 ; + Tuner->Init_Ctrl[21].addr[0] = 137; + Tuner->Init_Ctrl[21].bit[0] = 4; + Tuner->Init_Ctrl[21].val[0] = 0; + + Tuner->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ; + Tuner->Init_Ctrl[22].size = 1 ; + Tuner->Init_Ctrl[22].addr[0] = 137; + Tuner->Init_Ctrl[22].bit[0] = 7; + Tuner->Init_Ctrl[22].val[0] = 0; + + Tuner->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ; + Tuner->Init_Ctrl[23].size = 1 ; + Tuner->Init_Ctrl[23].addr[0] = 91; + Tuner->Init_Ctrl[23].bit[0] = 5; + Tuner->Init_Ctrl[23].val[0] = 1; + + Tuner->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ; + Tuner->Init_Ctrl[24].size = 1 ; + Tuner->Init_Ctrl[24].addr[0] = 43; + Tuner->Init_Ctrl[24].bit[0] = 0; + Tuner->Init_Ctrl[24].val[0] = 1; + + Tuner->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ; + Tuner->Init_Ctrl[25].size = 2 ; + Tuner->Init_Ctrl[25].addr[0] = 22; + Tuner->Init_Ctrl[25].bit[0] = 0; + Tuner->Init_Ctrl[25].val[0] = 1; + Tuner->Init_Ctrl[25].addr[1] = 22; + Tuner->Init_Ctrl[25].bit[1] = 1; + Tuner->Init_Ctrl[25].val[1] = 1; + + Tuner->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ; + Tuner->Init_Ctrl[26].size = 1 ; + Tuner->Init_Ctrl[26].addr[0] = 134; + Tuner->Init_Ctrl[26].bit[0] = 2; + Tuner->Init_Ctrl[26].val[0] = 0; + + Tuner->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ; + Tuner->Init_Ctrl[27].size = 1 ; + Tuner->Init_Ctrl[27].addr[0] = 137; + Tuner->Init_Ctrl[27].bit[0] = 3; + Tuner->Init_Ctrl[27].val[0] = 0; + + Tuner->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ; + Tuner->Init_Ctrl[28].size = 1 ; + Tuner->Init_Ctrl[28].addr[0] = 77; + Tuner->Init_Ctrl[28].bit[0] = 7; + Tuner->Init_Ctrl[28].val[0] = 0; + + Tuner->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ; + Tuner->Init_Ctrl[29].size = 1 ; + Tuner->Init_Ctrl[29].addr[0] = 166; + Tuner->Init_Ctrl[29].bit[0] = 7; + Tuner->Init_Ctrl[29].val[0] = 1; + + Tuner->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ; + Tuner->Init_Ctrl[30].size = 3 ; + Tuner->Init_Ctrl[30].addr[0] = 166; + Tuner->Init_Ctrl[30].bit[0] = 0; + Tuner->Init_Ctrl[30].val[0] = 0; + Tuner->Init_Ctrl[30].addr[1] = 166; + Tuner->Init_Ctrl[30].bit[1] = 1; + Tuner->Init_Ctrl[30].val[1] = 1; + Tuner->Init_Ctrl[30].addr[2] = 166; + Tuner->Init_Ctrl[30].bit[2] = 2; + Tuner->Init_Ctrl[30].val[2] = 1; + + Tuner->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ; + Tuner->Init_Ctrl[31].size = 3 ; + Tuner->Init_Ctrl[31].addr[0] = 166; + Tuner->Init_Ctrl[31].bit[0] = 3; + Tuner->Init_Ctrl[31].val[0] = 1; + Tuner->Init_Ctrl[31].addr[1] = 166; + Tuner->Init_Ctrl[31].bit[1] = 4; + Tuner->Init_Ctrl[31].val[1] = 0; + Tuner->Init_Ctrl[31].addr[2] = 166; + Tuner->Init_Ctrl[31].bit[2] = 5; + Tuner->Init_Ctrl[31].val[2] = 1; + + Tuner->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ; + Tuner->Init_Ctrl[32].size = 3 ; + Tuner->Init_Ctrl[32].addr[0] = 167; + Tuner->Init_Ctrl[32].bit[0] = 0; + Tuner->Init_Ctrl[32].val[0] = 1; + Tuner->Init_Ctrl[32].addr[1] = 167; + Tuner->Init_Ctrl[32].bit[1] = 1; + Tuner->Init_Ctrl[32].val[1] = 1; + Tuner->Init_Ctrl[32].addr[2] = 167; + Tuner->Init_Ctrl[32].bit[2] = 2; + Tuner->Init_Ctrl[32].val[2] = 0; + + Tuner->Init_Ctrl[33].Ctrl_Num = RFA_FLR ; + Tuner->Init_Ctrl[33].size = 4 ; + Tuner->Init_Ctrl[33].addr[0] = 168; + Tuner->Init_Ctrl[33].bit[0] = 0; + Tuner->Init_Ctrl[33].val[0] = 0; + Tuner->Init_Ctrl[33].addr[1] = 168; + Tuner->Init_Ctrl[33].bit[1] = 1; + Tuner->Init_Ctrl[33].val[1] = 1; + Tuner->Init_Ctrl[33].addr[2] = 168; + Tuner->Init_Ctrl[33].bit[2] = 2; + Tuner->Init_Ctrl[33].val[2] = 0; + Tuner->Init_Ctrl[33].addr[3] = 168; + Tuner->Init_Ctrl[33].bit[3] = 3; + Tuner->Init_Ctrl[33].val[3] = 0; + + Tuner->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ; + Tuner->Init_Ctrl[34].size = 4 ; + Tuner->Init_Ctrl[34].addr[0] = 168; + Tuner->Init_Ctrl[34].bit[0] = 4; + Tuner->Init_Ctrl[34].val[0] = 1; + Tuner->Init_Ctrl[34].addr[1] = 168; + Tuner->Init_Ctrl[34].bit[1] = 5; + Tuner->Init_Ctrl[34].val[1] = 1; + Tuner->Init_Ctrl[34].addr[2] = 168; + Tuner->Init_Ctrl[34].bit[2] = 6; + Tuner->Init_Ctrl[34].val[2] = 1; + Tuner->Init_Ctrl[34].addr[3] = 168; + Tuner->Init_Ctrl[34].bit[3] = 7; + Tuner->Init_Ctrl[34].val[3] = 1; + + Tuner->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ; + Tuner->Init_Ctrl[35].size = 1 ; + Tuner->Init_Ctrl[35].addr[0] = 135; + Tuner->Init_Ctrl[35].bit[0] = 0; + Tuner->Init_Ctrl[35].val[0] = 0; + + Tuner->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ; + Tuner->Init_Ctrl[36].size = 1 ; + Tuner->Init_Ctrl[36].addr[0] = 56; + Tuner->Init_Ctrl[36].bit[0] = 3; + Tuner->Init_Ctrl[36].val[0] = 0; + + Tuner->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ; + Tuner->Init_Ctrl[37].size = 7 ; + Tuner->Init_Ctrl[37].addr[0] = 59; + Tuner->Init_Ctrl[37].bit[0] = 1; + Tuner->Init_Ctrl[37].val[0] = 0; + Tuner->Init_Ctrl[37].addr[1] = 59; + Tuner->Init_Ctrl[37].bit[1] = 2; + Tuner->Init_Ctrl[37].val[1] = 0; + Tuner->Init_Ctrl[37].addr[2] = 59; + Tuner->Init_Ctrl[37].bit[2] = 3; + Tuner->Init_Ctrl[37].val[2] = 0; + Tuner->Init_Ctrl[37].addr[3] = 59; + Tuner->Init_Ctrl[37].bit[3] = 4; + Tuner->Init_Ctrl[37].val[3] = 0; + Tuner->Init_Ctrl[37].addr[4] = 59; + Tuner->Init_Ctrl[37].bit[4] = 5; + Tuner->Init_Ctrl[37].val[4] = 0; + Tuner->Init_Ctrl[37].addr[5] = 59; + Tuner->Init_Ctrl[37].bit[5] = 6; + Tuner->Init_Ctrl[37].val[5] = 0; + Tuner->Init_Ctrl[37].addr[6] = 59; + Tuner->Init_Ctrl[37].bit[6] = 7; + Tuner->Init_Ctrl[37].val[6] = 0; + + Tuner->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ; + Tuner->Init_Ctrl[38].size = 6 ; + Tuner->Init_Ctrl[38].addr[0] = 32; + Tuner->Init_Ctrl[38].bit[0] = 2; + Tuner->Init_Ctrl[38].val[0] = 0; + Tuner->Init_Ctrl[38].addr[1] = 32; + Tuner->Init_Ctrl[38].bit[1] = 3; + Tuner->Init_Ctrl[38].val[1] = 0; + Tuner->Init_Ctrl[38].addr[2] = 32; + Tuner->Init_Ctrl[38].bit[2] = 4; + Tuner->Init_Ctrl[38].val[2] = 0; + Tuner->Init_Ctrl[38].addr[3] = 32; + Tuner->Init_Ctrl[38].bit[3] = 5; + Tuner->Init_Ctrl[38].val[3] = 0; + Tuner->Init_Ctrl[38].addr[4] = 32; + Tuner->Init_Ctrl[38].bit[4] = 6; + Tuner->Init_Ctrl[38].val[4] = 1; + Tuner->Init_Ctrl[38].addr[5] = 32; + Tuner->Init_Ctrl[38].bit[5] = 7; + Tuner->Init_Ctrl[38].val[5] = 0; + + Tuner->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ; + Tuner->Init_Ctrl[39].size = 1 ; + Tuner->Init_Ctrl[39].addr[0] = 25; + Tuner->Init_Ctrl[39].bit[0] = 3; + Tuner->Init_Ctrl[39].val[0] = 1; + + + Tuner->CH_Ctrl_Num = CHCTRL_NUM ; + + Tuner->CH_Ctrl[0].Ctrl_Num = DN_POLY ; + Tuner->CH_Ctrl[0].size = 2 ; + Tuner->CH_Ctrl[0].addr[0] = 68; + Tuner->CH_Ctrl[0].bit[0] = 6; + Tuner->CH_Ctrl[0].val[0] = 1; + Tuner->CH_Ctrl[0].addr[1] = 68; + Tuner->CH_Ctrl[0].bit[1] = 7; + Tuner->CH_Ctrl[0].val[1] = 1; + + Tuner->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ; + Tuner->CH_Ctrl[1].size = 2 ; + Tuner->CH_Ctrl[1].addr[0] = 70; + Tuner->CH_Ctrl[1].bit[0] = 6; + Tuner->CH_Ctrl[1].val[0] = 1; + Tuner->CH_Ctrl[1].addr[1] = 70; + Tuner->CH_Ctrl[1].bit[1] = 7; + Tuner->CH_Ctrl[1].val[1] = 0; + + Tuner->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ; + Tuner->CH_Ctrl[2].size = 9 ; + Tuner->CH_Ctrl[2].addr[0] = 69; + Tuner->CH_Ctrl[2].bit[0] = 5; + Tuner->CH_Ctrl[2].val[0] = 0; + Tuner->CH_Ctrl[2].addr[1] = 69; + Tuner->CH_Ctrl[2].bit[1] = 6; + Tuner->CH_Ctrl[2].val[1] = 0; + Tuner->CH_Ctrl[2].addr[2] = 69; + Tuner->CH_Ctrl[2].bit[2] = 7; + Tuner->CH_Ctrl[2].val[2] = 0; + Tuner->CH_Ctrl[2].addr[3] = 68; + Tuner->CH_Ctrl[2].bit[3] = 0; + Tuner->CH_Ctrl[2].val[3] = 0; + Tuner->CH_Ctrl[2].addr[4] = 68; + Tuner->CH_Ctrl[2].bit[4] = 1; + Tuner->CH_Ctrl[2].val[4] = 0; + Tuner->CH_Ctrl[2].addr[5] = 68; + Tuner->CH_Ctrl[2].bit[5] = 2; + Tuner->CH_Ctrl[2].val[5] = 0; + Tuner->CH_Ctrl[2].addr[6] = 68; + Tuner->CH_Ctrl[2].bit[6] = 3; + Tuner->CH_Ctrl[2].val[6] = 0; + Tuner->CH_Ctrl[2].addr[7] = 68; + Tuner->CH_Ctrl[2].bit[7] = 4; + Tuner->CH_Ctrl[2].val[7] = 0; + Tuner->CH_Ctrl[2].addr[8] = 68; + Tuner->CH_Ctrl[2].bit[8] = 5; + Tuner->CH_Ctrl[2].val[8] = 0; + + Tuner->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ; + Tuner->CH_Ctrl[3].size = 1 ; + Tuner->CH_Ctrl[3].addr[0] = 70; + Tuner->CH_Ctrl[3].bit[0] = 5; + Tuner->CH_Ctrl[3].val[0] = 0; + + Tuner->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ; + Tuner->CH_Ctrl[4].size = 3 ; + Tuner->CH_Ctrl[4].addr[0] = 73; + Tuner->CH_Ctrl[4].bit[0] = 4; + Tuner->CH_Ctrl[4].val[0] = 0; + Tuner->CH_Ctrl[4].addr[1] = 73; + Tuner->CH_Ctrl[4].bit[1] = 5; + Tuner->CH_Ctrl[4].val[1] = 1; + Tuner->CH_Ctrl[4].addr[2] = 73; + Tuner->CH_Ctrl[4].bit[2] = 6; + Tuner->CH_Ctrl[4].val[2] = 0; + + Tuner->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ; + Tuner->CH_Ctrl[5].size = 4 ; + Tuner->CH_Ctrl[5].addr[0] = 70; + Tuner->CH_Ctrl[5].bit[0] = 0; + Tuner->CH_Ctrl[5].val[0] = 0; + Tuner->CH_Ctrl[5].addr[1] = 70; + Tuner->CH_Ctrl[5].bit[1] = 1; + Tuner->CH_Ctrl[5].val[1] = 0; + Tuner->CH_Ctrl[5].addr[2] = 70; + Tuner->CH_Ctrl[5].bit[2] = 2; + Tuner->CH_Ctrl[5].val[2] = 0; + Tuner->CH_Ctrl[5].addr[3] = 70; + Tuner->CH_Ctrl[5].bit[3] = 3; + Tuner->CH_Ctrl[5].val[3] = 0; + + Tuner->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ; + Tuner->CH_Ctrl[6].size = 1 ; + Tuner->CH_Ctrl[6].addr[0] = 70; + Tuner->CH_Ctrl[6].bit[0] = 4; + Tuner->CH_Ctrl[6].val[0] = 1; + + Tuner->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ; + Tuner->CH_Ctrl[7].size = 1 ; + Tuner->CH_Ctrl[7].addr[0] = 111; + Tuner->CH_Ctrl[7].bit[0] = 4; + Tuner->CH_Ctrl[7].val[0] = 0; + + Tuner->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ; + Tuner->CH_Ctrl[8].size = 1 ; + Tuner->CH_Ctrl[8].addr[0] = 111; + Tuner->CH_Ctrl[8].bit[0] = 7; + Tuner->CH_Ctrl[8].val[0] = 1; + + Tuner->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ; + Tuner->CH_Ctrl[9].size = 1 ; + Tuner->CH_Ctrl[9].addr[0] = 111; + Tuner->CH_Ctrl[9].bit[0] = 6; + Tuner->CH_Ctrl[9].val[0] = 1; + + Tuner->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ; + Tuner->CH_Ctrl[10].size = 1 ; + Tuner->CH_Ctrl[10].addr[0] = 111; + Tuner->CH_Ctrl[10].bit[0] = 5; + Tuner->CH_Ctrl[10].val[0] = 0; + + Tuner->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ; + Tuner->CH_Ctrl[11].size = 2 ; + Tuner->CH_Ctrl[11].addr[0] = 110; + Tuner->CH_Ctrl[11].bit[0] = 0; + Tuner->CH_Ctrl[11].val[0] = 1; + Tuner->CH_Ctrl[11].addr[1] = 110; + Tuner->CH_Ctrl[11].bit[1] = 1; + Tuner->CH_Ctrl[11].val[1] = 0; + + Tuner->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ; + Tuner->CH_Ctrl[12].size = 3 ; + Tuner->CH_Ctrl[12].addr[0] = 69; + Tuner->CH_Ctrl[12].bit[0] = 2; + Tuner->CH_Ctrl[12].val[0] = 0; + Tuner->CH_Ctrl[12].addr[1] = 69; + Tuner->CH_Ctrl[12].bit[1] = 3; + Tuner->CH_Ctrl[12].val[1] = 0; + Tuner->CH_Ctrl[12].addr[2] = 69; + Tuner->CH_Ctrl[12].bit[2] = 4; + Tuner->CH_Ctrl[12].val[2] = 0; + + Tuner->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ; + Tuner->CH_Ctrl[13].size = 6 ; + Tuner->CH_Ctrl[13].addr[0] = 110; + Tuner->CH_Ctrl[13].bit[0] = 2; + Tuner->CH_Ctrl[13].val[0] = 0; + Tuner->CH_Ctrl[13].addr[1] = 110; + Tuner->CH_Ctrl[13].bit[1] = 3; + Tuner->CH_Ctrl[13].val[1] = 0; + Tuner->CH_Ctrl[13].addr[2] = 110; + Tuner->CH_Ctrl[13].bit[2] = 4; + Tuner->CH_Ctrl[13].val[2] = 0; + Tuner->CH_Ctrl[13].addr[3] = 110; + Tuner->CH_Ctrl[13].bit[3] = 5; + Tuner->CH_Ctrl[13].val[3] = 0; + Tuner->CH_Ctrl[13].addr[4] = 110; + Tuner->CH_Ctrl[13].bit[4] = 6; + Tuner->CH_Ctrl[13].val[4] = 0; + Tuner->CH_Ctrl[13].addr[5] = 110; + Tuner->CH_Ctrl[13].bit[5] = 7; + Tuner->CH_Ctrl[13].val[5] = 1; + + Tuner->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ; + Tuner->CH_Ctrl[14].size = 7 ; + Tuner->CH_Ctrl[14].addr[0] = 14; + Tuner->CH_Ctrl[14].bit[0] = 0; + Tuner->CH_Ctrl[14].val[0] = 0; + Tuner->CH_Ctrl[14].addr[1] = 14; + Tuner->CH_Ctrl[14].bit[1] = 1; + Tuner->CH_Ctrl[14].val[1] = 0; + Tuner->CH_Ctrl[14].addr[2] = 14; + Tuner->CH_Ctrl[14].bit[2] = 2; + Tuner->CH_Ctrl[14].val[2] = 0; + Tuner->CH_Ctrl[14].addr[3] = 14; + Tuner->CH_Ctrl[14].bit[3] = 3; + Tuner->CH_Ctrl[14].val[3] = 0; + Tuner->CH_Ctrl[14].addr[4] = 14; + Tuner->CH_Ctrl[14].bit[4] = 4; + Tuner->CH_Ctrl[14].val[4] = 0; + Tuner->CH_Ctrl[14].addr[5] = 14; + Tuner->CH_Ctrl[14].bit[5] = 5; + Tuner->CH_Ctrl[14].val[5] = 0; + Tuner->CH_Ctrl[14].addr[6] = 14; + Tuner->CH_Ctrl[14].bit[6] = 6; + Tuner->CH_Ctrl[14].val[6] = 0; + + Tuner->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ; + Tuner->CH_Ctrl[15].size = 18 ; + Tuner->CH_Ctrl[15].addr[0] = 17; + Tuner->CH_Ctrl[15].bit[0] = 6; + Tuner->CH_Ctrl[15].val[0] = 0; + Tuner->CH_Ctrl[15].addr[1] = 17; + Tuner->CH_Ctrl[15].bit[1] = 7; + Tuner->CH_Ctrl[15].val[1] = 0; + Tuner->CH_Ctrl[15].addr[2] = 16; + Tuner->CH_Ctrl[15].bit[2] = 0; + Tuner->CH_Ctrl[15].val[2] = 0; + Tuner->CH_Ctrl[15].addr[3] = 16; + Tuner->CH_Ctrl[15].bit[3] = 1; + Tuner->CH_Ctrl[15].val[3] = 0; + Tuner->CH_Ctrl[15].addr[4] = 16; + Tuner->CH_Ctrl[15].bit[4] = 2; + Tuner->CH_Ctrl[15].val[4] = 0; + Tuner->CH_Ctrl[15].addr[5] = 16; + Tuner->CH_Ctrl[15].bit[5] = 3; + Tuner->CH_Ctrl[15].val[5] = 0; + Tuner->CH_Ctrl[15].addr[6] = 16; + Tuner->CH_Ctrl[15].bit[6] = 4; + Tuner->CH_Ctrl[15].val[6] = 0; + Tuner->CH_Ctrl[15].addr[7] = 16; + Tuner->CH_Ctrl[15].bit[7] = 5; + Tuner->CH_Ctrl[15].val[7] = 0; + Tuner->CH_Ctrl[15].addr[8] = 16; + Tuner->CH_Ctrl[15].bit[8] = 6; + Tuner->CH_Ctrl[15].val[8] = 0; + Tuner->CH_Ctrl[15].addr[9] = 16; + Tuner->CH_Ctrl[15].bit[9] = 7; + Tuner->CH_Ctrl[15].val[9] = 0; + Tuner->CH_Ctrl[15].addr[10] = 15; + Tuner->CH_Ctrl[15].bit[10] = 0; + Tuner->CH_Ctrl[15].val[10] = 0; + Tuner->CH_Ctrl[15].addr[11] = 15; + Tuner->CH_Ctrl[15].bit[11] = 1; + Tuner->CH_Ctrl[15].val[11] = 0; + Tuner->CH_Ctrl[15].addr[12] = 15; + Tuner->CH_Ctrl[15].bit[12] = 2; + Tuner->CH_Ctrl[15].val[12] = 0; + Tuner->CH_Ctrl[15].addr[13] = 15; + Tuner->CH_Ctrl[15].bit[13] = 3; + Tuner->CH_Ctrl[15].val[13] = 0; + Tuner->CH_Ctrl[15].addr[14] = 15; + Tuner->CH_Ctrl[15].bit[14] = 4; + Tuner->CH_Ctrl[15].val[14] = 0; + Tuner->CH_Ctrl[15].addr[15] = 15; + Tuner->CH_Ctrl[15].bit[15] = 5; + Tuner->CH_Ctrl[15].val[15] = 0; + Tuner->CH_Ctrl[15].addr[16] = 15; + Tuner->CH_Ctrl[15].bit[16] = 6; + Tuner->CH_Ctrl[15].val[16] = 1; + Tuner->CH_Ctrl[15].addr[17] = 15; + Tuner->CH_Ctrl[15].bit[17] = 7; + Tuner->CH_Ctrl[15].val[17] = 1; + + Tuner->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ; + Tuner->CH_Ctrl[16].size = 5 ; + Tuner->CH_Ctrl[16].addr[0] = 112; + Tuner->CH_Ctrl[16].bit[0] = 0; + Tuner->CH_Ctrl[16].val[0] = 0; + Tuner->CH_Ctrl[16].addr[1] = 112; + Tuner->CH_Ctrl[16].bit[1] = 1; + Tuner->CH_Ctrl[16].val[1] = 0; + Tuner->CH_Ctrl[16].addr[2] = 112; + Tuner->CH_Ctrl[16].bit[2] = 2; + Tuner->CH_Ctrl[16].val[2] = 0; + Tuner->CH_Ctrl[16].addr[3] = 112; + Tuner->CH_Ctrl[16].bit[3] = 3; + Tuner->CH_Ctrl[16].val[3] = 0; + Tuner->CH_Ctrl[16].addr[4] = 112; + Tuner->CH_Ctrl[16].bit[4] = 4; + Tuner->CH_Ctrl[16].val[4] = 1; + + Tuner->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ; + Tuner->CH_Ctrl[17].size = 1 ; + Tuner->CH_Ctrl[17].addr[0] = 14; + Tuner->CH_Ctrl[17].bit[0] = 7; + Tuner->CH_Ctrl[17].val[0] = 0; + + Tuner->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ; + Tuner->CH_Ctrl[18].size = 4 ; + Tuner->CH_Ctrl[18].addr[0] = 107; + Tuner->CH_Ctrl[18].bit[0] = 3; + Tuner->CH_Ctrl[18].val[0] = 0; + Tuner->CH_Ctrl[18].addr[1] = 107; + Tuner->CH_Ctrl[18].bit[1] = 4; + Tuner->CH_Ctrl[18].val[1] = 0; + Tuner->CH_Ctrl[18].addr[2] = 107; + Tuner->CH_Ctrl[18].bit[2] = 5; + Tuner->CH_Ctrl[18].val[2] = 0; + Tuner->CH_Ctrl[18].addr[3] = 107; + Tuner->CH_Ctrl[18].bit[3] = 6; + Tuner->CH_Ctrl[18].val[3] = 0; + + Tuner->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ; + Tuner->CH_Ctrl[19].size = 3 ; + Tuner->CH_Ctrl[19].addr[0] = 107; + Tuner->CH_Ctrl[19].bit[0] = 7; + Tuner->CH_Ctrl[19].val[0] = 1; + Tuner->CH_Ctrl[19].addr[1] = 106; + Tuner->CH_Ctrl[19].bit[1] = 0; + Tuner->CH_Ctrl[19].val[1] = 1; + Tuner->CH_Ctrl[19].addr[2] = 106; + Tuner->CH_Ctrl[19].bit[2] = 1; + Tuner->CH_Ctrl[19].val[2] = 1; + + Tuner->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ; + Tuner->CH_Ctrl[20].size = 11 ; + Tuner->CH_Ctrl[20].addr[0] = 109; + Tuner->CH_Ctrl[20].bit[0] = 2; + Tuner->CH_Ctrl[20].val[0] = 0; + Tuner->CH_Ctrl[20].addr[1] = 109; + Tuner->CH_Ctrl[20].bit[1] = 3; + Tuner->CH_Ctrl[20].val[1] = 0; + Tuner->CH_Ctrl[20].addr[2] = 109; + Tuner->CH_Ctrl[20].bit[2] = 4; + Tuner->CH_Ctrl[20].val[2] = 0; + Tuner->CH_Ctrl[20].addr[3] = 109; + Tuner->CH_Ctrl[20].bit[3] = 5; + Tuner->CH_Ctrl[20].val[3] = 0; + Tuner->CH_Ctrl[20].addr[4] = 109; + Tuner->CH_Ctrl[20].bit[4] = 6; + Tuner->CH_Ctrl[20].val[4] = 0; + Tuner->CH_Ctrl[20].addr[5] = 109; + Tuner->CH_Ctrl[20].bit[5] = 7; + Tuner->CH_Ctrl[20].val[5] = 0; + Tuner->CH_Ctrl[20].addr[6] = 108; + Tuner->CH_Ctrl[20].bit[6] = 0; + Tuner->CH_Ctrl[20].val[6] = 0; + Tuner->CH_Ctrl[20].addr[7] = 108; + Tuner->CH_Ctrl[20].bit[7] = 1; + Tuner->CH_Ctrl[20].val[7] = 0; + Tuner->CH_Ctrl[20].addr[8] = 108; + Tuner->CH_Ctrl[20].bit[8] = 2; + Tuner->CH_Ctrl[20].val[8] = 1; + Tuner->CH_Ctrl[20].addr[9] = 108; + Tuner->CH_Ctrl[20].bit[9] = 3; + Tuner->CH_Ctrl[20].val[9] = 1; + Tuner->CH_Ctrl[20].addr[10] = 108; + Tuner->CH_Ctrl[20].bit[10] = 4; + Tuner->CH_Ctrl[20].val[10] = 1; + + Tuner->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ; + Tuner->CH_Ctrl[21].size = 6 ; + Tuner->CH_Ctrl[21].addr[0] = 106; + Tuner->CH_Ctrl[21].bit[0] = 2; + Tuner->CH_Ctrl[21].val[0] = 0; + Tuner->CH_Ctrl[21].addr[1] = 106; + Tuner->CH_Ctrl[21].bit[1] = 3; + Tuner->CH_Ctrl[21].val[1] = 0; + Tuner->CH_Ctrl[21].addr[2] = 106; + Tuner->CH_Ctrl[21].bit[2] = 4; + Tuner->CH_Ctrl[21].val[2] = 0; + Tuner->CH_Ctrl[21].addr[3] = 106; + Tuner->CH_Ctrl[21].bit[3] = 5; + Tuner->CH_Ctrl[21].val[3] = 0; + Tuner->CH_Ctrl[21].addr[4] = 106; + Tuner->CH_Ctrl[21].bit[4] = 6; + Tuner->CH_Ctrl[21].val[4] = 0; + Tuner->CH_Ctrl[21].addr[5] = 106; + Tuner->CH_Ctrl[21].bit[5] = 7; + Tuner->CH_Ctrl[21].val[5] = 1; + + Tuner->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ; + Tuner->CH_Ctrl[22].size = 1 ; + Tuner->CH_Ctrl[22].addr[0] = 138; + Tuner->CH_Ctrl[22].bit[0] = 4; + Tuner->CH_Ctrl[22].val[0] = 1; + + Tuner->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ; + Tuner->CH_Ctrl[23].size = 1 ; + Tuner->CH_Ctrl[23].addr[0] = 17; + Tuner->CH_Ctrl[23].bit[0] = 5; + Tuner->CH_Ctrl[23].val[0] = 0; + + Tuner->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ; + Tuner->CH_Ctrl[24].size = 1 ; + Tuner->CH_Ctrl[24].addr[0] = 111; + Tuner->CH_Ctrl[24].bit[0] = 3; + Tuner->CH_Ctrl[24].val[0] = 0; + + Tuner->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ; + Tuner->CH_Ctrl[25].size = 1 ; + Tuner->CH_Ctrl[25].addr[0] = 112; + Tuner->CH_Ctrl[25].bit[0] = 7; + Tuner->CH_Ctrl[25].val[0] = 0; + + Tuner->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ; + Tuner->CH_Ctrl[26].size = 1 ; + Tuner->CH_Ctrl[26].addr[0] = 136; + Tuner->CH_Ctrl[26].bit[0] = 7; + Tuner->CH_Ctrl[26].val[0] = 0; + + Tuner->CH_Ctrl[27].Ctrl_Num = GPIO_4B ; + Tuner->CH_Ctrl[27].size = 1 ; + Tuner->CH_Ctrl[27].addr[0] = 149; + Tuner->CH_Ctrl[27].bit[0] = 7; + Tuner->CH_Ctrl[27].val[0] = 0; + + Tuner->CH_Ctrl[28].Ctrl_Num = GPIO_3B ; + Tuner->CH_Ctrl[28].size = 1 ; + Tuner->CH_Ctrl[28].addr[0] = 149; + Tuner->CH_Ctrl[28].bit[0] = 6; + Tuner->CH_Ctrl[28].val[0] = 0; + + Tuner->CH_Ctrl[29].Ctrl_Num = GPIO_4 ; + Tuner->CH_Ctrl[29].size = 1 ; + Tuner->CH_Ctrl[29].addr[0] = 149; + Tuner->CH_Ctrl[29].bit[0] = 5; + Tuner->CH_Ctrl[29].val[0] = 1; + + Tuner->CH_Ctrl[30].Ctrl_Num = GPIO_3 ; + Tuner->CH_Ctrl[30].size = 1 ; + Tuner->CH_Ctrl[30].addr[0] = 149; + Tuner->CH_Ctrl[30].bit[0] = 4; + Tuner->CH_Ctrl[30].val[0] = 1; + + Tuner->CH_Ctrl[31].Ctrl_Num = GPIO_1B ; + Tuner->CH_Ctrl[31].size = 1 ; + Tuner->CH_Ctrl[31].addr[0] = 149; + Tuner->CH_Ctrl[31].bit[0] = 3; + Tuner->CH_Ctrl[31].val[0] = 0; + + Tuner->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ; + Tuner->CH_Ctrl[32].size = 1 ; + Tuner->CH_Ctrl[32].addr[0] = 93; + Tuner->CH_Ctrl[32].bit[0] = 1; + Tuner->CH_Ctrl[32].val[0] = 0; + + Tuner->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ; + Tuner->CH_Ctrl[33].size = 1 ; + Tuner->CH_Ctrl[33].addr[0] = 93; + Tuner->CH_Ctrl[33].bit[0] = 0; + Tuner->CH_Ctrl[33].val[0] = 0; + + Tuner->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ; + Tuner->CH_Ctrl[34].size = 6 ; + Tuner->CH_Ctrl[34].addr[0] = 92; + Tuner->CH_Ctrl[34].bit[0] = 2; + Tuner->CH_Ctrl[34].val[0] = 0; + Tuner->CH_Ctrl[34].addr[1] = 92; + Tuner->CH_Ctrl[34].bit[1] = 3; + Tuner->CH_Ctrl[34].val[1] = 0; + Tuner->CH_Ctrl[34].addr[2] = 92; + Tuner->CH_Ctrl[34].bit[2] = 4; + Tuner->CH_Ctrl[34].val[2] = 0; + Tuner->CH_Ctrl[34].addr[3] = 92; + Tuner->CH_Ctrl[34].bit[3] = 5; + Tuner->CH_Ctrl[34].val[3] = 0; + Tuner->CH_Ctrl[34].addr[4] = 92; + Tuner->CH_Ctrl[34].bit[4] = 6; + Tuner->CH_Ctrl[34].val[4] = 0; + Tuner->CH_Ctrl[34].addr[5] = 92; + Tuner->CH_Ctrl[34].bit[5] = 7; + Tuner->CH_Ctrl[34].val[5] = 0; + + Tuner->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ; + Tuner->CH_Ctrl[35].size = 6 ; + Tuner->CH_Ctrl[35].addr[0] = 93; + Tuner->CH_Ctrl[35].bit[0] = 2; + Tuner->CH_Ctrl[35].val[0] = 0; + Tuner->CH_Ctrl[35].addr[1] = 93; + Tuner->CH_Ctrl[35].bit[1] = 3; + Tuner->CH_Ctrl[35].val[1] = 0; + Tuner->CH_Ctrl[35].addr[2] = 93; + Tuner->CH_Ctrl[35].bit[2] = 4; + Tuner->CH_Ctrl[35].val[2] = 0; + Tuner->CH_Ctrl[35].addr[3] = 93; + Tuner->CH_Ctrl[35].bit[3] = 5; + Tuner->CH_Ctrl[35].val[3] = 0; + Tuner->CH_Ctrl[35].addr[4] = 93; + Tuner->CH_Ctrl[35].bit[4] = 6; + Tuner->CH_Ctrl[35].val[4] = 0; + Tuner->CH_Ctrl[35].addr[5] = 93; + Tuner->CH_Ctrl[35].bit[5] = 7; + Tuner->CH_Ctrl[35].val[5] = 0; + +#ifdef _MXL_PRODUCTION + Tuner->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ; + Tuner->CH_Ctrl[36].size = 1 ; + Tuner->CH_Ctrl[36].addr[0] = 109; + Tuner->CH_Ctrl[36].bit[0] = 1; + Tuner->CH_Ctrl[36].val[0] = 1; + + Tuner->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ; + Tuner->CH_Ctrl[37].size = 2 ; + Tuner->CH_Ctrl[37].addr[0] = 112; + Tuner->CH_Ctrl[37].bit[0] = 5; + Tuner->CH_Ctrl[37].val[0] = 0; + Tuner->CH_Ctrl[37].addr[1] = 112; + Tuner->CH_Ctrl[37].bit[1] = 6; + Tuner->CH_Ctrl[37].val[1] = 0; + + Tuner->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ; + Tuner->CH_Ctrl[38].size = 1 ; + Tuner->CH_Ctrl[38].addr[0] = 65; + Tuner->CH_Ctrl[38].bit[0] = 1; + Tuner->CH_Ctrl[38].val[0] = 0; +#endif + + return 0 ; +} + + + + + + + + + + + + + + + +// MaxLinear source code - MXL5005_c.cpp + + + +// MXL5005.cpp : Defines the initialization routines for the DLL. +// 2.6.12 + + +//#ifdef _MXL_HEADER +//#include "stdafx.h" +//#endif +//#include "MXL5005_c.h" + + +void InitTunerControls(Tuner_struct *Tuner) +{ + MXL5005_RegisterInit(Tuner) ; + MXL5005_ControlInit(Tuner) ; +#ifdef _MXL_INTERNAL + MXL5005_MXLControlInit(Tuner) ; +#endif +} + + + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_ConfigTuner // +// // +// Description: Configure MXL5005Tuner structure for desired // +// Channel Bandwidth/Channel Frequency // +// // +// // +// Functions used: // +// MXL_SynthIFLO_Calc // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// Mode: Tuner Mode (Analog/Digital) // +// IF_Mode: IF Mode ( Zero/Low ) // +// Bandwidth: Filter Channel Bandwidth (in Hz) // +// IF_out: Desired IF out Frequency (in Hz) // +// Fxtal: Crystal Frerquency (in Hz) // +// TOP: 0: Dual AGC; Value: take over point // +// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // +// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // +// DIV_OUT: 0: Div-1; 1: Div-4 // +// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // +// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL5005_TunerConfig(Tuner_struct *Tuner, + _u8 Mode, // 0: Analog Mode ; 1: Digital Mode + _u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF + _u32 Bandwidth, // filter channel bandwidth (6, 7, 8) + _u32 IF_out, // Desired IF Out Frequency + _u32 Fxtal, // XTAL Frequency + _u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 + _u16 TOP, // 0: Dual AGC; Value: take over point + _u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms) + _u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out + _u8 DIV_OUT, // 0: Div-1; 1: Div-4 + _u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable + _u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI + _u8 Mod_Type, // Modulation Type; + // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable + _u8 TF_Type // Tracking Filter + // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H + ) +{ + _u16 status = 0 ; + + Tuner->Mode = Mode ; + Tuner->IF_Mode = IF_mode ; + Tuner->Chan_Bandwidth = Bandwidth ; + Tuner->IF_OUT = IF_out ; + Tuner->Fxtal = Fxtal ; + Tuner->AGC_Mode = AGC_Mode ; + Tuner->TOP = TOP ; + Tuner->IF_OUT_LOAD = IF_OUT_LOAD ; + Tuner->CLOCK_OUT = CLOCK_OUT ; + Tuner->DIV_OUT = DIV_OUT ; + Tuner->CAPSELECT = CAPSELECT ; + Tuner->EN_RSSI = EN_RSSI ; + Tuner->Mod_Type = Mod_Type ; + Tuner->TF_Type = TF_Type ; + + + + // + // Initialize all the controls and registers + // + InitTunerControls (Tuner) ; + // + // Synthesizer LO frequency calculation + // + MXL_SynthIFLO_Calc( Tuner ) ; + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_SynthIFLO_Calc // +// // +// Description: Calculate Internal IF-LO Frequency // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) +{ + if (Tuner->Mode == 1) // Digital Mode + { + Tuner->IF_LO = Tuner->IF_OUT ; + } + else // Analog Mode + { + if(Tuner->IF_Mode == 0) // Analog Zero IF mode + { + Tuner->IF_LO = Tuner->IF_OUT + 400000 ; + } + else // Analog Low IF mode + { + Tuner->IF_LO = Tuner->IF_OUT + Tuner->Chan_Bandwidth/2 ; + } + } +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_SynthRFTGLO_Calc // +// // +// Description: Calculate Internal RF-LO frequency and // +// internal Tone-Gen(TG)-LO frequency // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) +{ + if (Tuner->Mode == 1) // Digital Mode + { + //remove 20.48MHz setting for 2.6.10 + Tuner->RF_LO = Tuner->RF_IN ; + Tuner->TG_LO = Tuner->RF_IN - 750000 ; //change for 2.6.6 + } + else // Analog Mode + { + if(Tuner->IF_Mode == 0) // Analog Zero IF mode + { + Tuner->RF_LO = Tuner->RF_IN - 400000 ; + Tuner->TG_LO = Tuner->RF_IN - 1750000 ; + } + else // Analog Low IF mode + { + Tuner->RF_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth/2 ; + Tuner->TG_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth + 500000 ; + } + } +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_OverwriteICDefault // +// // +// Description: Overwrite the Default Register Setting // +// // +// // +// Functions used: // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) +{ + _u16 status = 0 ; + + status += MXL_ControlWrite(Tuner, OVERRIDE_1, 1) ; + status += MXL_ControlWrite(Tuner, OVERRIDE_2, 1) ; + status += MXL_ControlWrite(Tuner, OVERRIDE_3, 1) ; + status += MXL_ControlWrite(Tuner, OVERRIDE_4, 1) ; + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_BlockInit // +// // +// Description: Tuner Initialization as a function of 'User Settings' // +// * User settings in Tuner strcuture must be assigned // +// first // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// Tuner_struct: structure defined at higher level // +// // +// Inputs: // +// Tuner : Tuner structure defined at higher level // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_BlockInit( Tuner_struct *Tuner ) +{ + _u16 status = 0 ; + + status += MXL_OverwriteICDefault(Tuner) ; + + // + // Downconverter Control + // Dig Ana + status += MXL_ControlWrite(Tuner, DN_IQTN_AMP_CUT, Tuner->Mode ? 1 : 0) ; + + // + // Filter Control + // Dig Ana + status += MXL_ControlWrite(Tuner, BB_MODE, Tuner->Mode ? 0 : 1) ; + status += MXL_ControlWrite(Tuner, BB_BUF, Tuner->Mode ? 3 : 2) ; + status += MXL_ControlWrite(Tuner, BB_BUF_OA, Tuner->Mode ? 1 : 0) ; + + status += MXL_ControlWrite(Tuner, BB_IQSWAP, Tuner->Mode ? 0 : 1) ; + status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 0) ; + + // Initialize Low-Pass Filter + if (Tuner->Mode) { // Digital Mode + switch (Tuner->Chan_Bandwidth) { + case 8000000: + status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 0) ; + break ; + case 7000000: + status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 2) ; + break ; + case 6000000: + status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 3) ; + break ; + } + } else { // Analog Mode + switch (Tuner->Chan_Bandwidth) { + case 8000000: // Low Zero + status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 0 : 3)) ; + break ; + case 7000000: + status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 1 : 4)) ; + break ; + case 6000000: + status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 2 : 5)) ; + break ; + } + } + + // + // Charge Pump Control + // Dig Ana + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, Tuner->Mode ? 5 : 8) ; + status += MXL_ControlWrite(Tuner, RFSYN_EN_CHP_HIGAIN, Tuner->Mode ? 1 : 1) ; + status += MXL_ControlWrite(Tuner, EN_CHP_LIN_B, Tuner->Mode ? 0 : 0) ; + + // + // AGC TOP Control + // + if (Tuner->AGC_Mode == 0) // Dual AGC + { + status += MXL_ControlWrite(Tuner, AGC_IF, 15) ; + status += MXL_ControlWrite(Tuner, AGC_RF, 15) ; + } + else // Single AGC Mode Dig Ana + status += MXL_ControlWrite(Tuner, AGC_RF, Tuner->Mode? 15 : 12) ; + + + if (Tuner->TOP == 55) // TOP == 5.5 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x0) ; + + if (Tuner->TOP == 72) // TOP == 7.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x1) ; + + if (Tuner->TOP == 92) // TOP == 9.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x2) ; + + if (Tuner->TOP == 110) // TOP == 11.0 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x3) ; + + if (Tuner->TOP == 129) // TOP == 12.9 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x4) ; + + if (Tuner->TOP == 147) // TOP == 14.7 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x5) ; + + if (Tuner->TOP == 168) // TOP == 16.8 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x6) ; + + if (Tuner->TOP == 194) // TOP == 19.4 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x7) ; + + if (Tuner->TOP == 212) // TOP == 21.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x9) ; + + if (Tuner->TOP == 232) // TOP == 23.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xA) ; + + if (Tuner->TOP == 252) // TOP == 25.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xB) ; + + if (Tuner->TOP == 271) // TOP == 27.1 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xC) ; + + if (Tuner->TOP == 292) // TOP == 29.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xD) ; + + if (Tuner->TOP == 317) // TOP == 31.7 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xE) ; + + if (Tuner->TOP == 349) // TOP == 34.9 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xF) ; + + // + // IF Synthesizer Control + // + status += MXL_IFSynthInit( Tuner ) ; + + // + // IF UpConverter Control + if (Tuner->IF_OUT_LOAD == 200) + { + status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 6) ; + status += MXL_ControlWrite(Tuner, I_DRIVER, 2) ; + } + if (Tuner->IF_OUT_LOAD == 300) + { + status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 4) ; + status += MXL_ControlWrite(Tuner, I_DRIVER, 1) ; + } + + // + // Anti-Alias Filtering Control + // + // initialise Anti-Aliasing Filter + if (Tuner->Mode) {// Digital Mode + if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 6280000UL) { + status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; + status += MXL_ControlWrite(Tuner, EN_3P, 1) ; + status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; + status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; + } + if ((Tuner->IF_OUT == 36125000UL) || (Tuner->IF_OUT == 36150000UL)) { + status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; + status += MXL_ControlWrite(Tuner, EN_3P, 1) ; + status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; + status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ; + } + if (Tuner->IF_OUT > 36150000UL) { + status += MXL_ControlWrite(Tuner, EN_AAF, 0) ; + status += MXL_ControlWrite(Tuner, EN_3P, 1) ; + status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; + status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ; + } + } else { // Analog Mode + if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 5000000UL) + { + status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; + status += MXL_ControlWrite(Tuner, EN_3P, 1) ; + status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; + status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; + } + if (Tuner->IF_OUT > 5000000UL) + { + status += MXL_ControlWrite(Tuner, EN_AAF, 0) ; + status += MXL_ControlWrite(Tuner, EN_3P, 0) ; + status += MXL_ControlWrite(Tuner, EN_AUX_3P, 0) ; + status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; + } + } + + // + // Demod Clock Out + // + if (Tuner->CLOCK_OUT) + status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 1) ; + else + status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 0) ; + + if (Tuner->DIV_OUT == 1) + status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 1) ; + if (Tuner->DIV_OUT == 0) + status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 0) ; + + // + // Crystal Control + // + if (Tuner->CAPSELECT) + status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 1) ; + else + status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 0) ; + + if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) + status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 1) ; + if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL) + status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 0) ; + + if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL) + status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 3) ; + if (Tuner->Fxtal > 22000000UL && Tuner->Fxtal <= 32000000UL) + status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 0) ; + + // + // Misc Controls + // + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog LowIF mode + status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 0); + else + status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 1); + +// status += MXL_ControlRead(Tuner, IF_DIVVAL, &IF_DIVVAL_Val) ; + + // Set TG_R_DIV + status += MXL_ControlWrite(Tuner, TG_R_DIV, MXL_Ceiling(Tuner->Fxtal, 1000000)) ; + + // + // Apply Default value to BB_INITSTATE_DLPF_TUNE + // + + + + // + // RSSI Control + // + if(Tuner->EN_RSSI) + { + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 3) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; + // TOP point + status += MXL_ControlWrite(Tuner, RFA_FLR, 0) ; + status += MXL_ControlWrite(Tuner, RFA_CEIL, 12) ; + } + + // + // Modulation type bit settings + // Override the control values preset + // + if (Tuner->Mod_Type == MXL_DVBT) // DVB-T Mode + { + Tuner->AGC_Mode = 1 ; // Single AGC Mode + + // Enable RSSI + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; + // TOP point + status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ; + status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ; + if (Tuner->IF_OUT <= 6280000UL) // Low IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; + else // High IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + + } + if (Tuner->Mod_Type == MXL_ATSC) // ATSC Mode + { + Tuner->AGC_Mode = 1 ; // Single AGC Mode + + // Enable RSSI + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 4) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; + // TOP point + status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ; + status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ; + + status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; // Low Zero + if (Tuner->IF_OUT <= 6280000UL) // Low IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; + else // High IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + } + if (Tuner->Mod_Type == MXL_QAM) // QAM Mode + { + Tuner->Mode = MXL_DIGITAL_MODE; + + //Tuner->AGC_Mode = 1 ; // Single AGC Mode + + // Disable RSSI //change here for v2.6.5 + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; + + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; //change here for v2.6.5 + + if (Tuner->IF_OUT <= 6280000UL) // Low IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; + else // High IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + } + if (Tuner->Mod_Type == MXL_ANALOG_CABLE) // Analog Cable Mode + { + //Tuner->Mode = MXL_DIGITAL_MODE ; + Tuner->AGC_Mode = 1 ; // Single AGC Mode + + // Disable RSSI + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + + status += MXL_ControlWrite(Tuner, AGC_IF, 1) ; //change for 2.6.3 + status += MXL_ControlWrite(Tuner, AGC_RF, 15) ; + + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + } + + if (Tuner->Mod_Type == MXL_ANALOG_OTA) //Analog OTA Terrestrial mode add for 2.6.7 + { + //Tuner->Mode = MXL_ANALOG_MODE; + + // Enable RSSI + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; + + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; + + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + } + + // RSSI disable + if(Tuner->EN_RSSI==0) + { + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + } + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_IFSynthInit // +// // +// Description: Tuner IF Synthesizer related register initialization // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// Tuner_struct: structure defined at higher level // +// // +// Inputs: // +// Tuner : Tuner structure defined at higher level // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_IFSynthInit( Tuner_struct * Tuner ) +{ + _u16 status = 0 ; + // Declare Local Variables + _u32 Fref = 0 ; + _u32 Kdbl, intModVal ; + _u32 fracModVal ; + Kdbl = 2 ; + + if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) + Kdbl = 2 ; + if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL) + Kdbl = 1 ; + + // + // IF Synthesizer Control + // + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF mode + { + if (Tuner->IF_LO == 41000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 328000000UL ; + } + if (Tuner->IF_LO == 47000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 376000000UL ; + } + if (Tuner->IF_LO == 54000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 324000000UL ; + } + if (Tuner->IF_LO == 60000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 39250000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 314000000UL ; + } + if (Tuner->IF_LO == 39650000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 317200000UL ; + } + if (Tuner->IF_LO == 40150000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 321200000UL ; + } + if (Tuner->IF_LO == 40650000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 325200000UL ; + } + } + + if (Tuner->Mode || (Tuner->Mode == 0 && Tuner->IF_Mode == 0)) + { + if (Tuner->IF_LO == 57000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 342000000UL ; + } + if (Tuner->IF_LO == 44000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 352000000UL ; + } + if (Tuner->IF_LO == 43750000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 350000000UL ; + } + if (Tuner->IF_LO == 36650000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 366500000UL ; + } + if (Tuner->IF_LO == 36150000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 361500000UL ; + } + if (Tuner->IF_LO == 36000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 35250000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 352500000UL ; + } + if (Tuner->IF_LO == 34750000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 347500000UL ; + } + if (Tuner->IF_LO == 6280000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 376800000UL ; + } + if (Tuner->IF_LO == 5000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 4500000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 4570000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 365600000UL ; + } + if (Tuner->IF_LO == 4000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 57400000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 344400000UL ; + } + if (Tuner->IF_LO == 44400000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 355200000UL ; + } + if (Tuner->IF_LO == 44150000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 353200000UL ; + } + if (Tuner->IF_LO == 37050000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 370500000UL ; + } + if (Tuner->IF_LO == 36550000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 365500000UL ; + } + if (Tuner->IF_LO == 36125000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 361250000UL ; + } + if (Tuner->IF_LO == 6000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 5400000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 324000000UL ; + } + if (Tuner->IF_LO == 5380000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 322800000UL ; + } + if (Tuner->IF_LO == 5200000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 374400000UL ; + } + if (Tuner->IF_LO == 4900000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 352800000UL ; + } + if (Tuner->IF_LO == 4400000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 352000000UL ; + } + if (Tuner->IF_LO == 4063000UL) //add for 2.6.8 + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 365670000UL ; + } + } + // CHCAL_INT_MOD_IF + // CHCAL_FRAC_MOD_IF + intModVal = Fref / (Tuner->Fxtal * Kdbl/2) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_IF, intModVal ) ; + + fracModVal = (2<<15)*(Fref/1000 - (Tuner->Fxtal/1000 * Kdbl/2) * intModVal); + fracModVal = fracModVal / ((Tuner->Fxtal * Kdbl/2)/1000) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_IF, fracModVal) ; + + + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_GetXtalInt // +// // +// Description: return the Crystal Integration Value for // +// TG_VCO_BIAS calculation // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// Crystal Frequency Value in Hz // +// // +// Outputs: // +// Calculated Crystal Frequency Integration Value // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +_u32 MXL_GetXtalInt(_u32 Xtal_Freq) +{ + if ((Xtal_Freq % 1000000) == 0) + return (Xtal_Freq / 10000) ; + else + return (((Xtal_Freq / 1000000) + 1)*100) ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL5005_TuneRF // +// // +// Description: Set control names to tune to requested RF_IN frequency // +// // +// Globals: // +// None // +// // +// Functions used: // +// MXL_SynthRFTGLO_Calc // +// MXL5005_ControlWrite // +// MXL_GetXtalInt // +// // +// Inputs: // +// Tuner : Tuner structure defined at higher level // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// 1 : Unsuccessful // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) +{ + // Declare Local Variables + _u16 status = 0 ; + _u32 divider_val, E3, E4, E5, E5A ; + _u32 Fmax, Fmin, FmaxBin, FminBin ; + _u32 Kdbl_RF = 2; + _u32 tg_divval ; + _u32 tg_lo ; + _u32 Xtal_Int ; + + _u32 Fref_TG; + _u32 Fvco; +// _u32 temp; + + + Xtal_Int = MXL_GetXtalInt(Tuner->Fxtal ) ; + + Tuner->RF_IN = RF_Freq ; + + MXL_SynthRFTGLO_Calc( Tuner ) ; + + if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL) + Kdbl_RF = 2 ; + if (Tuner->Fxtal > 22000000 && Tuner->Fxtal <= 32000000) + Kdbl_RF = 1 ; + + // + // Downconverter Controls + // + // Look-Up Table Implementation for: + // DN_POLY + // DN_RFGAIN + // DN_CAP_RFLPF + // DN_EN_VHFUHFBAR + // DN_GAIN_ADJUST + // Change the boundary reference from RF_IN to RF_LO + if (Tuner->RF_LO < 40000000UL) { + return -1; + } + if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 2) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 423) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ; + } + if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 222) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ; + } + if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 147) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ; + } + if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 9) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ; + } + if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + } + if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 650000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 1) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + } + if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 900000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 2) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + } + if (Tuner->RF_LO > 900000000UL) { + return -1; + } + // DN_IQTNBUF_AMP + // DN_IQTNGNBFBIAS_BST + if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 400000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 400000000UL && Tuner->RF_LO <= 450000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 450000000UL && Tuner->RF_LO <= 500000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 500000000UL && Tuner->RF_LO <= 550000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 550000000UL && Tuner->RF_LO <= 600000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 600000000UL && Tuner->RF_LO <= 650000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 700000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 700000000UL && Tuner->RF_LO <= 750000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 750000000UL && Tuner->RF_LO <= 800000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 800000000UL && Tuner->RF_LO <= 850000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ; + } + if (Tuner->RF_LO > 850000000UL && Tuner->RF_LO <= 900000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ; + } + + // + // Set RF Synth and LO Path Control + // + // Look-Up table implementation for: + // RFSYN_EN_OUTMUX + // RFSYN_SEL_VCO_OUT + // RFSYN_SEL_VCO_HI + // RFSYN_SEL_DIVM + // RFSYN_RF_DIV_BIAS + // DN_SEL_FREQ + // + // Set divider_val, Fmax, Fmix to use in Equations + FminBin = 28000000UL ; + FmaxBin = 42500000UL ; + if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + divider_val = 64 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 42500000UL ; + FmaxBin = 56000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + divider_val = 64 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 56000000UL ; + FmaxBin = 85000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + divider_val = 32 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 85000000UL ; + FmaxBin = 112000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + divider_val = 32 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 112000000UL ; + FmaxBin = 170000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ; + divider_val = 16 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 170000000UL ; + FmaxBin = 225000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ; + divider_val = 16 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 225000000UL ; + FmaxBin = 300000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 4) ; + divider_val = 8 ; + Fmax = 340000000UL ; + Fmin = FminBin ; + } + FminBin = 300000000UL ; + FmaxBin = 340000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + divider_val = 8 ; + Fmax = FmaxBin ; + Fmin = 225000000UL ; + } + FminBin = 340000000UL ; + FmaxBin = 450000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 2) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + divider_val = 8 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 450000000UL ; + FmaxBin = 680000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + divider_val = 4 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 680000000UL ; + FmaxBin = 900000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + divider_val = 4 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + + // CHCAL_INT_MOD_RF + // CHCAL_FRAC_MOD_RF + // RFSYN_LPF_R + // CHCAL_EN_INT_RF + + // Equation E3 + // RFSYN_VCO_BIAS + E3 = (((Fmax-Tuner->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, E3) ; + + // Equation E4 + // CHCAL_INT_MOD_RF + E4 = (Tuner->RF_LO*divider_val/1000)/(2*Tuner->Fxtal*Kdbl_RF/1000) ; + MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, E4) ; + + // Equation E5 + // CHCAL_FRAC_MOD_RF + // CHCAL_EN_INT_RF + E5 = ((2<<17)*(Tuner->RF_LO/10000*divider_val - (E4*(2*Tuner->Fxtal*Kdbl_RF)/10000)))/(2*Tuner->Fxtal*Kdbl_RF/10000) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ; + + // Equation E5A + // RFSYN_LPF_R + E5A = (((Fmax - Tuner->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; + status += MXL_ControlWrite(Tuner, RFSYN_LPF_R, E5A) ; + + // Euqation E5B + // CHCAL_EN_INIT_RF + status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); + //if (E5 == 0) + // status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, 1); + //else + // status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ; + + // + // Set TG Synth + // + // Look-Up table implementation for: + // TG_LO_DIVVAL + // TG_LO_SELVAL + // + // Set divider_val, Fmax, Fmix to use in Equations + if (Tuner->TG_LO < 33000000UL) { + return -1; + } + FminBin = 33000000UL ; + FmaxBin = 50000000UL ; + if (Tuner->TG_LO >= FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x6) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ; + divider_val = 36 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 50000000UL ; + FmaxBin = 67000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x1) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ; + divider_val = 24 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 67000000UL ; + FmaxBin = 100000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0xC) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + divider_val = 18 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 100000000UL ; + FmaxBin = 150000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + divider_val = 12 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 150000000UL ; + FmaxBin = 200000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + divider_val = 8 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 200000000UL ; + FmaxBin = 300000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ; + divider_val = 6 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 300000000UL ; + FmaxBin = 400000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ; + divider_val = 4 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 400000000UL ; + FmaxBin = 600000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ; + divider_val = 3 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 600000000UL ; + FmaxBin = 900000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ; + divider_val = 2 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + + // TG_DIV_VAL + tg_divval = (Tuner->TG_LO*divider_val/100000) + *(MXL_Ceiling(Tuner->Fxtal,1000000) * 100) / (Tuner->Fxtal/1000) ; + status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval) ; + + if (Tuner->TG_LO > 600000000UL) + status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval + 1 ) ; + + Fmax = 1800000000UL ; + Fmin = 1200000000UL ; + + + + // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4 + Fref_TG = (Tuner->Fxtal/1000)/ MXL_Ceiling(Tuner->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000 + + Fvco = (Tuner->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10 + + tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8; + + //below equation is same as above but much harder to debug. + //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((Tuner->TG_LO/10000)*divider_val*(Tuner->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ; + + + status += MXL_ControlWrite(Tuner, TG_VCO_BIAS , tg_lo) ; + + + + //add for 2.6.5 + //Special setting for QAM + if(Tuner ->Mod_Type == MXL_QAM) + { + if(Tuner->RF_IN < 680000000) + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; + else + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 2) ; + } + + + //remove 20.48MHz setting for 2.6.10 + + // + // Off Chip Tracking Filter Control + // + if (Tuner->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; + + status += MXL_SetGPIO(Tuner, 3, 1) ; // turn off Bank 1 + status += MXL_SetGPIO(Tuner, 1, 1) ; // turn off Bank 2 + status += MXL_SetGPIO(Tuner, 4, 1) ; // turn off Bank 3 + } + + if (Tuner->TF_Type == MXL_TF_C) // Tracking Filter type C + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; + status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000) + { + + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 29) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 16) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 7) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only + { + status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000) + { + + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_D) // Tracking Filter type D + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + + + if (Tuner->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 + { + status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + + if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) // if UHF and terrestrial => Turn off Tracking Filter + { + // Turn off all the banks + status += MXL_SetGPIO(Tuner, 3, 1) ; + status += MXL_SetGPIO(Tuner, 1, 1) ; + status += MXL_SetGPIO(Tuner, 4, 1) ; + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; + + status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; + } + + else // if VHF or cable => Turn on Tracking Filter + { + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 140000000) + { + + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + } + if (Tuner->RF_IN >= 140000000 && Tuner->RF_IN < 240000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + } + if (Tuner->RF_IN >= 240000000 && Tuner->RF_IN < 340000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + } + if (Tuner->RF_IN >= 340000000 && Tuner->RF_IN < 430000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + } + if (Tuner->RF_IN >= 430000000 && Tuner->RF_IN < 470000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + } + if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 570000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + } + if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 620000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Offq + } + if (Tuner->RF_IN >= 620000000 && Tuner->RF_IN < 760000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + } + + if (Tuner->TF_Type == MXL_TF_E) // Tracking Filter type E + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_F) // Tracking Filter type F + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 160000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 160000000 && Tuner->RF_IN < 210000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 210000000 && Tuner->RF_IN < 300000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 300000000 && Tuner->RF_IN < 390000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 390000000 && Tuner->RF_IN < 515000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 515000000 && Tuner->RF_IN < 650000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 650000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 50000000 && Tuner->RF_IN < 190000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 190000000 && Tuner->RF_IN < 280000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 350000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 470000000) //modified for 2.6.11 + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN < 820000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 820000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) //if UHF and terrestrial=> Turn off Tracking Filter + { + // Turn off all the banks + status += MXL_SetGPIO(Tuner, 3, 1) ; + status += MXL_SetGPIO(Tuner, 1, 1) ; + status += MXL_SetGPIO(Tuner, 4, 1) ; + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; + + //2.6.12 + //Turn on RSSI + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; + + + //status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; //doesn't matter since RSSI is turn on + + //following parameter is from analog OTA mode, can be change to seek better performance + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; + } + + else //if VHF or Cable => Turn on Tracking Filter + { + //2.6.12 + //Turn off RSSI + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; + + //change back from above condition + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; + + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + } + return status ; +} + +_u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) +{ + _u16 status = 0 ; + + if (GPIO_Num == 1) + status += MXL_ControlWrite(Tuner, GPIO_1B, GPIO_Val ? 0 : 1) ; + // GPIO2 is not available + if (GPIO_Num == 3) + { + if (GPIO_Val == 1) { + status += MXL_ControlWrite(Tuner, GPIO_3, 0) ; + status += MXL_ControlWrite(Tuner, GPIO_3B, 0) ; + } + if (GPIO_Val == 0) { + status += MXL_ControlWrite(Tuner, GPIO_3, 1) ; + status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ; + } + if (GPIO_Val == 3) { // tri-state + status += MXL_ControlWrite(Tuner, GPIO_3, 0) ; + status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ; + } + } + if (GPIO_Num == 4) + { + if (GPIO_Val == 1) { + status += MXL_ControlWrite(Tuner, GPIO_4, 0) ; + status += MXL_ControlWrite(Tuner, GPIO_4B, 0) ; + } + if (GPIO_Val == 0) { + status += MXL_ControlWrite(Tuner, GPIO_4, 1) ; + status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ; + } + if (GPIO_Val == 3) { // tri-state + status += MXL_ControlWrite(Tuner, GPIO_4, 0) ; + status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ; + } + } + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_ControlWrite // +// // +// Description: Update control name value // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// MXL_ControlWrite( Tuner, controlName, value, Group ) // +// // +// Inputs: // +// Tuner : Tuner structure // +// ControlName : Control name to be updated // +// value : Value to be written // +// // +// Outputs: // +// Tuner : Tuner structure defined at higher level // +// // +// Return: // +// 0 : Successful write // +// >0 : Value exceed maximum allowed for control number // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) +{ + _u16 status = 0 ; + // Will write ALL Matching Control Name + status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 1 ) ; // Write Matching INIT Control + status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 2 ) ; // Write Matching CH Control +#ifdef _MXL_INTERNAL + status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 3 ) ; // Write Matching MXL Control +#endif + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_ControlWrite // +// // +// Description: Update control name value // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// strcmp // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// ControlName : Control Name // +// value : Value Assigned to Control Name // +// controlGroup : Control Register Group // +// // +// Outputs: // +// NONE // +// // +// Return: // +// 0 : Successful write // +// 1 : Value exceed maximum allowed for control name // +// 2 : Control name not found // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u16 controlGroup) +{ + _u16 i, j, k ; + _u32 highLimit ; + _u32 ctrlVal ; + + if( controlGroup == 1) // Initial Control + { + for (i=0; iInit_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) + { // find the control Name + highLimit = 1 << Tuner->Init_Ctrl[i].size ; + if ( value < highLimit) + { + for( j=0; jInit_Ctrl[i].size; j++) + { + Tuner->Init_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + // change the register map accordingly + MXL_RegWriteBit( Tuner, (_u8)(Tuner->Init_Ctrl[i].addr[j]), + (_u8)(Tuner->Init_Ctrl[i].bit[j]), + (_u8)((value>>j) & 0x01) ) ; + } + ctrlVal = 0 ; + for(k=0; kInit_Ctrl[i].size; k++) + { + ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ; + } + } + else + { + return -1 ; + } + } + } + } + if ( controlGroup == 2) // Chan change Control + { + for (i=0; iCH_Ctrl_Num; i++) + { + if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) + { // find the control Name + highLimit = 1 << Tuner->CH_Ctrl[i].size ; + if ( value < highLimit) + { + for( j=0; jCH_Ctrl[i].size; j++) + { + Tuner->CH_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + // change the register map accordingly + MXL_RegWriteBit( Tuner, (_u8)(Tuner->CH_Ctrl[i].addr[j]), + (_u8)(Tuner->CH_Ctrl[i].bit[j]), + (_u8)((value>>j) & 0x01) ) ; + } + ctrlVal = 0 ; + for(k=0; kCH_Ctrl[i].size; k++) + { + ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ; + } + } + else + { + return -1 ; + } + } + } + } +#ifdef _MXL_INTERNAL + if ( controlGroup == 3) // Maxlinear Control + { + for (i=0; iMXL_Ctrl_Num; i++) + { + if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) + { // find the control Name + highLimit = (1 << Tuner->MXL_Ctrl[i].size) ; + if ( value < highLimit) + { + for( j=0; jMXL_Ctrl[i].size; j++) + { + Tuner->MXL_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + // change the register map accordingly + MXL_RegWriteBit( Tuner, (_u8)(Tuner->MXL_Ctrl[i].addr[j]), + (_u8)(Tuner->MXL_Ctrl[i].bit[j]), + (_u8)((value>>j) & 0x01) ) ; + } + ctrlVal = 0 ; + for(k=0; kMXL_Ctrl[i].size; k++) + { + ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1 << k) ; + } + } + else + { + return -1 ; + } + } + } + } +#endif + return 0 ; // successful return +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_RegWrite // +// // +// Description: Update tuner register value // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// RegNum : Register address to be assigned a value // +// RegVal : Register value to write // +// // +// Outputs: // +// NONE // +// // +// Return: // +// 0 : Successful write // +// -1 : Invalid Register Address // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) +{ + int i ; + + for (i=0; i<104; i++) + { + if (RegNum == Tuner->TunerRegs[i].Reg_Num ) + { + Tuner->TunerRegs[i].Reg_Val = RegVal ; + return 0 ; + } + } + + return 1 ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_RegRead // +// // +// Description: Retrieve tuner register value // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// RegNum : Register address to be assigned a value // +// // +// Outputs: // +// RegVal : Retrieved register value // +// // +// Return: // +// 0 : Successful read // +// -1 : Invalid Register Address // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) +{ + int i ; + + for (i=0; i<104; i++) + { + if (RegNum == Tuner->TunerRegs[i].Reg_Num ) + { + *RegVal = (_u8)(Tuner->TunerRegs[i].Reg_Val) ; + return 0 ; + } + } + + return 1 ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_ControlRead // +// // +// Description: Retrieve the control value based on the control name // +// // +// Globals: // +// NONE // +// // +// Inputs: // +// Tuner_struct : structure defined at higher level // +// ControlName : Control Name // +// // +// Outputs: // +// value : returned control value // +// // +// Return: // +// 0 : Successful read // +// -1 : Invalid control name // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value) +{ + _u32 ctrlVal ; + _u16 i, k ; + + for (i=0; iInit_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) + { + ctrlVal = 0 ; + for(k=0; kInit_Ctrl[i].size; k++) + ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ; + *value = ctrlVal ; + return 0 ; + } + } + for (i=0; iCH_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) + { + ctrlVal = 0 ; + for(k=0; kCH_Ctrl[i].size; k++) + ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ; + *value = ctrlVal ; + return 0 ; + } + } + +#ifdef _MXL_INTERNAL + for (i=0; iMXL_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) + { + ctrlVal = 0 ; + for(k=0; kMXL_Ctrl[i].size; k++) + ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1<Init_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) + { + Count = 1 ; + RegNum[0] = (_u8)(Tuner->Init_Ctrl[i].addr[0]) ; + + for(k=1; kInit_Ctrl[i].size; k++) + { + for (j= 0; jInit_Ctrl[i].addr[k] != RegNum[j]) + { + Count ++ ; + RegNum[Count-1] = (_u8)(Tuner->Init_Ctrl[i].addr[k]) ; + } + } + + } + *count = Count ; + return 0 ; + } + } + for (i=0; iCH_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) + { + Count = 1 ; + RegNum[0] = (_u8)(Tuner->CH_Ctrl[i].addr[0]) ; + + for(k=1; kCH_Ctrl[i].size; k++) + { + for (j= 0; jCH_Ctrl[i].addr[k] != RegNum[j]) + { + Count ++ ; + RegNum[Count-1] = (_u8)(Tuner->CH_Ctrl[i].addr[k]) ; + } + } + } + *count = Count ; + return 0 ; + } + } +#ifdef _MXL_INTERNAL + for (i=0; iMXL_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) + { + Count = 1 ; + RegNum[0] = (_u8)(Tuner->MXL_Ctrl[i].addr[0]) ; + + for(k=1; kMXL_Ctrl[i].size; k++) + { + for (j= 0; jMXL_Ctrl[i].addr[k] != RegNum[j]) + { + Count ++ ; + RegNum[Count-1] = (_u8)Tuner->MXL_Ctrl[i].addr[k] ; + } + } + } + *count = Count ; + return 0 ; + } + } +#endif + *count = 0 ; + return 1 ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_RegWriteBit // +// // +// Description: Write a register for specified register address, // +// register bit and register bit value // +// // +// Globals: // +// NONE // +// // +// Inputs: // +// Tuner_struct : structure defined at higher level // +// address : register address // +// bit : register bit number // +// bitVal : register bit value // +// // +// Outputs: // +// NONE // +// // +// Return: // +// NONE // +// // +/////////////////////////////////////////////////////////////////////////////// + +void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal) +{ + int i ; + + // Declare Local Constants + const _u8 AND_MAP[8] = { + 0xFE, 0xFD, 0xFB, 0xF7, + 0xEF, 0xDF, 0xBF, 0x7F } ; + + const _u8 OR_MAP[8] = { + 0x01, 0x02, 0x04, 0x08, + 0x10, 0x20, 0x40, 0x80 } ; + + for(i=0; iTunerRegs_Num; i++) { + if ( Tuner->TunerRegs[i].Reg_Num == address ) { + if (bitVal) + Tuner->TunerRegs[i].Reg_Val |= OR_MAP[bit] ; + else + Tuner->TunerRegs[i].Reg_Val &= AND_MAP[bit] ; + break ; + } + } +} ; + + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_Ceiling // +// // +// Description: Complete to closest increment of resolution // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// value : Input number to compute // +// resolution : Increment step // +// // +// Outputs: // +// NONE // +// // +// Return: // +// Computed value // +// // +/////////////////////////////////////////////////////////////////////////////// +_u32 MXL_Ceiling( _u32 value, _u32 resolution ) +{ + return (value/resolution + (value%resolution > 0 ? 1 : 0)) ; +}; + +// +// Retrieve the Initialzation Registers +// +_u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +{ + _u16 status = 0; + int i ; + + _u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, + 76, 77, 91, 134, 135, 137, 147, + 156, 166, 167, 168, 25 } ; + *count = sizeof(RegAddr) / sizeof(_u8) ; + + status += MXL_BlockInit(Tuner) ; + + for (i=0 ; i< *count; i++) + { + RegNum[i] = RegAddr[i] ; + status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + } + + return status ; +} + +_u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +{ + _u16 status = 0; + int i ; + +//add 77, 166, 167, 168 register for 2.6.12 +#ifdef _MXL_PRODUCTION + _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, + 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; +#else + _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, + 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; + //_u8 RegAddr[171]; + //for (i=0; i<=170; i++) + // RegAddr[i] = i; +#endif + + *count = sizeof(RegAddr) / sizeof(_u8) ; + + for (i=0 ; i< *count; i++) + { + RegNum[i] = RegAddr[i] ; + status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + } + + return status ; + +} + +_u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +{ + _u16 status = 0 ; + int i ; + + _u8 RegAddr[] = {43, 136} ; + + *count = sizeof(RegAddr) / sizeof(_u8) ; + + for (i=0; i<*count; i++) + { + RegNum[i] = RegAddr[i] ; + status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + } + return status ; + +} + +_u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +{ + _u16 status = 0 ; + int i ; + + _u8 RegAddr[] = {138} ; + + *count = sizeof(RegAddr) / sizeof(_u8) ; + + for (i=0; i<*count; i++) + { + RegNum[i] = RegAddr[i] ; + status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + } + return status ; + +} + +_u16 MXL_GetMasterControl(_u8 *MasterReg, int state) +{ + if (state == 1) // Load_Start + *MasterReg = 0xF3 ; + if (state == 2) // Power_Down + *MasterReg = 0x41 ; + if (state == 3) // Synth_Reset + *MasterReg = 0xB1 ; + if (state == 4) // Seq_Off + *MasterReg = 0xF1 ; + + return 0 ; +} + +#ifdef _MXL_PRODUCTION +_u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) +{ + _u16 status = 0 ; + + if (VCO_Range == 1) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224 ) ; + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ; + } + if (Tuner->Mode == 1) // Digital Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ; + } + } + + if (VCO_Range == 2) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ; + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; + } + if (Tuner->Mode == 1) // Digital Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384 ) ; + } + } + + if (VCO_Range == 3) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ; + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ; + } + if (Tuner->Mode == 1) // Digital Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760 ) ; + } + } + + if (VCO_Range == 4) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; + } + if (Tuner->Mode == 1) // Digital Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992 ) ; + } + } + + return status ; +} + +_u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) +{ + _u16 status = 0 ; + + if (Hystersis == 1) + status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1) ; + + return status ; +} +#endif + + + + + + + + + + + + + + + diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h new file mode 100644 index 000000000000..8542fc10a9bb --- /dev/null +++ b/drivers/media/common/tuners/mxl5005s.h @@ -0,0 +1,718 @@ +/* + * For the Realtek RTL chip RTL2831U + * Realtek Release Date: 2008-03-14, ver 080314 + * Realtek version RTL2831 Linux driver version 080314 + * ver 080314 + * + * for linux kernel version 2.6.21.4 - 2.6.22-14 + * support MXL5005s and MT2060 tuners (support tuner auto-detecting) + * support two IR types -- RC5 and NEC + * + * Known boards with Realtek RTL chip RTL2821U + * Freecom USB stick 14aa:0160 (version 4) + * Conceptronic CTVDIGRCU + * + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ + + +#ifndef __TUNER_MXL5005S_H +#define __TUNER_MXL5005S_H + + + +// The following context is source code provided by MaxLinear. + + +// MaxLinear source code - Common.h + + + +//#pragma once + +typedef unsigned char _u8; // At least 1 Byte +typedef unsigned short _u16; // At least 2 Bytes +typedef signed short _s16; +typedef unsigned long _u32; // At least 4 Bytes +typedef void * HANDLE; // Pointer to memory location + +#define TUNER_REGS_NUM 104 +#define INITCTRL_NUM 40 +#ifdef _MXL_PRODUCTION +#define CHCTRL_NUM 39 +#else +#define CHCTRL_NUM 36 +#endif + +#define MXLCTRL_NUM 189 + +#define MASTER_CONTROL_ADDR 9 + + + + +// Enumeration of AGC Mode +typedef enum +{ + MXL_DUAL_AGC = 0 , + MXL_SINGLE_AGC +} AGC_Mode ; + +// +// Enumeration of Master Control Register State +// +typedef enum +{ + MC_LOAD_START = 1 , + MC_POWER_DOWN , + MC_SYNTH_RESET , + MC_SEQ_OFF +} Master_Control_State ; + +// +// Enumeration of MXL5005 Tuner Mode +// +typedef enum +{ + MXL_ANALOG_MODE = 0 , + MXL_DIGITAL_MODE + +} Tuner_Mode ; + +// +// Enumeration of MXL5005 Tuner IF Mode +// +typedef enum +{ + MXL_ZERO_IF = 0 , + MXL_LOW_IF + +} Tuner_IF_Mode ; + +// +// Enumeration of MXL5005 Tuner Clock Out Mode +// +typedef enum +{ + MXL_CLOCK_OUT_DISABLE = 0 , + MXL_CLOCK_OUT_ENABLE +} Tuner_Clock_Out ; + +// +// Enumeration of MXL5005 Tuner Div Out Mode +// +typedef enum +{ + MXL_DIV_OUT_1 = 0 , + MXL_DIV_OUT_4 + +} Tuner_Div_Out ; + +// +// Enumeration of MXL5005 Tuner Pull-up Cap Select Mode +// +typedef enum +{ + MXL_CAP_SEL_DISABLE = 0 , + MXL_CAP_SEL_ENABLE + +} Tuner_Cap_Select ; + +// +// Enumeration of MXL5005 Tuner RSSI Mode +// +typedef enum +{ + MXL_RSSI_DISABLE = 0 , + MXL_RSSI_ENABLE + +} Tuner_RSSI ; + +// +// Enumeration of MXL5005 Tuner Modulation Type +// +typedef enum +{ + MXL_DEFAULT_MODULATION = 0 , + MXL_DVBT, + MXL_ATSC, + MXL_QAM, + MXL_ANALOG_CABLE, + MXL_ANALOG_OTA + +} Tuner_Modu_Type ; + +// +// Enumeration of MXL5005 Tuner Tracking Filter Type +// +typedef enum +{ + MXL_TF_DEFAULT = 0 , + MXL_TF_OFF, + MXL_TF_C, + MXL_TF_C_H, + MXL_TF_D, + MXL_TF_D_L, + MXL_TF_E, + MXL_TF_F, + MXL_TF_E_2, + MXL_TF_E_NA, + MXL_TF_G + + +} Tuner_TF_Type ; + + +// +// MXL5005 Tuner Register Struct +// +typedef struct _TunerReg_struct +{ + _u16 Reg_Num ; // Tuner Register Address + _u16 Reg_Val ; // Current sofware programmed value waiting to be writen +} TunerReg_struct ; + +// +// MXL5005 Tuner Control Struct +// +typedef struct _TunerControl_struct { + _u16 Ctrl_Num ; // Control Number + _u16 size ; // Number of bits to represent Value + _u16 addr[25] ; // Array of Tuner Register Address for each bit position + _u16 bit[25] ; // Array of bit position in Register Address for each bit position + _u16 val[25] ; // Binary representation of Value +} TunerControl_struct ; + +// +// MXL5005 Tuner Struct +// +typedef struct _Tuner_struct +{ + _u8 Mode ; // 0: Analog Mode ; 1: Digital Mode + _u8 IF_Mode ; // for Analog Mode, 0: zero IF; 1: low IF + _u32 Chan_Bandwidth ; // filter channel bandwidth (6, 7, 8) + _u32 IF_OUT ; // Desired IF Out Frequency + _u16 IF_OUT_LOAD ; // IF Out Load Resistor (200/300 Ohms) + _u32 RF_IN ; // RF Input Frequency + _u32 Fxtal ; // XTAL Frequency + _u8 AGC_Mode ; // AGC Mode 0: Dual AGC; 1: Single AGC + _u16 TOP ; // Value: take over point + _u8 CLOCK_OUT ; // 0: turn off clock out; 1: turn on clock out + _u8 DIV_OUT ; // 4MHz or 16MHz + _u8 CAPSELECT ; // 0: disable On-Chip pulling cap; 1: enable + _u8 EN_RSSI ; // 0: disable RSSI; 1: enable RSSI + _u8 Mod_Type ; // Modulation Type; + // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable + _u8 TF_Type ; // Tracking Filter Type + // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H + + // Calculated Settings + _u32 RF_LO ; // Synth RF LO Frequency + _u32 IF_LO ; // Synth IF LO Frequency + _u32 TG_LO ; // Synth TG_LO Frequency + + // Pointers to ControlName Arrays + _u16 Init_Ctrl_Num ; // Number of INIT Control Names + TunerControl_struct Init_Ctrl[INITCTRL_NUM] ; // INIT Control Names Array Pointer + _u16 CH_Ctrl_Num ; // Number of CH Control Names + TunerControl_struct CH_Ctrl[CHCTRL_NUM] ; // CH Control Name Array Pointer + _u16 MXL_Ctrl_Num ; // Number of MXL Control Names + TunerControl_struct MXL_Ctrl[MXLCTRL_NUM] ; // MXL Control Name Array Pointer + + // Pointer to Tuner Register Array + _u16 TunerRegs_Num ; // Number of Tuner Registers + TunerReg_struct TunerRegs[TUNER_REGS_NUM] ; // Tuner Register Array Pointer +} Tuner_struct ; + + + +typedef enum +{ + // + // Initialization Control Names + // + DN_IQTN_AMP_CUT = 1 , // 1 + BB_MODE , // 2 + BB_BUF , // 3 + BB_BUF_OA , // 4 + BB_ALPF_BANDSELECT , // 5 + BB_IQSWAP , // 6 + BB_DLPF_BANDSEL , // 7 + RFSYN_CHP_GAIN , // 8 + RFSYN_EN_CHP_HIGAIN , // 9 + AGC_IF , // 10 + AGC_RF , // 11 + IF_DIVVAL , // 12 + IF_VCO_BIAS , // 13 + CHCAL_INT_MOD_IF , // 14 + CHCAL_FRAC_MOD_IF , // 15 + DRV_RES_SEL , // 16 + I_DRIVER , // 17 + EN_AAF , // 18 + EN_3P , // 19 + EN_AUX_3P , // 20 + SEL_AAF_BAND , // 21 + SEQ_ENCLK16_CLK_OUT , // 22 + SEQ_SEL4_16B , // 23 + XTAL_CAPSELECT , // 24 + IF_SEL_DBL , // 25 + RFSYN_R_DIV , // 26 + SEQ_EXTSYNTHCALIF , // 27 + SEQ_EXTDCCAL , // 28 + AGC_EN_RSSI , // 29 + RFA_ENCLKRFAGC , // 30 + RFA_RSSI_REFH , // 31 + RFA_RSSI_REF , // 32 + RFA_RSSI_REFL , // 33 + RFA_FLR , // 34 + RFA_CEIL , // 35 + SEQ_EXTIQFSMPULSE , // 36 + OVERRIDE_1 , // 37 + BB_INITSTATE_DLPF_TUNE, // 38 + TG_R_DIV, // 39 + EN_CHP_LIN_B , // 40 + + // + // Channel Change Control Names + // + DN_POLY = 51 , // 51 + DN_RFGAIN , // 52 + DN_CAP_RFLPF , // 53 + DN_EN_VHFUHFBAR , // 54 + DN_GAIN_ADJUST , // 55 + DN_IQTNBUF_AMP , // 56 + DN_IQTNGNBFBIAS_BST , // 57 + RFSYN_EN_OUTMUX , // 58 + RFSYN_SEL_VCO_OUT , // 59 + RFSYN_SEL_VCO_HI , // 60 + RFSYN_SEL_DIVM , // 61 + RFSYN_RF_DIV_BIAS , // 62 + DN_SEL_FREQ , // 63 + RFSYN_VCO_BIAS , // 64 + CHCAL_INT_MOD_RF , // 65 + CHCAL_FRAC_MOD_RF , // 66 + RFSYN_LPF_R , // 67 + CHCAL_EN_INT_RF , // 68 + TG_LO_DIVVAL , // 69 + TG_LO_SELVAL , // 70 + TG_DIV_VAL , // 71 + TG_VCO_BIAS , // 72 + SEQ_EXTPOWERUP , // 73 + OVERRIDE_2 , // 74 + OVERRIDE_3 , // 75 + OVERRIDE_4 , // 76 + SEQ_FSM_PULSE , // 77 + GPIO_4B, // 78 + GPIO_3B, // 79 + GPIO_4, // 80 + GPIO_3, // 81 + GPIO_1B, // 82 + DAC_A_ENABLE , // 83 + DAC_B_ENABLE , // 84 + DAC_DIN_A , // 85 + DAC_DIN_B , // 86 +#ifdef _MXL_PRODUCTION + RFSYN_EN_DIV, // 87 + RFSYN_DIVM, // 88 + DN_BYPASS_AGC_I2C // 89 +#endif + +} MXL5005_ControlName ; + + + + + + + + + + + + + + + +// MaxLinear source code - MXL5005_c.h + + + +// MXL5005.h : main header file for the MXL5005 DLL +// +//#pragma once + +//#include "Common.h" +#ifdef _MXL_INTERNAL +#include "Common_MXL.h" +#endif + +void InitTunerControls( Tuner_struct *Tuner) ; + +_u16 MXL_BlockInit( Tuner_struct *Tuner ) ; + +_u16 MXL5005_RegisterInit (Tuner_struct * Tuner) ; +_u16 MXL5005_ControlInit (Tuner_struct *Tuner) ; + +#ifdef _MXL_INTERNAL + _u16 MXL5005_MXLControlInit(Tuner_struct *Tuner) ; +#endif + +_u16 MXL5005_TunerConfig(Tuner_struct *Tuner, + _u8 Mode, // 0: Analog Mode ; 1: Digital Mode + _u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF + _u32 Bandwidth, // filter channel bandwidth (6, 7, 8) + _u32 IF_out, // Desired IF Out Frequency + _u32 Fxtal, // XTAL Frequency + _u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 + _u16 TOP, // 0: Dual AGC; Value: take over point + _u16 IF_OUT_LOAD,// IF Out Load Resistor (200 / 300 Ohms) + _u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out + _u8 DIV_OUT, // 4MHz or 16MHz + _u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable + _u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI + _u8 Mod_Type, // Modulation Type; + // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable + _u8 TF_Type // Tracking Filter Type + // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H + ) ; + +void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) ; +void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) ; +_u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) ; +_u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) ; +_u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) ; +_u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 ControlNum, _u32 value, _u16 controlGroup) ; +_u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 ControlNum, _u32 * value) ; +_u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 ControlNum, _u8 *RegNum, int * count) ; +void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal); +_u16 MXL_IFSynthInit( Tuner_struct * Tuner ) ; +_u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) ; +_u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) ; +_u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) ; +_u32 MXL_Ceiling( _u32 value, _u32 resolution ) ; +_u32 MXL_GetXtalInt(_u32 Xtal_Freq) ; + +_u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; +_u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; +_u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; +_u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; +_u16 MXL_GetMasterControl(_u8 *MasterReg, int state) ; + +#ifdef _MXL_PRODUCTION +_u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) ; +_u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) ; +#endif + + + + + + + + + + + + + + + + + + + + + + + +// The following context is MxL5005S tuner API source code + + + + + +/** + +@file + +@brief MxL5005S tuner module declaration + +One can manipulate MxL5005S tuner through MxL5005S module. +MxL5005S module is derived from tuner module. + +*/ + + + +#include "tuner_base.h" + + + + + +// Definitions + +// Constants +#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 +#define MXL5005S_LATCH_BYTE 0xfe + +// Register address, MSB, and LSB +#define MXL5005S_BB_IQSWAP_ADDR 59 +#define MXL5005S_BB_IQSWAP_MSB 0 +#define MXL5005S_BB_IQSWAP_LSB 0 + +#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53 +#define MXL5005S_BB_DLPF_BANDSEL_MSB 4 +#define MXL5005S_BB_DLPF_BANDSEL_LSB 3 + + + +// Standard modes +enum +{ + MXL5005S_STANDARD_DVBT, + MXL5005S_STANDARD_ATSC, +}; +#define MXL5005S_STANDARD_MODE_NUM 2 + + +// Bandwidth modes +enum +{ + MXL5005S_BANDWIDTH_6MHZ = 6000000, + MXL5005S_BANDWIDTH_7MHZ = 7000000, + MXL5005S_BANDWIDTH_8MHZ = 8000000, +}; +#define MXL5005S_BANDWIDTH_MODE_NUM 3 + + +// Top modes +enum +{ + MXL5005S_TOP_5P5 = 55, + MXL5005S_TOP_7P2 = 72, + MXL5005S_TOP_9P2 = 92, + MXL5005S_TOP_11P0 = 110, + MXL5005S_TOP_12P9 = 129, + MXL5005S_TOP_14P7 = 147, + MXL5005S_TOP_16P8 = 168, + MXL5005S_TOP_19P4 = 194, + MXL5005S_TOP_21P2 = 212, + MXL5005S_TOP_23P2 = 232, + MXL5005S_TOP_25P2 = 252, + MXL5005S_TOP_27P1 = 271, + MXL5005S_TOP_29P2 = 292, + MXL5005S_TOP_31P7 = 317, + MXL5005S_TOP_34P9 = 349, +}; + + +// IF output load +enum +{ + MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, + MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, +}; + + + + + +/// MxL5005S extra module alias +typedef struct MXL5005S_EXTRA_MODULE_TAG MXL5005S_EXTRA_MODULE; + + + + + +// MxL5005S register setting function pointer +typedef int +(*MXL5005S_FP_SET_REGS_WITH_TABLE)( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char *pAddrTable, + unsigned char *pByteTable, + int TableLen + ); + + +// MxL5005S register mask bits setting function pointer +typedef int +(*MXL5005S_FP_SET_REG_MASK_BITS)( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char RegAddr, + unsigned char Msb, + unsigned char Lsb, + const unsigned char WritingValue + ); + + +// MxL5005S spectrum mode setting function pointer +typedef int +(*MXL5005S_FP_SET_SPECTRUM_MODE)( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + int SpectrumMode + ); + + +// MxL5005S bandwidth setting function pointer +typedef int +(*MXL5005S_FP_SET_BANDWIDTH_HZ)( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long BandwidthHz + ); + + + + + +// MxL5005S extra module +struct MXL5005S_EXTRA_MODULE_TAG +{ + // MxL5005S function pointers + MXL5005S_FP_SET_REGS_WITH_TABLE SetRegsWithTable; + MXL5005S_FP_SET_REG_MASK_BITS SetRegMaskBits; + MXL5005S_FP_SET_SPECTRUM_MODE SetSpectrumMode; + MXL5005S_FP_SET_BANDWIDTH_HZ SetBandwidthHz; + + + // MxL5005S extra data + unsigned char AgcMasterByte; // Variable name in MaxLinear source code: AGC_MASTER_BYTE + + // MaxLinear defined struct + Tuner_struct MxlDefinedTunerStructure; +}; + + + + + +// Builder +void +BuildMxl5005sModule( + TUNER_MODULE **ppTuner, + TUNER_MODULE *pTunerModuleMemory, + MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory, + BASE_INTERFACE_MODULE *pBaseInterfaceModuleMemory, + I2C_BRIDGE_MODULE *pI2cBridgeModuleMemory, + unsigned char DeviceAddr, + int StandardMode + ); + + + + + +// Manipulaing functions +void +mxl5005s_SetDeviceAddr( + TUNER_MODULE *pTuner, + unsigned char DeviceAddr + ); + +void +mxl5005s_GetTunerType( + TUNER_MODULE *pTuner, + int *pTunerType + ); + +int +mxl5005s_GetDeviceAddr( + TUNER_MODULE *pTuner, + unsigned char *pDeviceAddr + ); + +int +mxl5005s_Initialize( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner + ); + +int +mxl5005s_SetRfFreqHz( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long RfFreqHz + ); + +int +mxl5005s_GetRfFreqHz( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long *pRfFreqHz + ); + + + + + +// Extra manipulaing functions +int +mxl5005s_SetRegsWithTable( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char *pAddrTable, + unsigned char *pByteTable, + int TableLen + ); + +int +mxl5005s_SetRegMaskBits( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char RegAddr, + unsigned char Msb, + unsigned char Lsb, + const unsigned char WritingValue + ); + +int +mxl5005s_SetSpectrumMode( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + int SpectrumMode + ); + +int +mxl5005s_SetBandwidthHz( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long BandwidthHz + ); + + + + + +// I2C birdge module demod argument setting +void +mxl5005s_SetI2cBridgeModuleTunerArg( + TUNER_MODULE *pTuner + ); + + + + + + + + + + + + + + + +#endif + -- cgit v1.2.3 From 2637d5b498b979b46a01690d22ecca1e5b79b903 Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 05:01:31 -0300 Subject: V4L/DVB (7864): mxl5005s: Cleanup #1 Cleanup #1 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 8 +- drivers/media/common/tuners/mxl5005s.h | 773 +++++++++++---------------------- 2 files changed, 260 insertions(+), 521 deletions(-) diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index a32475fa1472..3c4330614faf 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -35,13 +35,7 @@ MxL5005S module is derived from tuner module. */ -#include "tuner_mxl5005s.h" -#include "tuner_demod_io.h" - - - - - +#include "mxl5005s.h" /** diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h index 8542fc10a9bb..1944d9e94427 100644 --- a/drivers/media/common/tuners/mxl5005s.h +++ b/drivers/media/common/tuners/mxl5005s.h @@ -23,138 +23,104 @@ */ -#ifndef __TUNER_MXL5005S_H -#define __TUNER_MXL5005S_H +#ifndef __MXL5005S_H +#define __MXL5005S_H +/* + * The following context is source code provided by MaxLinear. + * MaxLinear source code - Common.h + */ - -// The following context is source code provided by MaxLinear. - - -// MaxLinear source code - Common.h - - - -//#pragma once - -typedef unsigned char _u8; // At least 1 Byte -typedef unsigned short _u16; // At least 2 Bytes -typedef signed short _s16; -typedef unsigned long _u32; // At least 4 Bytes -typedef void * HANDLE; // Pointer to memory location +typedef void *HANDLE; /* Pointer to memory location */ #define TUNER_REGS_NUM 104 #define INITCTRL_NUM 40 + #ifdef _MXL_PRODUCTION -#define CHCTRL_NUM 39 +#define CHCTRL_NUM 39 #else -#define CHCTRL_NUM 36 +#define CHCTRL_NUM 36 #endif -#define MXLCTRL_NUM 189 - -#define MASTER_CONTROL_ADDR 9 - +#define MXLCTRL_NUM 189 +#define MASTER_CONTROL_ADDR 9 - - -// Enumeration of AGC Mode +/* Enumeration of AGC Mode */ typedef enum { - MXL_DUAL_AGC = 0 , + MXL_DUAL_AGC = 0, MXL_SINGLE_AGC -} AGC_Mode ; +} AGC_Mode; -// -// Enumeration of Master Control Register State -// +/* Enumeration of Master Control Register State */ typedef enum { - MC_LOAD_START = 1 , - MC_POWER_DOWN , - MC_SYNTH_RESET , + MC_LOAD_START = 1, + MC_POWER_DOWN, + MC_SYNTH_RESET, MC_SEQ_OFF -} Master_Control_State ; +} Master_Control_State; -// -// Enumeration of MXL5005 Tuner Mode -// +/* Enumeration of MXL5005 Tuner Mode */ typedef enum { - MXL_ANALOG_MODE = 0 , + MXL_ANALOG_MODE = 0, MXL_DIGITAL_MODE +} Tuner_Mode; -} Tuner_Mode ; - -// -// Enumeration of MXL5005 Tuner IF Mode -// +/* Enumeration of MXL5005 Tuner IF Mode */ typedef enum { - MXL_ZERO_IF = 0 , + MXL_ZERO_IF = 0, MXL_LOW_IF +} Tuner_IF_Mode; -} Tuner_IF_Mode ; - -// -// Enumeration of MXL5005 Tuner Clock Out Mode -// +/* Enumeration of MXL5005 Tuner Clock Out Mode */ typedef enum { - MXL_CLOCK_OUT_DISABLE = 0 , + MXL_CLOCK_OUT_DISABLE = 0, MXL_CLOCK_OUT_ENABLE -} Tuner_Clock_Out ; +} Tuner_Clock_Out; -// -// Enumeration of MXL5005 Tuner Div Out Mode -// +/* Enumeration of MXL5005 Tuner Div Out Mode */ typedef enum { - MXL_DIV_OUT_1 = 0 , + MXL_DIV_OUT_1 = 0, MXL_DIV_OUT_4 -} Tuner_Div_Out ; +} Tuner_Div_Out; -// -// Enumeration of MXL5005 Tuner Pull-up Cap Select Mode -// +/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ typedef enum { - MXL_CAP_SEL_DISABLE = 0 , + MXL_CAP_SEL_DISABLE = 0, MXL_CAP_SEL_ENABLE -} Tuner_Cap_Select ; +} Tuner_Cap_Select; -// -// Enumeration of MXL5005 Tuner RSSI Mode -// +/* Enumeration of MXL5005 Tuner RSSI Mode */ typedef enum { - MXL_RSSI_DISABLE = 0 , + MXL_RSSI_DISABLE = 0, MXL_RSSI_ENABLE -} Tuner_RSSI ; +} Tuner_RSSI; -// -// Enumeration of MXL5005 Tuner Modulation Type -// +/* Enumeration of MXL5005 Tuner Modulation Type */ typedef enum { - MXL_DEFAULT_MODULATION = 0 , + MXL_DEFAULT_MODULATION = 0, MXL_DVBT, MXL_ATSC, MXL_QAM, MXL_ANALOG_CABLE, MXL_ANALOG_OTA +} Tuner_Modu_Type; -} Tuner_Modu_Type ; - -// -// Enumeration of MXL5005 Tuner Tracking Filter Type -// +/* Enumeration of MXL5005 Tuner Tracking Filter Type */ typedef enum { - MXL_TF_DEFAULT = 0 , + MXL_TF_DEFAULT = 0, MXL_TF_OFF, MXL_TF_C, MXL_TF_C_H, @@ -165,316 +131,233 @@ typedef enum MXL_TF_E_2, MXL_TF_E_NA, MXL_TF_G +} Tuner_TF_Type; - -} Tuner_TF_Type ; - - -// -// MXL5005 Tuner Register Struct -// +/* MXL5005 Tuner Register Struct */ typedef struct _TunerReg_struct { - _u16 Reg_Num ; // Tuner Register Address - _u16 Reg_Val ; // Current sofware programmed value waiting to be writen -} TunerReg_struct ; + u16 Reg_Num; /* Tuner Register Address */ + u16 Reg_Val; /* Current sofware programmed value waiting to be writen */ +} TunerReg_struct; -// -// MXL5005 Tuner Control Struct -// +/* MXL5005 Tuner Control Struct */ typedef struct _TunerControl_struct { - _u16 Ctrl_Num ; // Control Number - _u16 size ; // Number of bits to represent Value - _u16 addr[25] ; // Array of Tuner Register Address for each bit position - _u16 bit[25] ; // Array of bit position in Register Address for each bit position - _u16 val[25] ; // Binary representation of Value -} TunerControl_struct ; - -// -// MXL5005 Tuner Struct -// + u16 Ctrl_Num; /* Control Number */ + u16 size; /* Number of bits to represent Value */ + u16 addr[25]; /* Array of Tuner Register Address for each bit position */ + u16 bit[25]; /* Array of bit position in Register Address for each bit position */ + u16 val[25]; /* Binary representation of Value */ +} TunerControl_struct; + +/* MXL5005 Tuner Struct */ typedef struct _Tuner_struct { - _u8 Mode ; // 0: Analog Mode ; 1: Digital Mode - _u8 IF_Mode ; // for Analog Mode, 0: zero IF; 1: low IF - _u32 Chan_Bandwidth ; // filter channel bandwidth (6, 7, 8) - _u32 IF_OUT ; // Desired IF Out Frequency - _u16 IF_OUT_LOAD ; // IF Out Load Resistor (200/300 Ohms) - _u32 RF_IN ; // RF Input Frequency - _u32 Fxtal ; // XTAL Frequency - _u8 AGC_Mode ; // AGC Mode 0: Dual AGC; 1: Single AGC - _u16 TOP ; // Value: take over point - _u8 CLOCK_OUT ; // 0: turn off clock out; 1: turn on clock out - _u8 DIV_OUT ; // 4MHz or 16MHz - _u8 CAPSELECT ; // 0: disable On-Chip pulling cap; 1: enable - _u8 EN_RSSI ; // 0: disable RSSI; 1: enable RSSI - _u8 Mod_Type ; // Modulation Type; - // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable - _u8 TF_Type ; // Tracking Filter Type - // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H - - // Calculated Settings - _u32 RF_LO ; // Synth RF LO Frequency - _u32 IF_LO ; // Synth IF LO Frequency - _u32 TG_LO ; // Synth TG_LO Frequency - - // Pointers to ControlName Arrays - _u16 Init_Ctrl_Num ; // Number of INIT Control Names - TunerControl_struct Init_Ctrl[INITCTRL_NUM] ; // INIT Control Names Array Pointer - _u16 CH_Ctrl_Num ; // Number of CH Control Names - TunerControl_struct CH_Ctrl[CHCTRL_NUM] ; // CH Control Name Array Pointer - _u16 MXL_Ctrl_Num ; // Number of MXL Control Names - TunerControl_struct MXL_Ctrl[MXLCTRL_NUM] ; // MXL Control Name Array Pointer - - // Pointer to Tuner Register Array - _u16 TunerRegs_Num ; // Number of Tuner Registers - TunerReg_struct TunerRegs[TUNER_REGS_NUM] ; // Tuner Register Array Pointer -} Tuner_struct ; - - + u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ + u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */ + u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */ + u32 IF_OUT; /* Desired IF Out Frequency */ + u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */ + u32 RF_IN; /* RF Input Frequency */ + u32 Fxtal; /* XTAL Frequency */ + u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */ + u16 TOP; /* Value: take over point */ + u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */ + u8 DIV_OUT; /* 4MHz or 16MHz */ + u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */ + u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */ + u8 Mod_Type; /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 TF_Type; /* Tracking Filter Type */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + + /* Calculated Settings */ + u32 RF_LO; /* Synth RF LO Frequency */ + u32 IF_LO; /* Synth IF LO Frequency */ + u32 TG_LO; /* Synth TG_LO Frequency */ + + /* Pointers to ControlName Arrays */ + u16 Init_Ctrl_Num; /* Number of INIT Control Names */ + TunerControl_struct + Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ + + u16 CH_Ctrl_Num; /* Number of CH Control Names */ + TunerControl_struct + CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ + + u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ + TunerControl_struct + MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ + + /* Pointer to Tuner Register Array */ + u16 TunerRegs_Num; /* Number of Tuner Registers */ + TunerReg_struct + TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ + +} Tuner_struct; typedef enum { - // - // Initialization Control Names - // - DN_IQTN_AMP_CUT = 1 , // 1 - BB_MODE , // 2 - BB_BUF , // 3 - BB_BUF_OA , // 4 - BB_ALPF_BANDSELECT , // 5 - BB_IQSWAP , // 6 - BB_DLPF_BANDSEL , // 7 - RFSYN_CHP_GAIN , // 8 - RFSYN_EN_CHP_HIGAIN , // 9 - AGC_IF , // 10 - AGC_RF , // 11 - IF_DIVVAL , // 12 - IF_VCO_BIAS , // 13 - CHCAL_INT_MOD_IF , // 14 - CHCAL_FRAC_MOD_IF , // 15 - DRV_RES_SEL , // 16 - I_DRIVER , // 17 - EN_AAF , // 18 - EN_3P , // 19 - EN_AUX_3P , // 20 - SEL_AAF_BAND , // 21 - SEQ_ENCLK16_CLK_OUT , // 22 - SEQ_SEL4_16B , // 23 - XTAL_CAPSELECT , // 24 - IF_SEL_DBL , // 25 - RFSYN_R_DIV , // 26 - SEQ_EXTSYNTHCALIF , // 27 - SEQ_EXTDCCAL , // 28 - AGC_EN_RSSI , // 29 - RFA_ENCLKRFAGC , // 30 - RFA_RSSI_REFH , // 31 - RFA_RSSI_REF , // 32 - RFA_RSSI_REFL , // 33 - RFA_FLR , // 34 - RFA_CEIL , // 35 - SEQ_EXTIQFSMPULSE , // 36 - OVERRIDE_1 , // 37 - BB_INITSTATE_DLPF_TUNE, // 38 - TG_R_DIV, // 39 - EN_CHP_LIN_B , // 40 - - // - // Channel Change Control Names - // - DN_POLY = 51 , // 51 - DN_RFGAIN , // 52 - DN_CAP_RFLPF , // 53 - DN_EN_VHFUHFBAR , // 54 - DN_GAIN_ADJUST , // 55 - DN_IQTNBUF_AMP , // 56 - DN_IQTNGNBFBIAS_BST , // 57 - RFSYN_EN_OUTMUX , // 58 - RFSYN_SEL_VCO_OUT , // 59 - RFSYN_SEL_VCO_HI , // 60 - RFSYN_SEL_DIVM , // 61 - RFSYN_RF_DIV_BIAS , // 62 - DN_SEL_FREQ , // 63 - RFSYN_VCO_BIAS , // 64 - CHCAL_INT_MOD_RF , // 65 - CHCAL_FRAC_MOD_RF , // 66 - RFSYN_LPF_R , // 67 - CHCAL_EN_INT_RF , // 68 - TG_LO_DIVVAL , // 69 - TG_LO_SELVAL , // 70 - TG_DIV_VAL , // 71 - TG_VCO_BIAS , // 72 - SEQ_EXTPOWERUP , // 73 - OVERRIDE_2 , // 74 - OVERRIDE_3 , // 75 - OVERRIDE_4 , // 76 - SEQ_FSM_PULSE , // 77 - GPIO_4B, // 78 - GPIO_3B, // 79 - GPIO_4, // 80 - GPIO_3, // 81 - GPIO_1B, // 82 - DAC_A_ENABLE , // 83 - DAC_B_ENABLE , // 84 - DAC_DIN_A , // 85 - DAC_DIN_B , // 86 + /* Initialization Control Names */ + DN_IQTN_AMP_CUT = 1, /* 1 */ + BB_MODE, /* 2 */ + BB_BUF, /* 3 */ + BB_BUF_OA, /* 4 */ + BB_ALPF_BANDSELECT, /* 5 */ + BB_IQSWAP, /* 6 */ + BB_DLPF_BANDSEL, /* 7 */ + RFSYN_CHP_GAIN, /* 8 */ + RFSYN_EN_CHP_HIGAIN, /* 9 */ + AGC_IF, /* 10 */ + AGC_RF, /* 11 */ + IF_DIVVAL, /* 12 */ + IF_VCO_BIAS, /* 13 */ + CHCAL_INT_MOD_IF, /* 14 */ + CHCAL_FRAC_MOD_IF, /* 15 */ + DRV_RES_SEL, /* 16 */ + I_DRIVER, /* 17 */ + EN_AAF, /* 18 */ + EN_3P, /* 19 */ + EN_AUX_3P, /* 20 */ + SEL_AAF_BAND, /* 21 */ + SEQ_ENCLK16_CLK_OUT, /* 22 */ + SEQ_SEL4_16B, /* 23 */ + XTAL_CAPSELECT, /* 24 */ + IF_SEL_DBL, /* 25 */ + RFSYN_R_DIV, /* 26 */ + SEQ_EXTSYNTHCALIF, /* 27 */ + SEQ_EXTDCCAL, /* 28 */ + AGC_EN_RSSI, /* 29 */ + RFA_ENCLKRFAGC, /* 30 */ + RFA_RSSI_REFH, /* 31 */ + RFA_RSSI_REF, /* 32 */ + RFA_RSSI_REFL, /* 33 */ + RFA_FLR, /* 34 */ + RFA_CEIL, /* 35 */ + SEQ_EXTIQFSMPULSE, /* 36 */ + OVERRIDE_1, /* 37 */ + BB_INITSTATE_DLPF_TUNE, /* 38 */ + TG_R_DIV, /* 39 */ + EN_CHP_LIN_B, /* 40 */ + + /* Channel Change Control Names */ + DN_POLY = 51, /* 51 */ + DN_RFGAIN, /* 52 */ + DN_CAP_RFLPF, /* 53 */ + DN_EN_VHFUHFBAR, /* 54 */ + DN_GAIN_ADJUST, /* 55 */ + DN_IQTNBUF_AMP, /* 56 */ + DN_IQTNGNBFBIAS_BST, /* 57 */ + RFSYN_EN_OUTMUX, /* 58 */ + RFSYN_SEL_VCO_OUT, /* 59 */ + RFSYN_SEL_VCO_HI, /* 60 */ + RFSYN_SEL_DIVM, /* 61 */ + RFSYN_RF_DIV_BIAS, /* 62 */ + DN_SEL_FREQ, /* 63 */ + RFSYN_VCO_BIAS, /* 64 */ + CHCAL_INT_MOD_RF, /* 65 */ + CHCAL_FRAC_MOD_RF, /* 66 */ + RFSYN_LPF_R, /* 67 */ + CHCAL_EN_INT_RF, /* 68 */ + TG_LO_DIVVAL, /* 69 */ + TG_LO_SELVAL, /* 70 */ + TG_DIV_VAL, /* 71 */ + TG_VCO_BIAS, /* 72 */ + SEQ_EXTPOWERUP, /* 73 */ + OVERRIDE_2, /* 74 */ + OVERRIDE_3, /* 75 */ + OVERRIDE_4, /* 76 */ + SEQ_FSM_PULSE, /* 77 */ + GPIO_4B, /* 78 */ + GPIO_3B, /* 79 */ + GPIO_4, /* 80 */ + GPIO_3, /* 81 */ + GPIO_1B, /* 82 */ + DAC_A_ENABLE, /* 83 */ + DAC_B_ENABLE, /* 84 */ + DAC_DIN_A, /* 85 */ + DAC_DIN_B, /* 86 */ #ifdef _MXL_PRODUCTION - RFSYN_EN_DIV, // 87 - RFSYN_DIVM, // 88 - DN_BYPASS_AGC_I2C // 89 + RFSYN_EN_DIV, /* 87 */ + RFSYN_DIVM, /* 88 */ + DN_BYPASS_AGC_I2C /* 89 */ #endif +} MXL5005_ControlName; -} MXL5005_ControlName ; - - +/* End of common.h */ +/* + * The following context is source code provided by MaxLinear. + * MaxLinear source code - Common_MXL.h (?) + */ - - - - - - - - - - - -// MaxLinear source code - MXL5005_c.h - - - -// MXL5005.h : main header file for the MXL5005 DLL -// -//#pragma once - -//#include "Common.h" +void InitTunerControls(Tuner_struct *Tuner); +u16 MXL_BlockInit(Tuner_struct *Tuner); +u16 MXL5005_RegisterInit(Tuner_struct *Tuner); +u16 MXL5005_ControlInit(Tuner_struct *Tuner); #ifdef _MXL_INTERNAL -#include "Common_MXL.h" +u16 MXL5005_MXLControlInit(Tuner_struct *Tuner); #endif -void InitTunerControls( Tuner_struct *Tuner) ; - -_u16 MXL_BlockInit( Tuner_struct *Tuner ) ; - -_u16 MXL5005_RegisterInit (Tuner_struct * Tuner) ; -_u16 MXL5005_ControlInit (Tuner_struct *Tuner) ; - -#ifdef _MXL_INTERNAL - _u16 MXL5005_MXLControlInit(Tuner_struct *Tuner) ; -#endif +u16 MXL5005_TunerConfig(Tuner_struct *Tuner, + u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ + u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ + u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ + u32 IF_out, /* Desired IF Out Frequency */ + u32 Fxtal, /* XTAL Frequency */ + u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ + u16 TOP, /* 0: Dual AGC; Value: take over point */ + u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ + u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */ + u8 DIV_OUT, /* 4MHz or 16MHz */ + u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ + u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ + u8 Mod_Type, /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 TF_Type /* Tracking Filter Type */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + ); -_u16 MXL5005_TunerConfig(Tuner_struct *Tuner, - _u8 Mode, // 0: Analog Mode ; 1: Digital Mode - _u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF - _u32 Bandwidth, // filter channel bandwidth (6, 7, 8) - _u32 IF_out, // Desired IF Out Frequency - _u32 Fxtal, // XTAL Frequency - _u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 - _u16 TOP, // 0: Dual AGC; Value: take over point - _u16 IF_OUT_LOAD,// IF Out Load Resistor (200 / 300 Ohms) - _u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out - _u8 DIV_OUT, // 4MHz or 16MHz - _u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable - _u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI - _u8 Mod_Type, // Modulation Type; - // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable - _u8 TF_Type // Tracking Filter Type - // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H - ) ; - -void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) ; -void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) ; -_u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) ; -_u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) ; -_u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) ; -_u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 ControlNum, _u32 value, _u16 controlGroup) ; -_u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 ControlNum, _u32 * value) ; -_u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 ControlNum, _u8 *RegNum, int * count) ; -void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal); -_u16 MXL_IFSynthInit( Tuner_struct * Tuner ) ; -_u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) ; -_u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) ; -_u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) ; -_u32 MXL_Ceiling( _u32 value, _u32 resolution ) ; -_u32 MXL_GetXtalInt(_u32 Xtal_Freq) ; - -_u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; -_u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; -_u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; -_u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; -_u16 MXL_GetMasterControl(_u8 *MasterReg, int state) ; +void MXL_SynthIFLO_Calc(Tuner_struct *Tuner); +void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner); +u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal); +u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal); +u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value); +u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 ControlNum, u32 value, u16 controlGroup); +u16 MXL_ControlRead(Tuner_struct *Tuner, u16 ControlNum, u32 * value); +u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 ControlNum, u8 *RegNum, int *count); +void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal); +u16 MXL_IFSynthInit(Tuner_struct * Tuner ); +u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq); +u16 MXL_OverwriteICDefault(Tuner_struct *Tuner); +u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val); +u32 MXL_Ceiling(u32 value, u32 resolution); +u32 MXL_GetXtalInt(u32 Xtal_Freq); + +u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); +u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); +u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); +u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); +u16 MXL_GetMasterControl(u8 *MasterReg, int state); #ifdef _MXL_PRODUCTION -_u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) ; -_u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) ; +u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range); +u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis); #endif +/* Constants */ +#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 +#define MXL5005S_LATCH_BYTE 0xfe - - - - - - - - - - - - - - - - - - - - - -// The following context is MxL5005S tuner API source code - - - - - -/** - -@file - -@brief MxL5005S tuner module declaration - -One can manipulate MxL5005S tuner through MxL5005S module. -MxL5005S module is derived from tuner module. - -*/ - - - -#include "tuner_base.h" - - - - - -// Definitions - -// Constants -#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 -#define MXL5005S_LATCH_BYTE 0xfe - -// Register address, MSB, and LSB -#define MXL5005S_BB_IQSWAP_ADDR 59 -#define MXL5005S_BB_IQSWAP_MSB 0 -#define MXL5005S_BB_IQSWAP_LSB 0 +/* Register address, MSB, and LSB */ +#define MXL5005S_BB_IQSWAP_ADDR 59 +#define MXL5005S_BB_IQSWAP_MSB 0 +#define MXL5005S_BB_IQSWAP_LSB 0 #define MXL5005S_BB_DLPF_BANDSEL_ADDR 53 #define MXL5005S_BB_DLPF_BANDSEL_MSB 4 #define MXL5005S_BB_DLPF_BANDSEL_LSB 3 - - -// Standard modes +/* Standard modes */ enum { MXL5005S_STANDARD_DVBT, @@ -482,8 +365,7 @@ enum }; #define MXL5005S_STANDARD_MODE_NUM 2 - -// Bandwidth modes +/* Bandwidth modes */ enum { MXL5005S_BANDWIDTH_6MHZ = 6000000, @@ -492,8 +374,7 @@ enum }; #define MXL5005S_BANDWIDTH_MODE_NUM 3 - -// Top modes +/* Top modes */ enum { MXL5005S_TOP_5P5 = 55, @@ -513,29 +394,20 @@ enum MXL5005S_TOP_34P9 = 349, }; - -// IF output load +/* IF output load */ enum { MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, }; - - - - -/// MxL5005S extra module alias +/* MxL5005S extra module alias */ typedef struct MXL5005S_EXTRA_MODULE_TAG MXL5005S_EXTRA_MODULE; - - - - -// MxL5005S register setting function pointer +/* MxL5005S register setting function pointer */ typedef int (*MXL5005S_FP_SET_REGS_WITH_TABLE)( - struct dvb_usb_device* dib, + struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned char *pAddrTable, unsigned char *pByteTable, @@ -543,10 +415,10 @@ typedef int ); -// MxL5005S register mask bits setting function pointer +/* MxL5005S register mask bits setting function pointer */ typedef int (*MXL5005S_FP_SET_REG_MASK_BITS)( - struct dvb_usb_device* dib, + struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned char RegAddr, unsigned char Msb, @@ -554,17 +426,15 @@ typedef int const unsigned char WritingValue ); - -// MxL5005S spectrum mode setting function pointer +/* MxL5005S spectrum mode setting function pointer */ typedef int (*MXL5005S_FP_SET_SPECTRUM_MODE)( - struct dvb_usb_device* dib, + struct dvb_usb_device* dib, TUNER_MODULE *pTuner, int SpectrumMode ); - -// MxL5005S bandwidth setting function pointer +/* MxL5005S bandwidth setting function pointer */ typedef int (*MXL5005S_FP_SET_BANDWIDTH_HZ)( struct dvb_usb_device* dib, @@ -572,147 +442,22 @@ typedef int unsigned long BandwidthHz ); - - - - -// MxL5005S extra module +/* MxL5005S extra module */ struct MXL5005S_EXTRA_MODULE_TAG { - // MxL5005S function pointers + /* MxL5005S function pointers */ MXL5005S_FP_SET_REGS_WITH_TABLE SetRegsWithTable; MXL5005S_FP_SET_REG_MASK_BITS SetRegMaskBits; MXL5005S_FP_SET_SPECTRUM_MODE SetSpectrumMode; MXL5005S_FP_SET_BANDWIDTH_HZ SetBandwidthHz; + /* MxL5005S extra data */ + unsigned char AgcMasterByte; /* Variable name in MaxLinear source code: AGC_MASTER_BYTE */ - // MxL5005S extra data - unsigned char AgcMasterByte; // Variable name in MaxLinear source code: AGC_MASTER_BYTE - - // MaxLinear defined struct + /* MaxLinear defined struct */ Tuner_struct MxlDefinedTunerStructure; }; +/* End of common_mxl.h (?) */ - - - - -// Builder -void -BuildMxl5005sModule( - TUNER_MODULE **ppTuner, - TUNER_MODULE *pTunerModuleMemory, - MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory, - BASE_INTERFACE_MODULE *pBaseInterfaceModuleMemory, - I2C_BRIDGE_MODULE *pI2cBridgeModuleMemory, - unsigned char DeviceAddr, - int StandardMode - ); - - - - - -// Manipulaing functions -void -mxl5005s_SetDeviceAddr( - TUNER_MODULE *pTuner, - unsigned char DeviceAddr - ); - -void -mxl5005s_GetTunerType( - TUNER_MODULE *pTuner, - int *pTunerType - ); - -int -mxl5005s_GetDeviceAddr( - TUNER_MODULE *pTuner, - unsigned char *pDeviceAddr - ); - -int -mxl5005s_Initialize( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner - ); - -int -mxl5005s_SetRfFreqHz( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long RfFreqHz - ); - -int -mxl5005s_GetRfFreqHz( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long *pRfFreqHz - ); - - - - - -// Extra manipulaing functions -int -mxl5005s_SetRegsWithTable( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned char *pAddrTable, - unsigned char *pByteTable, - int TableLen - ); - -int -mxl5005s_SetRegMaskBits( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned char RegAddr, - unsigned char Msb, - unsigned char Lsb, - const unsigned char WritingValue - ); - -int -mxl5005s_SetSpectrumMode( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - int SpectrumMode - ); - -int -mxl5005s_SetBandwidthHz( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long BandwidthHz - ); - - - - - -// I2C birdge module demod argument setting -void -mxl5005s_SetI2cBridgeModuleTunerArg( - TUNER_MODULE *pTuner - ); - - - - - - - - - - - - - - - -#endif +#endif /* __MXL5005S_H */ -- cgit v1.2.3 From a8214d48e6d41f3a16c1023ca4f30bbd140ba756 Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 05:02:58 -0300 Subject: V4L/DVB (7865): mxl5005s: Cleanup #2 Cleanup #2 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 907 ++++++++++----------------------- 1 file changed, 271 insertions(+), 636 deletions(-) diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 3c4330614faf..2af14de737e9 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -22,71 +22,10 @@ * Revision: 080314 - original version */ - -/** - -@file - -@brief MxL5005S tuner module definition - -One can manipulate MxL5005S tuner through MxL5005S module. -MxL5005S module is derived from tuner module. - -*/ - - #include "mxl5005s.h" -/** - -@defgroup MXL5005S_TUNER_MODULE MxL5005S tuner module - -MxL5005S tuner module is drived from tuner base module. - -@see TUNER_BASE_MODULE - -*/ - - - - - -/** -@defgroup MXL5005S_MODULE_BUILDER MxL5005S module builder -@ingroup MXL5005S_TUNER_MODULE - -One should call MxL5005S module builder before using MxL5005S module. - -*/ -/// @{ - - - - - -/** - -@brief MxL5005S tuner module builder - -Use BuildMxl5005sModule() to build MxL5005S module, set all module function pointers with the corresponding functions, -and initialize module private variables. - - -@param [in] ppTuner Pointer to MxL5005S tuner module pointer -@param [in] pTunerModuleMemory Pointer to an allocated tuner module memory -@param [in] pMxl5005sExtraModuleMemory Pointer to an allocated MxL5005S extra module memory -@param [in] pI2cBridgeModuleMemory Pointer to an allocated I2C bridge module memory -@param [in] DeviceAddr MxL5005S I2C device address -@param [in] CrystalFreqHz MxL5005S crystal frequency in Hz - - -@note \n - -# One should call BuildMxl5005sModule() to build MxL5005S module before using it. - -*/ -void -BuildMxl5005sModule( +void BuildMxl5005sModule( TUNER_MODULE **ppTuner, TUNER_MODULE *pTunerModuleMemory, MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory, @@ -200,43 +139,7 @@ BuildMxl5005sModule( return; } - - - - -/// @} - - - - - -/** - -@defgroup MXL5005S_MANIPULATING_FUNCTIONS MxL5005S manipulating functions derived from tuner base module -@ingroup MXL5005S_TUNER_MODULE - -One can use the MxL5005S tuner module manipulating interface implemented by MxL5005S manipulating functions to -manipulate MxL5005S tuner. - -*/ -/// @{ - - - - - -/** - -@brief Set MxL5005S tuner I2C device address. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_SET_DEVICE_ADDR() function pointer with mxl5005s_SetDeviceAddr(). - -@see TUNER_FP_SET_DEVICE_ADDR - -*/ -void -mxl5005s_SetDeviceAddr( +void mxl5005s_SetDeviceAddr( TUNER_MODULE *pTuner, unsigned char DeviceAddr ) @@ -249,22 +152,7 @@ mxl5005s_SetDeviceAddr( return; } - - - - -/** - -@brief Get MxL5005S tuner type. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_GET_TUNER_TYPE() function pointer with mxl5005s_GetTunerType(). - -@see TUNER_FP_GET_TUNER_TYPE - -*/ -void -mxl5005s_GetTunerType( +void mxl5005s_GetTunerType( TUNER_MODULE *pTuner, int *pTunerType ) @@ -276,22 +164,7 @@ mxl5005s_GetTunerType( return; } - - - - -/** - -@brief Get MxL5005S tuner I2C device address. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_GET_DEVICE_ADDR() function pointer with mxl5005s_GetDeviceAddr(). - -@see TUNER_FP_GET_DEVICE_ADDR - -*/ -int -mxl5005s_GetDeviceAddr( +int mxl5005s_GetDeviceAddr( TUNER_MODULE *pTuner, unsigned char *pDeviceAddr ) @@ -310,22 +183,7 @@ error_status_get_tuner_i2c_device_addr: return FUNCTION_ERROR; } - - - - -/** - -@brief Initialize MxL5005S tuner. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_INITIALIZE() function pointer with mxl5005s_Initialize(). - -@see TUNER_FP_INITIALIZE - -*/ -int -mxl5005s_Initialize( +int mxl5005s_Initialize( struct dvb_usb_device* dib, TUNER_MODULE *pTuner ) @@ -337,16 +195,12 @@ mxl5005s_Initialize( unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - - // Get tuner extra module. pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - // Get AGC master byte AgcMasterByte = pExtra->AgcMasterByte; - // Initialize MxL5005S tuner according to MxL5005S tuner example code. // Tuner initialization stage 0 @@ -357,37 +211,19 @@ mxl5005s_Initialize( if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) goto error_status_set_tuner_registers; - // Tuner initialization stage 1 MXL_GetInitRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen); if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) goto error_status_set_tuner_registers; - return FUNCTION_SUCCESS; - error_status_set_tuner_registers: return FUNCTION_ERROR; } - - - - -/** - -@brief Set MxL5005S tuner RF frequency in Hz. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_SET_RF_FREQ_HZ() function pointer with mxl5005s_SetRfFreqHz(). - -@see TUNER_FP_SET_RF_FREQ_HZ - -*/ -int -mxl5005s_SetRfFreqHz( +int mxl5005s_SetRfFreqHz( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned long RfFreqHz @@ -404,8 +240,6 @@ mxl5005s_SetRfFreqHz( unsigned long IfDivval; unsigned char MasterControlByte; - - // Get tuner extra module and base interface module. pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; pBaseInterface = pTuner->pBaseInterface; @@ -476,22 +310,7 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } - - - - -/** - -@brief Get MxL5005S tuner RF frequency in Hz. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_GET_RF_FREQ_HZ() function pointer with mxl5005s_GetRfFreqHz(). - -@see TUNER_FP_GET_RF_FREQ_HZ - -*/ -int -mxl5005s_GetRfFreqHz( +int mxl5005s_GetRfFreqHz( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned long *pRfFreqHz @@ -511,18 +330,7 @@ error_status_get_tuner_rf_frequency: return FUNCTION_ERROR; } - - - - -/** - -@brief Set MxL5005S tuner registers with table. - -*/ -/* -int -mxl5005s_SetRegsWithTable( +int mxl5005s_SetRegsWithTable( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned char *pAddrTable, @@ -585,11 +393,8 @@ mxl5005s_SetRegsWithTable( error_status_set_tuner_registers: return FUNCTION_ERROR; } -*/ - -int -mxl5005s_SetRegsWithTable( +int mxl5005s_SetRegsWithTable( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned char *pAddrTable, @@ -618,17 +423,7 @@ mxl5005s_SetRegsWithTable( return FUNCTION_SUCCESS; } - - - - -/** - -@brief Set MxL5005S tuner register bits. - -*/ -int -mxl5005s_SetRegMaskBits( +int mxl5005s_SetRegMaskBits( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned char RegAddr, @@ -685,17 +480,7 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } - - - - -/** - -@brief Set MxL5005S tuner spectrum mode. - -*/ -int -mxl5005s_SetSpectrumMode( +int mxl5005s_SetSpectrumMode( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, int SpectrumMode @@ -730,17 +515,7 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } - - - - -/** - -@brief Set MxL5005S tuner bandwidth in Hz. - -*/ -int -mxl5005s_SetBandwidthHz( +int mxl5005s_SetBandwidthHz( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned long BandwidthHz @@ -777,48 +552,7 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } - - - - -/// @} - - - - - -/** - -@defgroup MXL5005S_DEPENDENCE MxL5005S dependence -@ingroup MXL5005S_TUNER_MODULE - -MxL5005S dependence is the related functions for MxL5005S tuner module interface. -One should not use MxL5005S dependence directly. - -*/ -/// @{ - - - - - -/** - -@brief Set I2C bridge module tuner arguments. - -MxL5005S builder will use mxl5005s_SetI2cBridgeModuleTunerArg() to set I2C bridge module tuner arguments. - - -@param [in] pTuner The tuner module pointer - - -@see BuildMxl5005sModule() - -*/ -void -mxl5005s_SetI2cBridgeModuleTunerArg( - TUNER_MODULE *pTuner - ) +void mxl5005s_SetI2cBridgeModuleTunerArg(TUNER_MODULE *pTuner) { I2C_BRIDGE_MODULE *pI2cBridge; @@ -833,51 +567,10 @@ mxl5005s_SetI2cBridgeModuleTunerArg( return; } - - - - - -/// @} - - - - - - - - - - - - - - - - - - - - - - // The following context is source code provided by MaxLinear. - - - - - // MaxLinear source code - MXL5005_Initialize.cpp - - - -//#ifdef _MXL_HEADER -//#include "stdafx.h" -//#endif -//#include "MXL5005_c.h" - -_u16 MXL5005_RegisterInit (Tuner_struct * Tuner) +u16 MXL5005_RegisterInit(Tuner_struct *Tuner) { Tuner->TunerRegs_Num = TUNER_REGS_NUM ; // Tuner->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; @@ -1197,7 +890,7 @@ _u16 MXL5005_RegisterInit (Tuner_struct * Tuner) return 0 ; } -_u16 MXL5005_ControlInit (Tuner_struct *Tuner) +u16 MXL5005_ControlInit(Tuner_struct *Tuner) { Tuner->Init_Ctrl_Num = INITCTRL_NUM ; @@ -2136,34 +1829,10 @@ _u16 MXL5005_ControlInit (Tuner_struct *Tuner) return 0 ; } - - - - - - - - - - - - - - // MaxLinear source code - MXL5005_c.cpp - - - // MXL5005.cpp : Defines the initialization routines for the DLL. // 2.6.12 - -//#ifdef _MXL_HEADER -//#include "stdafx.h" -//#endif -//#include "MXL5005_c.h" - - void InitTunerControls(Tuner_struct *Tuner) { MXL5005_RegisterInit(Tuner) ; @@ -2173,8 +1842,6 @@ void InitTunerControls(Tuner_struct *Tuner) #endif } - - /////////////////////////////////////////////////////////////////////////////// // // // Function: MXL_ConfigTuner // @@ -2184,7 +1851,7 @@ void InitTunerControls(Tuner_struct *Tuner) // // // // // Functions used: // -// MXL_SynthIFLO_Calc // +// MXL_SynthIFLO_Calc // // // // Inputs: // // Tuner_struct: structure defined at higher level // @@ -2193,12 +1860,12 @@ void InitTunerControls(Tuner_struct *Tuner) // Bandwidth: Filter Channel Bandwidth (in Hz) // // IF_out: Desired IF out Frequency (in Hz) // // Fxtal: Crystal Frerquency (in Hz) // -// TOP: 0: Dual AGC; Value: take over point // -// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // -// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // -// DIV_OUT: 0: Div-1; 1: Div-4 // -// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // -// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // +// TOP: 0: Dual AGC; Value: take over point // +// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // +// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // +// DIV_OUT: 0: Div-1; 1: Div-4 // +// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // +// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // // // // Outputs: // // Tuner // @@ -2208,26 +1875,26 @@ void InitTunerControls(Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL5005_TunerConfig(Tuner_struct *Tuner, - _u8 Mode, // 0: Analog Mode ; 1: Digital Mode - _u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF - _u32 Bandwidth, // filter channel bandwidth (6, 7, 8) - _u32 IF_out, // Desired IF Out Frequency - _u32 Fxtal, // XTAL Frequency - _u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 - _u16 TOP, // 0: Dual AGC; Value: take over point - _u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms) - _u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out - _u8 DIV_OUT, // 0: Div-1; 1: Div-4 - _u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable - _u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI - _u8 Mod_Type, // Modulation Type; - // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable - _u8 TF_Type // Tracking Filter - // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H +u16 MXL5005_TunerConfig(Tuner_struct *Tuner, + u8 Mode, // 0: Analog Mode ; 1: Digital Mode + u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF + u32 Bandwidth, // filter channel bandwidth (6, 7, 8) + u32 IF_out, // Desired IF Out Frequency + u32 Fxtal, // XTAL Frequency + u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 + u16 TOP, // 0: Dual AGC; Value: take over point + u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms) + u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out + u8 DIV_OUT, // 0: Div-1; 1: Div-4 + u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable + u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI + u8 Mod_Type, // Modulation Type; + // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable + u8 TF_Type // Tracking Filter + // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H ) { - _u16 status = 0 ; + u16 status = 0 ; Tuner->Mode = Mode ; Tuner->IF_Mode = IF_mode ; @@ -2244,15 +1911,10 @@ _u16 MXL5005_TunerConfig(Tuner_struct *Tuner, Tuner->Mod_Type = Mod_Type ; Tuner->TF_Type = TF_Type ; - - - // - // Initialize all the controls and registers - // + /* Initialize all the controls and registers */ InitTunerControls (Tuner) ; - // - // Synthesizer LO frequency calculation - // + + /* Synthesizer LO frequency calculation */ MXL_SynthIFLO_Calc( Tuner ) ; return status ; @@ -2366,9 +2028,9 @@ void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) +u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) { - _u16 status = 0 ; + u16 status = 0 ; status += MXL_ControlWrite(Tuner, OVERRIDE_1, 1) ; status += MXL_ControlWrite(Tuner, OVERRIDE_2, 1) ; @@ -2403,20 +2065,20 @@ _u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_BlockInit( Tuner_struct *Tuner ) +u16 MXL_BlockInit( Tuner_struct *Tuner ) { - _u16 status = 0 ; + u16 status = 0 ; status += MXL_OverwriteICDefault(Tuner) ; // // Downconverter Control - // Dig Ana + // Dig Ana status += MXL_ControlWrite(Tuner, DN_IQTN_AMP_CUT, Tuner->Mode ? 1 : 0) ; // // Filter Control - // Dig Ana + // Dig Ana status += MXL_ControlWrite(Tuner, BB_MODE, Tuner->Mode ? 0 : 1) ; status += MXL_ControlWrite(Tuner, BB_BUF, Tuner->Mode ? 3 : 2) ; status += MXL_ControlWrite(Tuner, BB_BUF_OA, Tuner->Mode ? 1 : 0) ; @@ -2439,7 +2101,7 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner ) } } else { // Analog Mode switch (Tuner->Chan_Bandwidth) { - case 8000000: // Low Zero + case 8000000: // Low Zero status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 0 : 3)) ; break ; case 7000000: @@ -2453,7 +2115,7 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner ) // // Charge Pump Control - // Dig Ana + // Dig Ana status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, Tuner->Mode ? 5 : 8) ; status += MXL_ControlWrite(Tuner, RFSYN_EN_CHP_HIGAIN, Tuner->Mode ? 1 : 1) ; status += MXL_ControlWrite(Tuner, EN_CHP_LIN_B, Tuner->Mode ? 0 : 0) ; @@ -2621,8 +2283,6 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner ) // Apply Default value to BB_INITSTATE_DLPF_TUNE // - - // // RSSI Control // @@ -2697,7 +2357,7 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner ) //Tuner->AGC_Mode = 1 ; // Single AGC Mode - // Disable RSSI //change here for v2.6.5 + // Disable RSSI //change here for v2.6.5 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; @@ -2787,13 +2447,13 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner ) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_IFSynthInit( Tuner_struct * Tuner ) +u16 MXL_IFSynthInit(Tuner_struct * Tuner) { - _u16 status = 0 ; + u16 status = 0 ; // Declare Local Variables - _u32 Fref = 0 ; - _u32 Kdbl, intModVal ; - _u32 fracModVal ; + u32 Fref = 0 ; + u32 Kdbl, intModVal ; + u32 fracModVal ; Kdbl = 2 ; if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) @@ -2999,8 +2659,6 @@ _u16 MXL_IFSynthInit( Tuner_struct * Tuner ) fracModVal = fracModVal / ((Tuner->Fxtal * Kdbl/2)/1000) ; status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_IF, fracModVal) ; - - return status ; } @@ -3008,14 +2666,14 @@ _u16 MXL_IFSynthInit( Tuner_struct * Tuner ) // // // Function: MXL_GetXtalInt // // // -// Description: return the Crystal Integration Value for // -// TG_VCO_BIAS calculation // +// Description: return the Crystal Integration Value for // +// TG_VCO_BIAS calculation // // // // Globals: // // NONE // // // // Functions used: // -// NONE // +// NONE // // // // Inputs: // // Crystal Frequency Value in Hz // @@ -3028,7 +2686,7 @@ _u16 MXL_IFSynthInit( Tuner_struct * Tuner ) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -_u32 MXL_GetXtalInt(_u32 Xtal_Freq) +u32 MXL_GetXtalInt(u32 Xtal_Freq) { if ((Xtal_Freq % 1000000) == 0) return (Xtal_Freq / 10000) ; @@ -3048,7 +2706,7 @@ _u32 MXL_GetXtalInt(_u32 Xtal_Freq) // Functions used: // // MXL_SynthRFTGLO_Calc // // MXL5005_ControlWrite // -// MXL_GetXtalInt // +// MXL_GetXtalInt // // // // Inputs: // // Tuner : Tuner structure defined at higher level // @@ -3060,20 +2718,20 @@ _u32 MXL_GetXtalInt(_u32 Xtal_Freq) // 0 : Successful // // 1 : Unsuccessful // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) +u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) { // Declare Local Variables - _u16 status = 0 ; - _u32 divider_val, E3, E4, E5, E5A ; - _u32 Fmax, Fmin, FmaxBin, FminBin ; - _u32 Kdbl_RF = 2; - _u32 tg_divval ; - _u32 tg_lo ; - _u32 Xtal_Int ; + u16 status = 0 ; + u32 divider_val, E3, E4, E5, E5A ; + u32 Fmax, Fmin, FmaxBin, FminBin ; + u32 Kdbl_RF = 2; + u32 tg_divval ; + u32 tg_lo ; + u32 Xtal_Int ; - _u32 Fref_TG; - _u32 Fvco; -// _u32 temp; + u32 Fref_TG; + u32 Fvco; +// u32 temp; Xtal_Int = MXL_GetXtalInt(Tuner->Fxtal ) ; @@ -3774,7 +3432,8 @@ _u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) { status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; - if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) // if UHF and terrestrial => Turn off Tracking Filter + // if UHF and terrestrial => Turn off Tracking Filter + if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) { // Turn off all the banks status += MXL_SetGPIO(Tuner, 3, 1) ; @@ -4089,7 +3748,8 @@ _u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) { status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) //if UHF and terrestrial=> Turn off Tracking Filter + // if UHF and terrestrial=> Turn off Tracking Filter + if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) { // Turn off all the banks status += MXL_SetGPIO(Tuner, 3, 1) ; @@ -4181,9 +3841,9 @@ _u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) return status ; } -_u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) +u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val) { - _u16 status = 0 ; + u16 status = 0 ; if (GPIO_Num == 1) status += MXL_ControlWrite(Tuner, GPIO_1B, GPIO_Val ? 0 : 1) ; @@ -4247,9 +3907,9 @@ _u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) // >0 : Value exceed maximum allowed for control number // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) +u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value) { - _u16 status = 0 ; + u16 status = 0 ; // Will write ALL Matching Control Name status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 1 ) ; // Write Matching INIT Control status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 2 ) ; // Write Matching CH Control @@ -4287,11 +3947,11 @@ _u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) // 2 : Control name not found // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u16 controlGroup) +u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 controlNum, u32 value, u16 controlGroup) { - _u16 i, j, k ; - _u32 highLimit ; - _u32 ctrlVal ; + u16 i, j, k ; + u32 highLimit ; + u32 ctrlVal ; if( controlGroup == 1) // Initial Control { @@ -4304,11 +3964,11 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u { for( j=0; jInit_Ctrl[i].size; j++) { - Tuner->Init_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + Tuner->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; // change the register map accordingly - MXL_RegWriteBit( Tuner, (_u8)(Tuner->Init_Ctrl[i].addr[j]), - (_u8)(Tuner->Init_Ctrl[i].bit[j]), - (_u8)((value>>j) & 0x01) ) ; + MXL_RegWriteBit( Tuner, (u8)(Tuner->Init_Ctrl[i].addr[j]), + (u8)(Tuner->Init_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ) ; } ctrlVal = 0 ; for(k=0; kInit_Ctrl[i].size; k++) @@ -4334,11 +3994,11 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u { for( j=0; jCH_Ctrl[i].size; j++) { - Tuner->CH_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + Tuner->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; // change the register map accordingly - MXL_RegWriteBit( Tuner, (_u8)(Tuner->CH_Ctrl[i].addr[j]), - (_u8)(Tuner->CH_Ctrl[i].bit[j]), - (_u8)((value>>j) & 0x01) ) ; + MXL_RegWriteBit( Tuner, (u8)(Tuner->CH_Ctrl[i].addr[j]), + (u8)(Tuner->CH_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ) ; } ctrlVal = 0 ; for(k=0; kCH_Ctrl[i].size; k++) @@ -4365,11 +4025,11 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u { for( j=0; jMXL_Ctrl[i].size; j++) { - Tuner->MXL_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + Tuner->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; // change the register map accordingly - MXL_RegWriteBit( Tuner, (_u8)(Tuner->MXL_Ctrl[i].addr[j]), - (_u8)(Tuner->MXL_Ctrl[i].bit[j]), - (_u8)((value>>j) & 0x01) ) ; + MXL_RegWriteBit( Tuner, (u8)(Tuner->MXL_Ctrl[i].addr[j]), + (u8)(Tuner->MXL_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ) ; } ctrlVal = 0 ; for(k=0; kMXL_Ctrl[i].size; k++) @@ -4413,7 +4073,7 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) +u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal) { int i ; @@ -4453,7 +4113,7 @@ _u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) +u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal) { int i ; @@ -4461,7 +4121,7 @@ _u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) { if (RegNum == Tuner->TunerRegs[i].Reg_Num ) { - *RegVal = (_u8)(Tuner->TunerRegs[i].Reg_Val) ; + *RegVal = (u8)(Tuner->TunerRegs[i].Reg_Val) ; return 0 ; } } @@ -4490,10 +4150,10 @@ _u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value) +u16 MXL_ControlRead(Tuner_struct *Tuner, u16 controlNum, u32 * value) { - _u32 ctrlVal ; - _u16 i, k ; + u32 ctrlVal ; + u16 i, k ; for (i=0; iInit_Ctrl_Num ; i++) { @@ -4539,7 +4199,7 @@ _u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value) // Function: MXL_ControlRegRead // // // // Description: Retrieve the register addresses and count related to a // -// a specific control name // +// a specific control name // // // // Globals: // // NONE // @@ -4550,24 +4210,24 @@ _u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value) // // // Outputs: // // RegNum : returned register address array // -// count : returned register count related to a control // +// count : returned register count related to a control // // // // Return: // // 0 : Successful read // // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * count) +u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 controlNum, u8 *RegNum, int * count) { - _u16 i, j, k ; - _u16 Count ; + u16 i, j, k ; + u16 Count ; for (i=0; iInit_Ctrl_Num ; i++) { if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) { Count = 1 ; - RegNum[0] = (_u8)(Tuner->Init_Ctrl[i].addr[0]) ; + RegNum[0] = (u8)(Tuner->Init_Ctrl[i].addr[0]) ; for(k=1; kInit_Ctrl[i].size; k++) { @@ -4576,7 +4236,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * if (Tuner->Init_Ctrl[i].addr[k] != RegNum[j]) { Count ++ ; - RegNum[Count-1] = (_u8)(Tuner->Init_Ctrl[i].addr[k]) ; + RegNum[Count-1] = (u8)(Tuner->Init_Ctrl[i].addr[k]) ; } } @@ -4590,7 +4250,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) { Count = 1 ; - RegNum[0] = (_u8)(Tuner->CH_Ctrl[i].addr[0]) ; + RegNum[0] = (u8)(Tuner->CH_Ctrl[i].addr[0]) ; for(k=1; kCH_Ctrl[i].size; k++) { @@ -4599,7 +4259,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * if (Tuner->CH_Ctrl[i].addr[k] != RegNum[j]) { Count ++ ; - RegNum[Count-1] = (_u8)(Tuner->CH_Ctrl[i].addr[k]) ; + RegNum[Count-1] = (u8)(Tuner->CH_Ctrl[i].addr[k]) ; } } } @@ -4613,7 +4273,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) { Count = 1 ; - RegNum[0] = (_u8)(Tuner->MXL_Ctrl[i].addr[0]) ; + RegNum[0] = (u8)(Tuner->MXL_Ctrl[i].addr[0]) ; for(k=1; kMXL_Ctrl[i].size; k++) { @@ -4622,7 +4282,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * if (Tuner->MXL_Ctrl[i].addr[k] != RegNum[j]) { Count ++ ; - RegNum[Count-1] = (_u8)Tuner->MXL_Ctrl[i].addr[k] ; + RegNum[Count-1] = (u8)Tuner->MXL_Ctrl[i].addr[k] ; } } } @@ -4648,8 +4308,8 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * // Inputs: // // Tuner_struct : structure defined at higher level // // address : register address // -// bit : register bit number // -// bitVal : register bit value // +// bit : register bit number // +// bitVal : register bit value // // // // Outputs: // // NONE // @@ -4659,16 +4319,16 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * // // /////////////////////////////////////////////////////////////////////////////// -void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal) +void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal) { int i ; // Declare Local Constants - const _u8 AND_MAP[8] = { + const u8 AND_MAP[8] = { 0xFE, 0xFD, 0xFB, 0xF7, 0xEF, 0xDF, 0xBF, 0x7F } ; - const _u8 OR_MAP[8] = { + const u8 OR_MAP[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 } ; @@ -4707,7 +4367,7 @@ void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal) // Computed value // // // /////////////////////////////////////////////////////////////////////////////// -_u32 MXL_Ceiling( _u32 value, _u32 resolution ) +u32 MXL_Ceiling( u32 value, u32 resolution ) { return (value/resolution + (value%resolution > 0 ? 1 : 0)) ; }; @@ -4715,15 +4375,15 @@ _u32 MXL_Ceiling( _u32 value, _u32 resolution ) // // Retrieve the Initialzation Registers // -_u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) { - _u16 status = 0; + u16 status = 0; int i ; - _u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, + u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, 76, 77, 91, 134, 135, 137, 147, 156, 166, 167, 168, 25 } ; - *count = sizeof(RegAddr) / sizeof(_u8) ; + *count = sizeof(RegAddr) / sizeof(u8) ; status += MXL_BlockInit(Tuner) ; @@ -4736,24 +4396,24 @@ _u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *co return status ; } -_u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) { - _u16 status = 0; + u16 status = 0; int i ; //add 77, 166, 167, 168 register for 2.6.12 #ifdef _MXL_PRODUCTION - _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, - 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; + u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, + 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; #else - _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, - 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; - //_u8 RegAddr[171]; + u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, + 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; + //u8 RegAddr[171]; //for (i=0; i<=170; i++) // RegAddr[i] = i; #endif - *count = sizeof(RegAddr) / sizeof(_u8) ; + *count = sizeof(RegAddr) / sizeof(u8) ; for (i=0 ; i< *count; i++) { @@ -4765,14 +4425,14 @@ _u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *coun } -_u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) { - _u16 status = 0 ; + u16 status = 0 ; int i ; - _u8 RegAddr[] = {43, 136} ; + u8 RegAddr[] = {43, 136} ; - *count = sizeof(RegAddr) / sizeof(_u8) ; + *count = sizeof(RegAddr) / sizeof(u8) ; for (i=0; i<*count; i++) { @@ -4783,14 +4443,14 @@ _u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, in } -_u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) { - _u16 status = 0 ; + u16 status = 0 ; int i ; - _u8 RegAddr[] = {138} ; + u8 RegAddr[] = {138} ; - *count = sizeof(RegAddr) / sizeof(_u8) ; + *count = sizeof(RegAddr) / sizeof(u8) ; for (i=0; i<*count; i++) { @@ -4801,7 +4461,7 @@ _u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int } -_u16 MXL_GetMasterControl(_u8 *MasterReg, int state) +u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) // Load_Start *MasterReg = 0xF3 ; @@ -4816,168 +4476,143 @@ _u16 MXL_GetMasterControl(_u8 *MasterReg, int state) } #ifdef _MXL_PRODUCTION -_u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) -{ - _u16 status = 0 ; - - if (VCO_Range == 1) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224 ) ; - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ; - } - if (Tuner->Mode == 1) // Digital Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ; - } - } - - if (VCO_Range == 2) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ; - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; - } - if (Tuner->Mode == 1) // Digital Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384 ) ; - } - } - - if (VCO_Range == 3) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ; - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ; - } - if (Tuner->Mode == 1) // Digital Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760 ) ; - } - } - - if (VCO_Range == 4) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; - } - if (Tuner->Mode == 1) // Digital Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992 ) ; - } - } - - return status ; -} - -_u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) +u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) { - _u16 status = 0 ; - - if (Hystersis == 1) - status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1) ; - - return status ; -} -#endif - - - - - - + u16 status = 0 ; + + if (VCO_Range == 1) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224); + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ; + } + if (Tuner->Mode == 1) // Digital Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ; + } + } + if (VCO_Range == 2) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41); + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); + } + if (Tuner->Mode == 1) // Digital Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384); + } + } + if (VCO_Range == 3) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670); + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670); + } + if (Tuner->Mode == 1) // Digital Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760); + } + } + if (VCO_Range == 4) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); + } + if (Tuner->Mode == 1) // Digital Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992); + } + } + return status; +} +u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) +{ + u16 status = 0; + if (Hystersis == 1) + status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1); + return status; +} +#endif -- cgit v1.2.3 From 3935c25484bc632b12c447e19c4eacbf5de5f7ae Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 05:45:44 -0300 Subject: V4L/DVB (7866): mxl5005s: Cleanup #3 Cleanup #3 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 5527 ++++++++++++++++---------------- drivers/media/common/tuners/mxl5005s.h | 165 - 2 files changed, 2677 insertions(+), 3015 deletions(-) diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 2af14de737e9..d8885484cfbd 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -24,164 +24,61 @@ #include "mxl5005s.h" - -void BuildMxl5005sModule( - TUNER_MODULE **ppTuner, - TUNER_MODULE *pTunerModuleMemory, - MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory, - BASE_INTERFACE_MODULE *pBaseInterfaceModuleMemory, - I2C_BRIDGE_MODULE *pI2cBridgeModuleMemory, - unsigned char DeviceAddr, - int StandardMode - ) -{ - MXL5005S_EXTRA_MODULE *pExtra; - - int MxlModMode; - int MxlIfMode; - unsigned long MxlBandwitdh; - unsigned long MxlIfFreqHz; - unsigned long MxlCrystalFreqHz; - int MxlAgcMode; - unsigned short MxlTop; - unsigned short MxlIfOutputLoad; - int MxlClockOut; - int MxlDivOut; - int MxlCapSel; - int MxlRssiOnOff; - unsigned char MxlStandard; - unsigned char MxlTfType; - - - - // Set tuner module pointer, tuner extra module pointer, and I2C bridge module pointer. - *ppTuner = pTunerModuleMemory; - (*ppTuner)->pExtra = pMxl5005sExtraModuleMemory; - (*ppTuner)->pBaseInterface = pBaseInterfaceModuleMemory; - (*ppTuner)->pI2cBridge = pI2cBridgeModuleMemory; - - // Get tuner extra module pointer. - pExtra = (MXL5005S_EXTRA_MODULE *)(*ppTuner)->pExtra; - - - // Set I2C bridge tuner arguments. - mxl5005s_SetI2cBridgeModuleTunerArg(*ppTuner); - - - // Set tuner module manipulating function pointers. - (*ppTuner)->SetDeviceAddr = mxl5005s_SetDeviceAddr; - - (*ppTuner)->GetTunerType = mxl5005s_GetTunerType; - (*ppTuner)->GetDeviceAddr = mxl5005s_GetDeviceAddr; - - (*ppTuner)->Initialize = mxl5005s_Initialize; - (*ppTuner)->SetRfFreqHz = mxl5005s_SetRfFreqHz; - (*ppTuner)->GetRfFreqHz = mxl5005s_GetRfFreqHz; - - - // Set tuner extra module manipulating function pointers. - pExtra->SetRegsWithTable = mxl5005s_SetRegsWithTable; - pExtra->SetRegMaskBits = mxl5005s_SetRegMaskBits; - pExtra->SetSpectrumMode = mxl5005s_SetSpectrumMode; - pExtra->SetBandwidthHz = mxl5005s_SetBandwidthHz; - - - // Initialize tuner parameter setting status. - (*ppTuner)->IsDeviceAddrSet = NO; - (*ppTuner)->IsRfFreqHzSet = NO; - - - // Set MxL5005S parameters. - MxlModMode = MXL_DIGITAL_MODE; - MxlIfMode = MXL_ZERO_IF; - MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; - MxlIfFreqHz = IF_FREQ_4570000HZ; - MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; - MxlAgcMode = MXL_SINGLE_AGC; - MxlTop = MXL5005S_TOP_25P2; - MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; - MxlClockOut = MXL_CLOCK_OUT_DISABLE; - MxlDivOut = MXL_DIV_OUT_4; - MxlCapSel = MXL_CAP_SEL_ENABLE; - MxlRssiOnOff = MXL_RSSI_ENABLE; - MxlTfType = MXL_TF_C_H; - - - // Set MxL5005S parameters according to standard mode - switch(StandardMode) - { - default: - case MXL5005S_STANDARD_DVBT: MxlStandard = MXL_DVBT; break; - case MXL5005S_STANDARD_ATSC: MxlStandard = MXL_ATSC; break; - } - - - // Set MxL5005S extra module. - pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; - - MXL5005_TunerConfig(&pExtra->MxlDefinedTunerStructure, (unsigned char)MxlModMode, (unsigned char)MxlIfMode, - MxlBandwitdh, MxlIfFreqHz, MxlCrystalFreqHz, (unsigned char)MxlAgcMode, MxlTop, MxlIfOutputLoad, - (unsigned char)MxlClockOut, (unsigned char)MxlDivOut, (unsigned char)MxlCapSel, (unsigned char)MxlRssiOnOff, - MxlStandard, MxlTfType); - - - - // Note: Need to set all module arguments before using module functions. - - - // Set tuner type. - (*ppTuner)->TunerType = TUNER_TYPE_MXL5005S; - - // Set tuner I2C device address. - (*ppTuner)->SetDeviceAddr(*ppTuner, DeviceAddr); - - - return; -} - -void mxl5005s_SetDeviceAddr( - TUNER_MODULE *pTuner, - unsigned char DeviceAddr - ) -{ - // Set tuner I2C device address. - pTuner->DeviceAddr = DeviceAddr; - pTuner->IsDeviceAddrSet = YES; - - - return; -} - -void mxl5005s_GetTunerType( - TUNER_MODULE *pTuner, - int *pTunerType - ) -{ - // Get tuner type from tuner module. - *pTunerType = pTuner->TunerType; - - - return; -} - -int mxl5005s_GetDeviceAddr( - TUNER_MODULE *pTuner, - unsigned char *pDeviceAddr - ) +/* MXL5005 Tuner Control Struct */ +typedef struct _TunerControl_struct { + u16 Ctrl_Num; /* Control Number */ + u16 size; /* Number of bits to represent Value */ + u16 addr[25]; /* Array of Tuner Register Address for each bit position */ + u16 bit[25]; /* Array of bit position in Register Address for each bit position */ + u16 val[25]; /* Binary representation of Value */ +} TunerControl_struct; + +/* MXL5005 Tuner Struct */ +struct mxl5005s_state { - // Get tuner I2C device address from tuner module. - if(pTuner->IsDeviceAddrSet != YES) - goto error_status_get_tuner_i2c_device_addr; - - *pDeviceAddr = pTuner->DeviceAddr; - - - return FUNCTION_SUCCESS; + u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ + u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */ + u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */ + u32 IF_OUT; /* Desired IF Out Frequency */ + u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */ + u32 RF_IN; /* RF Input Frequency */ + u32 Fxtal; /* XTAL Frequency */ + u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */ + u16 TOP; /* Value: take over point */ + u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */ + u8 DIV_OUT; /* 4MHz or 16MHz */ + u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */ + u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */ + u8 Mod_Type; /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 TF_Type; /* Tracking Filter Type */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + + /* Calculated Settings */ + u32 RF_LO; /* Synth RF LO Frequency */ + u32 IF_LO; /* Synth IF LO Frequency */ + u32 TG_LO; /* Synth TG_LO Frequency */ + + /* Pointers to ControlName Arrays */ + u16 Init_Ctrl_Num; /* Number of INIT Control Names */ + TunerControl_struct + Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ + + u16 CH_Ctrl_Num; /* Number of CH Control Names */ + TunerControl_struct + CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ + + u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ + TunerControl_struct + MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ + + /* Pointer to Tuner Register Array */ + u16 TunerRegs_Num; /* Number of Tuner Registers */ + TunerReg_struct + TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ +}; -error_status_get_tuner_i2c_device_addr: - return FUNCTION_ERROR; -} int mxl5005s_Initialize( struct dvb_usb_device* dib, @@ -310,24 +207,19 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } -int mxl5005s_GetRfFreqHz( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long *pRfFreqHz - ) +// DONE +int mxl5005s_GetRfFreqHz(struct dvb_frontend *fe, unsigned long *pRfFreqHz) { - // Get tuner RF frequency in Hz from tuner module. - if(pTuner->IsRfFreqHzSet != YES) - goto error_status_get_tuner_rf_frequency; - - *pRfFreqHz = pTuner->RfFreqHz; - - - return FUNCTION_SUCCESS; + struct mxl5005s_state *state = fe->demodulator_priv; + int ret = -1; + /* Get tuner RF frequency in Hz from tuner module. */ + if(state->IsRfFreqHzSet == YES) { + *pRfFreqHz = state->RfFreqHz; + ret = 0; + } -error_status_get_tuner_rf_frequency: - return FUNCTION_ERROR; + return -1; } int mxl5005s_SetRegsWithTable( @@ -394,14 +286,13 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } -int mxl5005s_SetRegsWithTable( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, +int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, unsigned char *pAddrTable, unsigned char *pByteTable, int TableLen ) { + struct mxl5005s_state *state = fe->demodulator_priv; int i; u8 end_two_bytes_buf[]={ 0 , 0 }; u8 tuner_addr=0x00; @@ -423,31 +314,21 @@ int mxl5005s_SetRegsWithTable( return FUNCTION_SUCCESS; } -int mxl5005s_SetRegMaskBits( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, +int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, unsigned char RegAddr, unsigned char Msb, unsigned char Lsb, const unsigned char WritingValue ) { - MXL5005S_EXTRA_MODULE *pExtra; - + struct mxl5005s_state *state = fe->demodulator_priv; int i; unsigned char Mask; unsigned char Shift; - unsigned char RegByte; - - - // Get tuner extra module. - pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - - - // Generate mask and shift according to MSB and LSB. + /* Generate mask and shift according to MSB and LSB. */ Mask = 0; for(i = Lsb; i < (unsigned char)(Msb + 1); i++) Mask |= 0x1 << i; @@ -455,20 +336,17 @@ int mxl5005s_SetRegMaskBits( Shift = Lsb; - // Get tuner register byte according to register adddress. + /* Get tuner register byte according to register adddress. */ MXL_RegRead(&pExtra->MxlDefinedTunerStructure, RegAddr, &RegByte); - - // Reserve register byte unmask bit with mask and inlay writing value into it. + /* Reserve register byte unmask bit with mask and inlay writing value into it. */ RegByte &= ~Mask; RegByte |= (WritingValue << Shift) & Mask; - - // Update tuner register byte table. + /* Update tuner register byte table. */ MXL_RegWrite(&pExtra->MxlDefinedTunerStructure, RegAddr, RegByte); - - // Write tuner register byte with writing byte. + /* Write tuner register byte with writing byte. */ if(pExtra->SetRegsWithTable( dib, pTuner, &RegAddr, &RegByte, LEN_1_BYTE) != FUNCTION_SUCCESS) goto error_status_set_tuner_registers; @@ -480,1350 +358,1321 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } -int mxl5005s_SetSpectrumMode( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - int SpectrumMode - ) +// DONE +int mxl5005s_SetSpectrumMode(struct dvb_frontend *fe, int SpectrumMode) { + struct mxl5005s_state *state = fe->demodulator_priv; static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] = { - // BB_IQSWAP - 0, // Normal spectrum - 1, // Inverse spectrum + /* BB_IQSWAP */ + 0, /* Normal spectrum */ + 1, /* Inverse spectrum */ }; - - MXL5005S_EXTRA_MODULE *pExtra; - - - - // Get tuner extra module. - pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - - - // Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. - if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_IQSWAP_ADDR, MXL5005S_BB_IQSWAP_MSB, - MXL5005S_BB_IQSWAP_LSB, BbIqswapTable[SpectrumMode]) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - + /* Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. */ + mxl5005s_SetRegMaskBits(fe, + MXL5005S_BB_IQSWAP_ADDR, + MXL5005S_BB_IQSWAP_MSB, + MXL5005S_BB_IQSWAP_LSB, + BbIqswapTable[SpectrumMode]); return FUNCTION_SUCCESS; - - -error_status_set_tuner_registers: - return FUNCTION_ERROR; } -int mxl5005s_SetBandwidthHz( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long BandwidthHz - ) +// DONE +int mxl5005s_SetBandwidthHz(struct dvb_frontend *fe, unsigned long BandwidthHz) { - MXL5005S_EXTRA_MODULE *pExtra; + struct mxl5005s_state *state = fe->demodulator_priv; unsigned char BbDlpfBandsel; - - - // Get tuner extra module. - pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - - - // Set BB_DLPF_BANDSEL according to bandwidth. + /* Set BB_DLPF_BANDSEL according to bandwidth. */ switch(BandwidthHz) { default: - case MXL5005S_BANDWIDTH_6MHZ: BbDlpfBandsel = 3; break; - case MXL5005S_BANDWIDTH_7MHZ: BbDlpfBandsel = 2; break; - case MXL5005S_BANDWIDTH_8MHZ: BbDlpfBandsel = 0; break; + case MXL5005S_BANDWIDTH_6MHZ: + BbDlpfBandsel = 3; + break; + case MXL5005S_BANDWIDTH_7MHZ: + BbDlpfBandsel = 2; + break; + case MXL5005S_BANDWIDTH_8MHZ: + BbDlpfBandsel = 0; + break; } if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB, - MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != FUNCTION_SUCCESS) + MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != 0) goto error_status_set_tuner_registers; - return FUNCTION_SUCCESS; + return 0; error_status_set_tuner_registers: - return FUNCTION_ERROR; -} - -void mxl5005s_SetI2cBridgeModuleTunerArg(TUNER_MODULE *pTuner) -{ - I2C_BRIDGE_MODULE *pI2cBridge; - - - - // Get I2C bridge module. - pI2cBridge = pTuner->pI2cBridge; - - // Set I2C bridge module tuner arguments. - pI2cBridge->pTunerDeviceAddr = &pTuner->DeviceAddr; - - - return; + return -1; } // The following context is source code provided by MaxLinear. // MaxLinear source code - MXL5005_Initialize.cpp -u16 MXL5005_RegisterInit(Tuner_struct *Tuner) +// DONE +u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { - Tuner->TunerRegs_Num = TUNER_REGS_NUM ; -// Tuner->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; + struct mxl5005s_state *state = fe->demodulator_priv; + state->TunerRegs_Num = TUNER_REGS_NUM ; +// state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; - Tuner->TunerRegs[0].Reg_Num = 9 ; - Tuner->TunerRegs[0].Reg_Val = 0x40 ; + state->TunerRegs[0].Reg_Num = 9 ; + state->TunerRegs[0].Reg_Val = 0x40 ; - Tuner->TunerRegs[1].Reg_Num = 11 ; - Tuner->TunerRegs[1].Reg_Val = 0x19 ; + state->TunerRegs[1].Reg_Num = 11 ; + state->TunerRegs[1].Reg_Val = 0x19 ; - Tuner->TunerRegs[2].Reg_Num = 12 ; - Tuner->TunerRegs[2].Reg_Val = 0x60 ; + state->TunerRegs[2].Reg_Num = 12 ; + state->TunerRegs[2].Reg_Val = 0x60 ; - Tuner->TunerRegs[3].Reg_Num = 13 ; - Tuner->TunerRegs[3].Reg_Val = 0x00 ; + state->TunerRegs[3].Reg_Num = 13 ; + state->TunerRegs[3].Reg_Val = 0x00 ; - Tuner->TunerRegs[4].Reg_Num = 14 ; - Tuner->TunerRegs[4].Reg_Val = 0x00 ; + state->TunerRegs[4].Reg_Num = 14 ; + state->TunerRegs[4].Reg_Val = 0x00 ; - Tuner->TunerRegs[5].Reg_Num = 15 ; - Tuner->TunerRegs[5].Reg_Val = 0xC0 ; + state->TunerRegs[5].Reg_Num = 15 ; + state->TunerRegs[5].Reg_Val = 0xC0 ; - Tuner->TunerRegs[6].Reg_Num = 16 ; - Tuner->TunerRegs[6].Reg_Val = 0x00 ; + state->TunerRegs[6].Reg_Num = 16 ; + state->TunerRegs[6].Reg_Val = 0x00 ; - Tuner->TunerRegs[7].Reg_Num = 17 ; - Tuner->TunerRegs[7].Reg_Val = 0x00 ; + state->TunerRegs[7].Reg_Num = 17 ; + state->TunerRegs[7].Reg_Val = 0x00 ; - Tuner->TunerRegs[8].Reg_Num = 18 ; - Tuner->TunerRegs[8].Reg_Val = 0x00 ; + state->TunerRegs[8].Reg_Num = 18 ; + state->TunerRegs[8].Reg_Val = 0x00 ; - Tuner->TunerRegs[9].Reg_Num = 19 ; - Tuner->TunerRegs[9].Reg_Val = 0x34 ; + state->TunerRegs[9].Reg_Num = 19 ; + state->TunerRegs[9].Reg_Val = 0x34 ; - Tuner->TunerRegs[10].Reg_Num = 21 ; - Tuner->TunerRegs[10].Reg_Val = 0x00 ; + state->TunerRegs[10].Reg_Num = 21 ; + state->TunerRegs[10].Reg_Val = 0x00 ; - Tuner->TunerRegs[11].Reg_Num = 22 ; - Tuner->TunerRegs[11].Reg_Val = 0x6B ; + state->TunerRegs[11].Reg_Num = 22 ; + state->TunerRegs[11].Reg_Val = 0x6B ; - Tuner->TunerRegs[12].Reg_Num = 23 ; - Tuner->TunerRegs[12].Reg_Val = 0x35 ; + state->TunerRegs[12].Reg_Num = 23 ; + state->TunerRegs[12].Reg_Val = 0x35 ; - Tuner->TunerRegs[13].Reg_Num = 24 ; - Tuner->TunerRegs[13].Reg_Val = 0x70 ; + state->TunerRegs[13].Reg_Num = 24 ; + state->TunerRegs[13].Reg_Val = 0x70 ; - Tuner->TunerRegs[14].Reg_Num = 25 ; - Tuner->TunerRegs[14].Reg_Val = 0x3E ; + state->TunerRegs[14].Reg_Num = 25 ; + state->TunerRegs[14].Reg_Val = 0x3E ; - Tuner->TunerRegs[15].Reg_Num = 26 ; - Tuner->TunerRegs[15].Reg_Val = 0x82 ; + state->TunerRegs[15].Reg_Num = 26 ; + state->TunerRegs[15].Reg_Val = 0x82 ; - Tuner->TunerRegs[16].Reg_Num = 31 ; - Tuner->TunerRegs[16].Reg_Val = 0x00 ; + state->TunerRegs[16].Reg_Num = 31 ; + state->TunerRegs[16].Reg_Val = 0x00 ; - Tuner->TunerRegs[17].Reg_Num = 32 ; - Tuner->TunerRegs[17].Reg_Val = 0x40 ; + state->TunerRegs[17].Reg_Num = 32 ; + state->TunerRegs[17].Reg_Val = 0x40 ; - Tuner->TunerRegs[18].Reg_Num = 33 ; - Tuner->TunerRegs[18].Reg_Val = 0x53 ; + state->TunerRegs[18].Reg_Num = 33 ; + state->TunerRegs[18].Reg_Val = 0x53 ; - Tuner->TunerRegs[19].Reg_Num = 34 ; - Tuner->TunerRegs[19].Reg_Val = 0x81 ; + state->TunerRegs[19].Reg_Num = 34 ; + state->TunerRegs[19].Reg_Val = 0x81 ; - Tuner->TunerRegs[20].Reg_Num = 35 ; - Tuner->TunerRegs[20].Reg_Val = 0xC9 ; + state->TunerRegs[20].Reg_Num = 35 ; + state->TunerRegs[20].Reg_Val = 0xC9 ; - Tuner->TunerRegs[21].Reg_Num = 36 ; - Tuner->TunerRegs[21].Reg_Val = 0x01 ; + state->TunerRegs[21].Reg_Num = 36 ; + state->TunerRegs[21].Reg_Val = 0x01 ; - Tuner->TunerRegs[22].Reg_Num = 37 ; - Tuner->TunerRegs[22].Reg_Val = 0x00 ; + state->TunerRegs[22].Reg_Num = 37 ; + state->TunerRegs[22].Reg_Val = 0x00 ; - Tuner->TunerRegs[23].Reg_Num = 41 ; - Tuner->TunerRegs[23].Reg_Val = 0x00 ; + state->TunerRegs[23].Reg_Num = 41 ; + state->TunerRegs[23].Reg_Val = 0x00 ; - Tuner->TunerRegs[24].Reg_Num = 42 ; - Tuner->TunerRegs[24].Reg_Val = 0xF8 ; + state->TunerRegs[24].Reg_Num = 42 ; + state->TunerRegs[24].Reg_Val = 0xF8 ; - Tuner->TunerRegs[25].Reg_Num = 43 ; - Tuner->TunerRegs[25].Reg_Val = 0x43 ; + state->TunerRegs[25].Reg_Num = 43 ; + state->TunerRegs[25].Reg_Val = 0x43 ; - Tuner->TunerRegs[26].Reg_Num = 44 ; - Tuner->TunerRegs[26].Reg_Val = 0x20 ; + state->TunerRegs[26].Reg_Num = 44 ; + state->TunerRegs[26].Reg_Val = 0x20 ; - Tuner->TunerRegs[27].Reg_Num = 45 ; - Tuner->TunerRegs[27].Reg_Val = 0x80 ; + state->TunerRegs[27].Reg_Num = 45 ; + state->TunerRegs[27].Reg_Val = 0x80 ; - Tuner->TunerRegs[28].Reg_Num = 46 ; - Tuner->TunerRegs[28].Reg_Val = 0x88 ; + state->TunerRegs[28].Reg_Num = 46 ; + state->TunerRegs[28].Reg_Val = 0x88 ; - Tuner->TunerRegs[29].Reg_Num = 47 ; - Tuner->TunerRegs[29].Reg_Val = 0x86 ; + state->TunerRegs[29].Reg_Num = 47 ; + state->TunerRegs[29].Reg_Val = 0x86 ; - Tuner->TunerRegs[30].Reg_Num = 48 ; - Tuner->TunerRegs[30].Reg_Val = 0x00 ; + state->TunerRegs[30].Reg_Num = 48 ; + state->TunerRegs[30].Reg_Val = 0x00 ; - Tuner->TunerRegs[31].Reg_Num = 49 ; - Tuner->TunerRegs[31].Reg_Val = 0x00 ; + state->TunerRegs[31].Reg_Num = 49 ; + state->TunerRegs[31].Reg_Val = 0x00 ; - Tuner->TunerRegs[32].Reg_Num = 53 ; - Tuner->TunerRegs[32].Reg_Val = 0x94 ; + state->TunerRegs[32].Reg_Num = 53 ; + state->TunerRegs[32].Reg_Val = 0x94 ; - Tuner->TunerRegs[33].Reg_Num = 54 ; - Tuner->TunerRegs[33].Reg_Val = 0xFA ; + state->TunerRegs[33].Reg_Num = 54 ; + state->TunerRegs[33].Reg_Val = 0xFA ; - Tuner->TunerRegs[34].Reg_Num = 55 ; - Tuner->TunerRegs[34].Reg_Val = 0x92 ; + state->TunerRegs[34].Reg_Num = 55 ; + state->TunerRegs[34].Reg_Val = 0x92 ; - Tuner->TunerRegs[35].Reg_Num = 56 ; - Tuner->TunerRegs[35].Reg_Val = 0x80 ; + state->TunerRegs[35].Reg_Num = 56 ; + state->TunerRegs[35].Reg_Val = 0x80 ; - Tuner->TunerRegs[36].Reg_Num = 57 ; - Tuner->TunerRegs[36].Reg_Val = 0x41 ; + state->TunerRegs[36].Reg_Num = 57 ; + state->TunerRegs[36].Reg_Val = 0x41 ; - Tuner->TunerRegs[37].Reg_Num = 58 ; - Tuner->TunerRegs[37].Reg_Val = 0xDB ; + state->TunerRegs[37].Reg_Num = 58 ; + state->TunerRegs[37].Reg_Val = 0xDB ; - Tuner->TunerRegs[38].Reg_Num = 59 ; - Tuner->TunerRegs[38].Reg_Val = 0x00 ; + state->TunerRegs[38].Reg_Num = 59 ; + state->TunerRegs[38].Reg_Val = 0x00 ; - Tuner->TunerRegs[39].Reg_Num = 60 ; - Tuner->TunerRegs[39].Reg_Val = 0x00 ; + state->TunerRegs[39].Reg_Num = 60 ; + state->TunerRegs[39].Reg_Val = 0x00 ; - Tuner->TunerRegs[40].Reg_Num = 61 ; - Tuner->TunerRegs[40].Reg_Val = 0x00 ; + state->TunerRegs[40].Reg_Num = 61 ; + state->TunerRegs[40].Reg_Val = 0x00 ; - Tuner->TunerRegs[41].Reg_Num = 62 ; - Tuner->TunerRegs[41].Reg_Val = 0x00 ; + state->TunerRegs[41].Reg_Num = 62 ; + state->TunerRegs[41].Reg_Val = 0x00 ; - Tuner->TunerRegs[42].Reg_Num = 65 ; - Tuner->TunerRegs[42].Reg_Val = 0xF8 ; + state->TunerRegs[42].Reg_Num = 65 ; + state->TunerRegs[42].Reg_Val = 0xF8 ; - Tuner->TunerRegs[43].Reg_Num = 66 ; - Tuner->TunerRegs[43].Reg_Val = 0xE4 ; + state->TunerRegs[43].Reg_Num = 66 ; + state->TunerRegs[43].Reg_Val = 0xE4 ; - Tuner->TunerRegs[44].Reg_Num = 67 ; - Tuner->TunerRegs[44].Reg_Val = 0x90 ; + state->TunerRegs[44].Reg_Num = 67 ; + state->TunerRegs[44].Reg_Val = 0x90 ; - Tuner->TunerRegs[45].Reg_Num = 68 ; - Tuner->TunerRegs[45].Reg_Val = 0xC0 ; + state->TunerRegs[45].Reg_Num = 68 ; + state->TunerRegs[45].Reg_Val = 0xC0 ; - Tuner->TunerRegs[46].Reg_Num = 69 ; - Tuner->TunerRegs[46].Reg_Val = 0x01 ; + state->TunerRegs[46].Reg_Num = 69 ; + state->TunerRegs[46].Reg_Val = 0x01 ; - Tuner->TunerRegs[47].Reg_Num = 70 ; - Tuner->TunerRegs[47].Reg_Val = 0x50 ; + state->TunerRegs[47].Reg_Num = 70 ; + state->TunerRegs[47].Reg_Val = 0x50 ; - Tuner->TunerRegs[48].Reg_Num = 71 ; - Tuner->TunerRegs[48].Reg_Val = 0x06 ; + state->TunerRegs[48].Reg_Num = 71 ; + state->TunerRegs[48].Reg_Val = 0x06 ; - Tuner->TunerRegs[49].Reg_Num = 72 ; - Tuner->TunerRegs[49].Reg_Val = 0x00 ; + state->TunerRegs[49].Reg_Num = 72 ; + state->TunerRegs[49].Reg_Val = 0x00 ; - Tuner->TunerRegs[50].Reg_Num = 73 ; - Tuner->TunerRegs[50].Reg_Val = 0x20 ; + state->TunerRegs[50].Reg_Num = 73 ; + state->TunerRegs[50].Reg_Val = 0x20 ; - Tuner->TunerRegs[51].Reg_Num = 76 ; - Tuner->TunerRegs[51].Reg_Val = 0xBB ; + state->TunerRegs[51].Reg_Num = 76 ; + state->TunerRegs[51].Reg_Val = 0xBB ; - Tuner->TunerRegs[52].Reg_Num = 77 ; - Tuner->TunerRegs[52].Reg_Val = 0x13 ; + state->TunerRegs[52].Reg_Num = 77 ; + state->TunerRegs[52].Reg_Val = 0x13 ; - Tuner->TunerRegs[53].Reg_Num = 81 ; - Tuner->TunerRegs[53].Reg_Val = 0x04 ; + state->TunerRegs[53].Reg_Num = 81 ; + state->TunerRegs[53].Reg_Val = 0x04 ; - Tuner->TunerRegs[54].Reg_Num = 82 ; - Tuner->TunerRegs[54].Reg_Val = 0x75 ; + state->TunerRegs[54].Reg_Num = 82 ; + state->TunerRegs[54].Reg_Val = 0x75 ; - Tuner->TunerRegs[55].Reg_Num = 83 ; - Tuner->TunerRegs[55].Reg_Val = 0x00 ; + state->TunerRegs[55].Reg_Num = 83 ; + state->TunerRegs[55].Reg_Val = 0x00 ; - Tuner->TunerRegs[56].Reg_Num = 84 ; - Tuner->TunerRegs[56].Reg_Val = 0x00 ; + state->TunerRegs[56].Reg_Num = 84 ; + state->TunerRegs[56].Reg_Val = 0x00 ; - Tuner->TunerRegs[57].Reg_Num = 85 ; - Tuner->TunerRegs[57].Reg_Val = 0x00 ; + state->TunerRegs[57].Reg_Num = 85 ; + state->TunerRegs[57].Reg_Val = 0x00 ; - Tuner->TunerRegs[58].Reg_Num = 91 ; - Tuner->TunerRegs[58].Reg_Val = 0x70 ; + state->TunerRegs[58].Reg_Num = 91 ; + state->TunerRegs[58].Reg_Val = 0x70 ; - Tuner->TunerRegs[59].Reg_Num = 92 ; - Tuner->TunerRegs[59].Reg_Val = 0x00 ; + state->TunerRegs[59].Reg_Num = 92 ; + state->TunerRegs[59].Reg_Val = 0x00 ; - Tuner->TunerRegs[60].Reg_Num = 93 ; - Tuner->TunerRegs[60].Reg_Val = 0x00 ; + state->TunerRegs[60].Reg_Num = 93 ; + state->TunerRegs[60].Reg_Val = 0x00 ; - Tuner->TunerRegs[61].Reg_Num = 94 ; - Tuner->TunerRegs[61].Reg_Val = 0x00 ; + state->TunerRegs[61].Reg_Num = 94 ; + state->TunerRegs[61].Reg_Val = 0x00 ; - Tuner->TunerRegs[62].Reg_Num = 95 ; - Tuner->TunerRegs[62].Reg_Val = 0x0C ; + state->TunerRegs[62].Reg_Num = 95 ; + state->TunerRegs[62].Reg_Val = 0x0C ; - Tuner->TunerRegs[63].Reg_Num = 96 ; - Tuner->TunerRegs[63].Reg_Val = 0x00 ; + state->TunerRegs[63].Reg_Num = 96 ; + state->TunerRegs[63].Reg_Val = 0x00 ; - Tuner->TunerRegs[64].Reg_Num = 97 ; - Tuner->TunerRegs[64].Reg_Val = 0x00 ; + state->TunerRegs[64].Reg_Num = 97 ; + state->TunerRegs[64].Reg_Val = 0x00 ; - Tuner->TunerRegs[65].Reg_Num = 98 ; - Tuner->TunerRegs[65].Reg_Val = 0xE2 ; + state->TunerRegs[65].Reg_Num = 98 ; + state->TunerRegs[65].Reg_Val = 0xE2 ; - Tuner->TunerRegs[66].Reg_Num = 99 ; - Tuner->TunerRegs[66].Reg_Val = 0x00 ; + state->TunerRegs[66].Reg_Num = 99 ; + state->TunerRegs[66].Reg_Val = 0x00 ; - Tuner->TunerRegs[67].Reg_Num = 100 ; - Tuner->TunerRegs[67].Reg_Val = 0x00 ; + state->TunerRegs[67].Reg_Num = 100 ; + state->TunerRegs[67].Reg_Val = 0x00 ; - Tuner->TunerRegs[68].Reg_Num = 101 ; - Tuner->TunerRegs[68].Reg_Val = 0x12 ; + state->TunerRegs[68].Reg_Num = 101 ; + state->TunerRegs[68].Reg_Val = 0x12 ; - Tuner->TunerRegs[69].Reg_Num = 102 ; - Tuner->TunerRegs[69].Reg_Val = 0x80 ; + state->TunerRegs[69].Reg_Num = 102 ; + state->TunerRegs[69].Reg_Val = 0x80 ; - Tuner->TunerRegs[70].Reg_Num = 103 ; - Tuner->TunerRegs[70].Reg_Val = 0x32 ; + state->TunerRegs[70].Reg_Num = 103 ; + state->TunerRegs[70].Reg_Val = 0x32 ; - Tuner->TunerRegs[71].Reg_Num = 104 ; - Tuner->TunerRegs[71].Reg_Val = 0xB4 ; + state->TunerRegs[71].Reg_Num = 104 ; + state->TunerRegs[71].Reg_Val = 0xB4 ; - Tuner->TunerRegs[72].Reg_Num = 105 ; - Tuner->TunerRegs[72].Reg_Val = 0x60 ; + state->TunerRegs[72].Reg_Num = 105 ; + state->TunerRegs[72].Reg_Val = 0x60 ; - Tuner->TunerRegs[73].Reg_Num = 106 ; - Tuner->TunerRegs[73].Reg_Val = 0x83 ; + state->TunerRegs[73].Reg_Num = 106 ; + state->TunerRegs[73].Reg_Val = 0x83 ; - Tuner->TunerRegs[74].Reg_Num = 107 ; - Tuner->TunerRegs[74].Reg_Val = 0x84 ; + state->TunerRegs[74].Reg_Num = 107 ; + state->TunerRegs[74].Reg_Val = 0x84 ; - Tuner->TunerRegs[75].Reg_Num = 108 ; - Tuner->TunerRegs[75].Reg_Val = 0x9C ; + state->TunerRegs[75].Reg_Num = 108 ; + state->TunerRegs[75].Reg_Val = 0x9C ; - Tuner->TunerRegs[76].Reg_Num = 109 ; - Tuner->TunerRegs[76].Reg_Val = 0x02 ; + state->TunerRegs[76].Reg_Num = 109 ; + state->TunerRegs[76].Reg_Val = 0x02 ; - Tuner->TunerRegs[77].Reg_Num = 110 ; - Tuner->TunerRegs[77].Reg_Val = 0x81 ; + state->TunerRegs[77].Reg_Num = 110 ; + state->TunerRegs[77].Reg_Val = 0x81 ; - Tuner->TunerRegs[78].Reg_Num = 111 ; - Tuner->TunerRegs[78].Reg_Val = 0xC0 ; + state->TunerRegs[78].Reg_Num = 111 ; + state->TunerRegs[78].Reg_Val = 0xC0 ; - Tuner->TunerRegs[79].Reg_Num = 112 ; - Tuner->TunerRegs[79].Reg_Val = 0x10 ; + state->TunerRegs[79].Reg_Num = 112 ; + state->TunerRegs[79].Reg_Val = 0x10 ; - Tuner->TunerRegs[80].Reg_Num = 131 ; - Tuner->TunerRegs[80].Reg_Val = 0x8A ; + state->TunerRegs[80].Reg_Num = 131 ; + state->TunerRegs[80].Reg_Val = 0x8A ; - Tuner->TunerRegs[81].Reg_Num = 132 ; - Tuner->TunerRegs[81].Reg_Val = 0x10 ; + state->TunerRegs[81].Reg_Num = 132 ; + state->TunerRegs[81].Reg_Val = 0x10 ; - Tuner->TunerRegs[82].Reg_Num = 133 ; - Tuner->TunerRegs[82].Reg_Val = 0x24 ; + state->TunerRegs[82].Reg_Num = 133 ; + state->TunerRegs[82].Reg_Val = 0x24 ; - Tuner->TunerRegs[83].Reg_Num = 134 ; - Tuner->TunerRegs[83].Reg_Val = 0x00 ; + state->TunerRegs[83].Reg_Num = 134 ; + state->TunerRegs[83].Reg_Val = 0x00 ; - Tuner->TunerRegs[84].Reg_Num = 135 ; - Tuner->TunerRegs[84].Reg_Val = 0x00 ; + state->TunerRegs[84].Reg_Num = 135 ; + state->TunerRegs[84].Reg_Val = 0x00 ; - Tuner->TunerRegs[85].Reg_Num = 136 ; - Tuner->TunerRegs[85].Reg_Val = 0x7E ; + state->TunerRegs[85].Reg_Num = 136 ; + state->TunerRegs[85].Reg_Val = 0x7E ; - Tuner->TunerRegs[86].Reg_Num = 137 ; - Tuner->TunerRegs[86].Reg_Val = 0x40 ; + state->TunerRegs[86].Reg_Num = 137 ; + state->TunerRegs[86].Reg_Val = 0x40 ; - Tuner->TunerRegs[87].Reg_Num = 138 ; - Tuner->TunerRegs[87].Reg_Val = 0x38 ; + state->TunerRegs[87].Reg_Num = 138 ; + state->TunerRegs[87].Reg_Val = 0x38 ; - Tuner->TunerRegs[88].Reg_Num = 146 ; - Tuner->TunerRegs[88].Reg_Val = 0xF6 ; + state->TunerRegs[88].Reg_Num = 146 ; + state->TunerRegs[88].Reg_Val = 0xF6 ; - Tuner->TunerRegs[89].Reg_Num = 147 ; - Tuner->TunerRegs[89].Reg_Val = 0x1A ; + state->TunerRegs[89].Reg_Num = 147 ; + state->TunerRegs[89].Reg_Val = 0x1A ; - Tuner->TunerRegs[90].Reg_Num = 148 ; - Tuner->TunerRegs[90].Reg_Val = 0x62 ; + state->TunerRegs[90].Reg_Num = 148 ; + state->TunerRegs[90].Reg_Val = 0x62 ; - Tuner->TunerRegs[91].Reg_Num = 149 ; - Tuner->TunerRegs[91].Reg_Val = 0x33 ; + state->TunerRegs[91].Reg_Num = 149 ; + state->TunerRegs[91].Reg_Val = 0x33 ; - Tuner->TunerRegs[92].Reg_Num = 150 ; - Tuner->TunerRegs[92].Reg_Val = 0x80 ; + state->TunerRegs[92].Reg_Num = 150 ; + state->TunerRegs[92].Reg_Val = 0x80 ; - Tuner->TunerRegs[93].Reg_Num = 156 ; - Tuner->TunerRegs[93].Reg_Val = 0x56 ; + state->TunerRegs[93].Reg_Num = 156 ; + state->TunerRegs[93].Reg_Val = 0x56 ; - Tuner->TunerRegs[94].Reg_Num = 157 ; - Tuner->TunerRegs[94].Reg_Val = 0x17 ; + state->TunerRegs[94].Reg_Num = 157 ; + state->TunerRegs[94].Reg_Val = 0x17 ; - Tuner->TunerRegs[95].Reg_Num = 158 ; - Tuner->TunerRegs[95].Reg_Val = 0xA9 ; + state->TunerRegs[95].Reg_Num = 158 ; + state->TunerRegs[95].Reg_Val = 0xA9 ; - Tuner->TunerRegs[96].Reg_Num = 159 ; - Tuner->TunerRegs[96].Reg_Val = 0x00 ; + state->TunerRegs[96].Reg_Num = 159 ; + state->TunerRegs[96].Reg_Val = 0x00 ; - Tuner->TunerRegs[97].Reg_Num = 160 ; - Tuner->TunerRegs[97].Reg_Val = 0x00 ; + state->TunerRegs[97].Reg_Num = 160 ; + state->TunerRegs[97].Reg_Val = 0x00 ; - Tuner->TunerRegs[98].Reg_Num = 161 ; - Tuner->TunerRegs[98].Reg_Val = 0x00 ; + state->TunerRegs[98].Reg_Num = 161 ; + state->TunerRegs[98].Reg_Val = 0x00 ; - Tuner->TunerRegs[99].Reg_Num = 162 ; - Tuner->TunerRegs[99].Reg_Val = 0x40 ; + state->TunerRegs[99].Reg_Num = 162 ; + state->TunerRegs[99].Reg_Val = 0x40 ; - Tuner->TunerRegs[100].Reg_Num = 166 ; - Tuner->TunerRegs[100].Reg_Val = 0xAE ; + state->TunerRegs[100].Reg_Num = 166 ; + state->TunerRegs[100].Reg_Val = 0xAE ; - Tuner->TunerRegs[101].Reg_Num = 167 ; - Tuner->TunerRegs[101].Reg_Val = 0x1B ; + state->TunerRegs[101].Reg_Num = 167 ; + state->TunerRegs[101].Reg_Val = 0x1B ; - Tuner->TunerRegs[102].Reg_Num = 168 ; - Tuner->TunerRegs[102].Reg_Val = 0xF2 ; + state->TunerRegs[102].Reg_Num = 168 ; + state->TunerRegs[102].Reg_Val = 0xF2 ; - Tuner->TunerRegs[103].Reg_Num = 195 ; - Tuner->TunerRegs[103].Reg_Val = 0x00 ; + state->TunerRegs[103].Reg_Num = 195 ; + state->TunerRegs[103].Reg_Val = 0x00 ; return 0 ; } -u16 MXL5005_ControlInit(Tuner_struct *Tuner) +// DONE +u16 MXL5005_ControlInit(struct dvb_frontend *fe) { - Tuner->Init_Ctrl_Num = INITCTRL_NUM ; - - Tuner->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; - Tuner->Init_Ctrl[0].size = 1 ; - Tuner->Init_Ctrl[0].addr[0] = 73; - Tuner->Init_Ctrl[0].bit[0] = 7; - Tuner->Init_Ctrl[0].val[0] = 0; - - Tuner->Init_Ctrl[1].Ctrl_Num = BB_MODE ; - Tuner->Init_Ctrl[1].size = 1 ; - Tuner->Init_Ctrl[1].addr[0] = 53; - Tuner->Init_Ctrl[1].bit[0] = 2; - Tuner->Init_Ctrl[1].val[0] = 1; - - Tuner->Init_Ctrl[2].Ctrl_Num = BB_BUF ; - Tuner->Init_Ctrl[2].size = 2 ; - Tuner->Init_Ctrl[2].addr[0] = 53; - Tuner->Init_Ctrl[2].bit[0] = 1; - Tuner->Init_Ctrl[2].val[0] = 0; - Tuner->Init_Ctrl[2].addr[1] = 57; - Tuner->Init_Ctrl[2].bit[1] = 0; - Tuner->Init_Ctrl[2].val[1] = 1; - - Tuner->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ; - Tuner->Init_Ctrl[3].size = 1 ; - Tuner->Init_Ctrl[3].addr[0] = 53; - Tuner->Init_Ctrl[3].bit[0] = 0; - Tuner->Init_Ctrl[3].val[0] = 0; - - Tuner->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ; - Tuner->Init_Ctrl[4].size = 3 ; - Tuner->Init_Ctrl[4].addr[0] = 53; - Tuner->Init_Ctrl[4].bit[0] = 5; - Tuner->Init_Ctrl[4].val[0] = 0; - Tuner->Init_Ctrl[4].addr[1] = 53; - Tuner->Init_Ctrl[4].bit[1] = 6; - Tuner->Init_Ctrl[4].val[1] = 0; - Tuner->Init_Ctrl[4].addr[2] = 53; - Tuner->Init_Ctrl[4].bit[2] = 7; - Tuner->Init_Ctrl[4].val[2] = 1; - - Tuner->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ; - Tuner->Init_Ctrl[5].size = 1 ; - Tuner->Init_Ctrl[5].addr[0] = 59; - Tuner->Init_Ctrl[5].bit[0] = 0; - Tuner->Init_Ctrl[5].val[0] = 0; - - Tuner->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ; - Tuner->Init_Ctrl[6].size = 2 ; - Tuner->Init_Ctrl[6].addr[0] = 53; - Tuner->Init_Ctrl[6].bit[0] = 3; - Tuner->Init_Ctrl[6].val[0] = 0; - Tuner->Init_Ctrl[6].addr[1] = 53; - Tuner->Init_Ctrl[6].bit[1] = 4; - Tuner->Init_Ctrl[6].val[1] = 1; - - Tuner->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ; - Tuner->Init_Ctrl[7].size = 4 ; - Tuner->Init_Ctrl[7].addr[0] = 22; - Tuner->Init_Ctrl[7].bit[0] = 4; - Tuner->Init_Ctrl[7].val[0] = 0; - Tuner->Init_Ctrl[7].addr[1] = 22; - Tuner->Init_Ctrl[7].bit[1] = 5; - Tuner->Init_Ctrl[7].val[1] = 1; - Tuner->Init_Ctrl[7].addr[2] = 22; - Tuner->Init_Ctrl[7].bit[2] = 6; - Tuner->Init_Ctrl[7].val[2] = 1; - Tuner->Init_Ctrl[7].addr[3] = 22; - Tuner->Init_Ctrl[7].bit[3] = 7; - Tuner->Init_Ctrl[7].val[3] = 0; - - Tuner->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ; - Tuner->Init_Ctrl[8].size = 1 ; - Tuner->Init_Ctrl[8].addr[0] = 22; - Tuner->Init_Ctrl[8].bit[0] = 2; - Tuner->Init_Ctrl[8].val[0] = 0; - - Tuner->Init_Ctrl[9].Ctrl_Num = AGC_IF ; - Tuner->Init_Ctrl[9].size = 4 ; - Tuner->Init_Ctrl[9].addr[0] = 76; - Tuner->Init_Ctrl[9].bit[0] = 0; - Tuner->Init_Ctrl[9].val[0] = 1; - Tuner->Init_Ctrl[9].addr[1] = 76; - Tuner->Init_Ctrl[9].bit[1] = 1; - Tuner->Init_Ctrl[9].val[1] = 1; - Tuner->Init_Ctrl[9].addr[2] = 76; - Tuner->Init_Ctrl[9].bit[2] = 2; - Tuner->Init_Ctrl[9].val[2] = 0; - Tuner->Init_Ctrl[9].addr[3] = 76; - Tuner->Init_Ctrl[9].bit[3] = 3; - Tuner->Init_Ctrl[9].val[3] = 1; - - Tuner->Init_Ctrl[10].Ctrl_Num = AGC_RF ; - Tuner->Init_Ctrl[10].size = 4 ; - Tuner->Init_Ctrl[10].addr[0] = 76; - Tuner->Init_Ctrl[10].bit[0] = 4; - Tuner->Init_Ctrl[10].val[0] = 1; - Tuner->Init_Ctrl[10].addr[1] = 76; - Tuner->Init_Ctrl[10].bit[1] = 5; - Tuner->Init_Ctrl[10].val[1] = 1; - Tuner->Init_Ctrl[10].addr[2] = 76; - Tuner->Init_Ctrl[10].bit[2] = 6; - Tuner->Init_Ctrl[10].val[2] = 0; - Tuner->Init_Ctrl[10].addr[3] = 76; - Tuner->Init_Ctrl[10].bit[3] = 7; - Tuner->Init_Ctrl[10].val[3] = 1; - - Tuner->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ; - Tuner->Init_Ctrl[11].size = 5 ; - Tuner->Init_Ctrl[11].addr[0] = 43; - Tuner->Init_Ctrl[11].bit[0] = 3; - Tuner->Init_Ctrl[11].val[0] = 0; - Tuner->Init_Ctrl[11].addr[1] = 43; - Tuner->Init_Ctrl[11].bit[1] = 4; - Tuner->Init_Ctrl[11].val[1] = 0; - Tuner->Init_Ctrl[11].addr[2] = 43; - Tuner->Init_Ctrl[11].bit[2] = 5; - Tuner->Init_Ctrl[11].val[2] = 0; - Tuner->Init_Ctrl[11].addr[3] = 43; - Tuner->Init_Ctrl[11].bit[3] = 6; - Tuner->Init_Ctrl[11].val[3] = 1; - Tuner->Init_Ctrl[11].addr[4] = 43; - Tuner->Init_Ctrl[11].bit[4] = 7; - Tuner->Init_Ctrl[11].val[4] = 0; - - Tuner->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ; - Tuner->Init_Ctrl[12].size = 6 ; - Tuner->Init_Ctrl[12].addr[0] = 44; - Tuner->Init_Ctrl[12].bit[0] = 2; - Tuner->Init_Ctrl[12].val[0] = 0; - Tuner->Init_Ctrl[12].addr[1] = 44; - Tuner->Init_Ctrl[12].bit[1] = 3; - Tuner->Init_Ctrl[12].val[1] = 0; - Tuner->Init_Ctrl[12].addr[2] = 44; - Tuner->Init_Ctrl[12].bit[2] = 4; - Tuner->Init_Ctrl[12].val[2] = 0; - Tuner->Init_Ctrl[12].addr[3] = 44; - Tuner->Init_Ctrl[12].bit[3] = 5; - Tuner->Init_Ctrl[12].val[3] = 1; - Tuner->Init_Ctrl[12].addr[4] = 44; - Tuner->Init_Ctrl[12].bit[4] = 6; - Tuner->Init_Ctrl[12].val[4] = 0; - Tuner->Init_Ctrl[12].addr[5] = 44; - Tuner->Init_Ctrl[12].bit[5] = 7; - Tuner->Init_Ctrl[12].val[5] = 0; - - Tuner->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ; - Tuner->Init_Ctrl[13].size = 7 ; - Tuner->Init_Ctrl[13].addr[0] = 11; - Tuner->Init_Ctrl[13].bit[0] = 0; - Tuner->Init_Ctrl[13].val[0] = 1; - Tuner->Init_Ctrl[13].addr[1] = 11; - Tuner->Init_Ctrl[13].bit[1] = 1; - Tuner->Init_Ctrl[13].val[1] = 0; - Tuner->Init_Ctrl[13].addr[2] = 11; - Tuner->Init_Ctrl[13].bit[2] = 2; - Tuner->Init_Ctrl[13].val[2] = 0; - Tuner->Init_Ctrl[13].addr[3] = 11; - Tuner->Init_Ctrl[13].bit[3] = 3; - Tuner->Init_Ctrl[13].val[3] = 1; - Tuner->Init_Ctrl[13].addr[4] = 11; - Tuner->Init_Ctrl[13].bit[4] = 4; - Tuner->Init_Ctrl[13].val[4] = 1; - Tuner->Init_Ctrl[13].addr[5] = 11; - Tuner->Init_Ctrl[13].bit[5] = 5; - Tuner->Init_Ctrl[13].val[5] = 0; - Tuner->Init_Ctrl[13].addr[6] = 11; - Tuner->Init_Ctrl[13].bit[6] = 6; - Tuner->Init_Ctrl[13].val[6] = 0; - - Tuner->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ; - Tuner->Init_Ctrl[14].size = 16 ; - Tuner->Init_Ctrl[14].addr[0] = 13; - Tuner->Init_Ctrl[14].bit[0] = 0; - Tuner->Init_Ctrl[14].val[0] = 0; - Tuner->Init_Ctrl[14].addr[1] = 13; - Tuner->Init_Ctrl[14].bit[1] = 1; - Tuner->Init_Ctrl[14].val[1] = 0; - Tuner->Init_Ctrl[14].addr[2] = 13; - Tuner->Init_Ctrl[14].bit[2] = 2; - Tuner->Init_Ctrl[14].val[2] = 0; - Tuner->Init_Ctrl[14].addr[3] = 13; - Tuner->Init_Ctrl[14].bit[3] = 3; - Tuner->Init_Ctrl[14].val[3] = 0; - Tuner->Init_Ctrl[14].addr[4] = 13; - Tuner->Init_Ctrl[14].bit[4] = 4; - Tuner->Init_Ctrl[14].val[4] = 0; - Tuner->Init_Ctrl[14].addr[5] = 13; - Tuner->Init_Ctrl[14].bit[5] = 5; - Tuner->Init_Ctrl[14].val[5] = 0; - Tuner->Init_Ctrl[14].addr[6] = 13; - Tuner->Init_Ctrl[14].bit[6] = 6; - Tuner->Init_Ctrl[14].val[6] = 0; - Tuner->Init_Ctrl[14].addr[7] = 13; - Tuner->Init_Ctrl[14].bit[7] = 7; - Tuner->Init_Ctrl[14].val[7] = 0; - Tuner->Init_Ctrl[14].addr[8] = 12; - Tuner->Init_Ctrl[14].bit[8] = 0; - Tuner->Init_Ctrl[14].val[8] = 0; - Tuner->Init_Ctrl[14].addr[9] = 12; - Tuner->Init_Ctrl[14].bit[9] = 1; - Tuner->Init_Ctrl[14].val[9] = 0; - Tuner->Init_Ctrl[14].addr[10] = 12; - Tuner->Init_Ctrl[14].bit[10] = 2; - Tuner->Init_Ctrl[14].val[10] = 0; - Tuner->Init_Ctrl[14].addr[11] = 12; - Tuner->Init_Ctrl[14].bit[11] = 3; - Tuner->Init_Ctrl[14].val[11] = 0; - Tuner->Init_Ctrl[14].addr[12] = 12; - Tuner->Init_Ctrl[14].bit[12] = 4; - Tuner->Init_Ctrl[14].val[12] = 0; - Tuner->Init_Ctrl[14].addr[13] = 12; - Tuner->Init_Ctrl[14].bit[13] = 5; - Tuner->Init_Ctrl[14].val[13] = 1; - Tuner->Init_Ctrl[14].addr[14] = 12; - Tuner->Init_Ctrl[14].bit[14] = 6; - Tuner->Init_Ctrl[14].val[14] = 1; - Tuner->Init_Ctrl[14].addr[15] = 12; - Tuner->Init_Ctrl[14].bit[15] = 7; - Tuner->Init_Ctrl[14].val[15] = 0; - - Tuner->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ; - Tuner->Init_Ctrl[15].size = 3 ; - Tuner->Init_Ctrl[15].addr[0] = 147; - Tuner->Init_Ctrl[15].bit[0] = 2; - Tuner->Init_Ctrl[15].val[0] = 0; - Tuner->Init_Ctrl[15].addr[1] = 147; - Tuner->Init_Ctrl[15].bit[1] = 3; - Tuner->Init_Ctrl[15].val[1] = 1; - Tuner->Init_Ctrl[15].addr[2] = 147; - Tuner->Init_Ctrl[15].bit[2] = 4; - Tuner->Init_Ctrl[15].val[2] = 1; - - Tuner->Init_Ctrl[16].Ctrl_Num = I_DRIVER ; - Tuner->Init_Ctrl[16].size = 2 ; - Tuner->Init_Ctrl[16].addr[0] = 147; - Tuner->Init_Ctrl[16].bit[0] = 0; - Tuner->Init_Ctrl[16].val[0] = 0; - Tuner->Init_Ctrl[16].addr[1] = 147; - Tuner->Init_Ctrl[16].bit[1] = 1; - Tuner->Init_Ctrl[16].val[1] = 1; - - Tuner->Init_Ctrl[17].Ctrl_Num = EN_AAF ; - Tuner->Init_Ctrl[17].size = 1 ; - Tuner->Init_Ctrl[17].addr[0] = 147; - Tuner->Init_Ctrl[17].bit[0] = 7; - Tuner->Init_Ctrl[17].val[0] = 0; - - Tuner->Init_Ctrl[18].Ctrl_Num = EN_3P ; - Tuner->Init_Ctrl[18].size = 1 ; - Tuner->Init_Ctrl[18].addr[0] = 147; - Tuner->Init_Ctrl[18].bit[0] = 6; - Tuner->Init_Ctrl[18].val[0] = 0; - - Tuner->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ; - Tuner->Init_Ctrl[19].size = 1 ; - Tuner->Init_Ctrl[19].addr[0] = 156; - Tuner->Init_Ctrl[19].bit[0] = 0; - Tuner->Init_Ctrl[19].val[0] = 0; - - Tuner->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ; - Tuner->Init_Ctrl[20].size = 1 ; - Tuner->Init_Ctrl[20].addr[0] = 147; - Tuner->Init_Ctrl[20].bit[0] = 5; - Tuner->Init_Ctrl[20].val[0] = 0; - - Tuner->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ; - Tuner->Init_Ctrl[21].size = 1 ; - Tuner->Init_Ctrl[21].addr[0] = 137; - Tuner->Init_Ctrl[21].bit[0] = 4; - Tuner->Init_Ctrl[21].val[0] = 0; - - Tuner->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ; - Tuner->Init_Ctrl[22].size = 1 ; - Tuner->Init_Ctrl[22].addr[0] = 137; - Tuner->Init_Ctrl[22].bit[0] = 7; - Tuner->Init_Ctrl[22].val[0] = 0; - - Tuner->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ; - Tuner->Init_Ctrl[23].size = 1 ; - Tuner->Init_Ctrl[23].addr[0] = 91; - Tuner->Init_Ctrl[23].bit[0] = 5; - Tuner->Init_Ctrl[23].val[0] = 1; - - Tuner->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ; - Tuner->Init_Ctrl[24].size = 1 ; - Tuner->Init_Ctrl[24].addr[0] = 43; - Tuner->Init_Ctrl[24].bit[0] = 0; - Tuner->Init_Ctrl[24].val[0] = 1; - - Tuner->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ; - Tuner->Init_Ctrl[25].size = 2 ; - Tuner->Init_Ctrl[25].addr[0] = 22; - Tuner->Init_Ctrl[25].bit[0] = 0; - Tuner->Init_Ctrl[25].val[0] = 1; - Tuner->Init_Ctrl[25].addr[1] = 22; - Tuner->Init_Ctrl[25].bit[1] = 1; - Tuner->Init_Ctrl[25].val[1] = 1; - - Tuner->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ; - Tuner->Init_Ctrl[26].size = 1 ; - Tuner->Init_Ctrl[26].addr[0] = 134; - Tuner->Init_Ctrl[26].bit[0] = 2; - Tuner->Init_Ctrl[26].val[0] = 0; - - Tuner->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ; - Tuner->Init_Ctrl[27].size = 1 ; - Tuner->Init_Ctrl[27].addr[0] = 137; - Tuner->Init_Ctrl[27].bit[0] = 3; - Tuner->Init_Ctrl[27].val[0] = 0; - - Tuner->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ; - Tuner->Init_Ctrl[28].size = 1 ; - Tuner->Init_Ctrl[28].addr[0] = 77; - Tuner->Init_Ctrl[28].bit[0] = 7; - Tuner->Init_Ctrl[28].val[0] = 0; - - Tuner->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ; - Tuner->Init_Ctrl[29].size = 1 ; - Tuner->Init_Ctrl[29].addr[0] = 166; - Tuner->Init_Ctrl[29].bit[0] = 7; - Tuner->Init_Ctrl[29].val[0] = 1; - - Tuner->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ; - Tuner->Init_Ctrl[30].size = 3 ; - Tuner->Init_Ctrl[30].addr[0] = 166; - Tuner->Init_Ctrl[30].bit[0] = 0; - Tuner->Init_Ctrl[30].val[0] = 0; - Tuner->Init_Ctrl[30].addr[1] = 166; - Tuner->Init_Ctrl[30].bit[1] = 1; - Tuner->Init_Ctrl[30].val[1] = 1; - Tuner->Init_Ctrl[30].addr[2] = 166; - Tuner->Init_Ctrl[30].bit[2] = 2; - Tuner->Init_Ctrl[30].val[2] = 1; - - Tuner->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ; - Tuner->Init_Ctrl[31].size = 3 ; - Tuner->Init_Ctrl[31].addr[0] = 166; - Tuner->Init_Ctrl[31].bit[0] = 3; - Tuner->Init_Ctrl[31].val[0] = 1; - Tuner->Init_Ctrl[31].addr[1] = 166; - Tuner->Init_Ctrl[31].bit[1] = 4; - Tuner->Init_Ctrl[31].val[1] = 0; - Tuner->Init_Ctrl[31].addr[2] = 166; - Tuner->Init_Ctrl[31].bit[2] = 5; - Tuner->Init_Ctrl[31].val[2] = 1; - - Tuner->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ; - Tuner->Init_Ctrl[32].size = 3 ; - Tuner->Init_Ctrl[32].addr[0] = 167; - Tuner->Init_Ctrl[32].bit[0] = 0; - Tuner->Init_Ctrl[32].val[0] = 1; - Tuner->Init_Ctrl[32].addr[1] = 167; - Tuner->Init_Ctrl[32].bit[1] = 1; - Tuner->Init_Ctrl[32].val[1] = 1; - Tuner->Init_Ctrl[32].addr[2] = 167; - Tuner->Init_Ctrl[32].bit[2] = 2; - Tuner->Init_Ctrl[32].val[2] = 0; - - Tuner->Init_Ctrl[33].Ctrl_Num = RFA_FLR ; - Tuner->Init_Ctrl[33].size = 4 ; - Tuner->Init_Ctrl[33].addr[0] = 168; - Tuner->Init_Ctrl[33].bit[0] = 0; - Tuner->Init_Ctrl[33].val[0] = 0; - Tuner->Init_Ctrl[33].addr[1] = 168; - Tuner->Init_Ctrl[33].bit[1] = 1; - Tuner->Init_Ctrl[33].val[1] = 1; - Tuner->Init_Ctrl[33].addr[2] = 168; - Tuner->Init_Ctrl[33].bit[2] = 2; - Tuner->Init_Ctrl[33].val[2] = 0; - Tuner->Init_Ctrl[33].addr[3] = 168; - Tuner->Init_Ctrl[33].bit[3] = 3; - Tuner->Init_Ctrl[33].val[3] = 0; - - Tuner->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ; - Tuner->Init_Ctrl[34].size = 4 ; - Tuner->Init_Ctrl[34].addr[0] = 168; - Tuner->Init_Ctrl[34].bit[0] = 4; - Tuner->Init_Ctrl[34].val[0] = 1; - Tuner->Init_Ctrl[34].addr[1] = 168; - Tuner->Init_Ctrl[34].bit[1] = 5; - Tuner->Init_Ctrl[34].val[1] = 1; - Tuner->Init_Ctrl[34].addr[2] = 168; - Tuner->Init_Ctrl[34].bit[2] = 6; - Tuner->Init_Ctrl[34].val[2] = 1; - Tuner->Init_Ctrl[34].addr[3] = 168; - Tuner->Init_Ctrl[34].bit[3] = 7; - Tuner->Init_Ctrl[34].val[3] = 1; - - Tuner->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ; - Tuner->Init_Ctrl[35].size = 1 ; - Tuner->Init_Ctrl[35].addr[0] = 135; - Tuner->Init_Ctrl[35].bit[0] = 0; - Tuner->Init_Ctrl[35].val[0] = 0; - - Tuner->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ; - Tuner->Init_Ctrl[36].size = 1 ; - Tuner->Init_Ctrl[36].addr[0] = 56; - Tuner->Init_Ctrl[36].bit[0] = 3; - Tuner->Init_Ctrl[36].val[0] = 0; - - Tuner->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ; - Tuner->Init_Ctrl[37].size = 7 ; - Tuner->Init_Ctrl[37].addr[0] = 59; - Tuner->Init_Ctrl[37].bit[0] = 1; - Tuner->Init_Ctrl[37].val[0] = 0; - Tuner->Init_Ctrl[37].addr[1] = 59; - Tuner->Init_Ctrl[37].bit[1] = 2; - Tuner->Init_Ctrl[37].val[1] = 0; - Tuner->Init_Ctrl[37].addr[2] = 59; - Tuner->Init_Ctrl[37].bit[2] = 3; - Tuner->Init_Ctrl[37].val[2] = 0; - Tuner->Init_Ctrl[37].addr[3] = 59; - Tuner->Init_Ctrl[37].bit[3] = 4; - Tuner->Init_Ctrl[37].val[3] = 0; - Tuner->Init_Ctrl[37].addr[4] = 59; - Tuner->Init_Ctrl[37].bit[4] = 5; - Tuner->Init_Ctrl[37].val[4] = 0; - Tuner->Init_Ctrl[37].addr[5] = 59; - Tuner->Init_Ctrl[37].bit[5] = 6; - Tuner->Init_Ctrl[37].val[5] = 0; - Tuner->Init_Ctrl[37].addr[6] = 59; - Tuner->Init_Ctrl[37].bit[6] = 7; - Tuner->Init_Ctrl[37].val[6] = 0; - - Tuner->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ; - Tuner->Init_Ctrl[38].size = 6 ; - Tuner->Init_Ctrl[38].addr[0] = 32; - Tuner->Init_Ctrl[38].bit[0] = 2; - Tuner->Init_Ctrl[38].val[0] = 0; - Tuner->Init_Ctrl[38].addr[1] = 32; - Tuner->Init_Ctrl[38].bit[1] = 3; - Tuner->Init_Ctrl[38].val[1] = 0; - Tuner->Init_Ctrl[38].addr[2] = 32; - Tuner->Init_Ctrl[38].bit[2] = 4; - Tuner->Init_Ctrl[38].val[2] = 0; - Tuner->Init_Ctrl[38].addr[3] = 32; - Tuner->Init_Ctrl[38].bit[3] = 5; - Tuner->Init_Ctrl[38].val[3] = 0; - Tuner->Init_Ctrl[38].addr[4] = 32; - Tuner->Init_Ctrl[38].bit[4] = 6; - Tuner->Init_Ctrl[38].val[4] = 1; - Tuner->Init_Ctrl[38].addr[5] = 32; - Tuner->Init_Ctrl[38].bit[5] = 7; - Tuner->Init_Ctrl[38].val[5] = 0; - - Tuner->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ; - Tuner->Init_Ctrl[39].size = 1 ; - Tuner->Init_Ctrl[39].addr[0] = 25; - Tuner->Init_Ctrl[39].bit[0] = 3; - Tuner->Init_Ctrl[39].val[0] = 1; - - - Tuner->CH_Ctrl_Num = CHCTRL_NUM ; - - Tuner->CH_Ctrl[0].Ctrl_Num = DN_POLY ; - Tuner->CH_Ctrl[0].size = 2 ; - Tuner->CH_Ctrl[0].addr[0] = 68; - Tuner->CH_Ctrl[0].bit[0] = 6; - Tuner->CH_Ctrl[0].val[0] = 1; - Tuner->CH_Ctrl[0].addr[1] = 68; - Tuner->CH_Ctrl[0].bit[1] = 7; - Tuner->CH_Ctrl[0].val[1] = 1; - - Tuner->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ; - Tuner->CH_Ctrl[1].size = 2 ; - Tuner->CH_Ctrl[1].addr[0] = 70; - Tuner->CH_Ctrl[1].bit[0] = 6; - Tuner->CH_Ctrl[1].val[0] = 1; - Tuner->CH_Ctrl[1].addr[1] = 70; - Tuner->CH_Ctrl[1].bit[1] = 7; - Tuner->CH_Ctrl[1].val[1] = 0; - - Tuner->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ; - Tuner->CH_Ctrl[2].size = 9 ; - Tuner->CH_Ctrl[2].addr[0] = 69; - Tuner->CH_Ctrl[2].bit[0] = 5; - Tuner->CH_Ctrl[2].val[0] = 0; - Tuner->CH_Ctrl[2].addr[1] = 69; - Tuner->CH_Ctrl[2].bit[1] = 6; - Tuner->CH_Ctrl[2].val[1] = 0; - Tuner->CH_Ctrl[2].addr[2] = 69; - Tuner->CH_Ctrl[2].bit[2] = 7; - Tuner->CH_Ctrl[2].val[2] = 0; - Tuner->CH_Ctrl[2].addr[3] = 68; - Tuner->CH_Ctrl[2].bit[3] = 0; - Tuner->CH_Ctrl[2].val[3] = 0; - Tuner->CH_Ctrl[2].addr[4] = 68; - Tuner->CH_Ctrl[2].bit[4] = 1; - Tuner->CH_Ctrl[2].val[4] = 0; - Tuner->CH_Ctrl[2].addr[5] = 68; - Tuner->CH_Ctrl[2].bit[5] = 2; - Tuner->CH_Ctrl[2].val[5] = 0; - Tuner->CH_Ctrl[2].addr[6] = 68; - Tuner->CH_Ctrl[2].bit[6] = 3; - Tuner->CH_Ctrl[2].val[6] = 0; - Tuner->CH_Ctrl[2].addr[7] = 68; - Tuner->CH_Ctrl[2].bit[7] = 4; - Tuner->CH_Ctrl[2].val[7] = 0; - Tuner->CH_Ctrl[2].addr[8] = 68; - Tuner->CH_Ctrl[2].bit[8] = 5; - Tuner->CH_Ctrl[2].val[8] = 0; - - Tuner->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ; - Tuner->CH_Ctrl[3].size = 1 ; - Tuner->CH_Ctrl[3].addr[0] = 70; - Tuner->CH_Ctrl[3].bit[0] = 5; - Tuner->CH_Ctrl[3].val[0] = 0; - - Tuner->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ; - Tuner->CH_Ctrl[4].size = 3 ; - Tuner->CH_Ctrl[4].addr[0] = 73; - Tuner->CH_Ctrl[4].bit[0] = 4; - Tuner->CH_Ctrl[4].val[0] = 0; - Tuner->CH_Ctrl[4].addr[1] = 73; - Tuner->CH_Ctrl[4].bit[1] = 5; - Tuner->CH_Ctrl[4].val[1] = 1; - Tuner->CH_Ctrl[4].addr[2] = 73; - Tuner->CH_Ctrl[4].bit[2] = 6; - Tuner->CH_Ctrl[4].val[2] = 0; - - Tuner->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ; - Tuner->CH_Ctrl[5].size = 4 ; - Tuner->CH_Ctrl[5].addr[0] = 70; - Tuner->CH_Ctrl[5].bit[0] = 0; - Tuner->CH_Ctrl[5].val[0] = 0; - Tuner->CH_Ctrl[5].addr[1] = 70; - Tuner->CH_Ctrl[5].bit[1] = 1; - Tuner->CH_Ctrl[5].val[1] = 0; - Tuner->CH_Ctrl[5].addr[2] = 70; - Tuner->CH_Ctrl[5].bit[2] = 2; - Tuner->CH_Ctrl[5].val[2] = 0; - Tuner->CH_Ctrl[5].addr[3] = 70; - Tuner->CH_Ctrl[5].bit[3] = 3; - Tuner->CH_Ctrl[5].val[3] = 0; - - Tuner->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ; - Tuner->CH_Ctrl[6].size = 1 ; - Tuner->CH_Ctrl[6].addr[0] = 70; - Tuner->CH_Ctrl[6].bit[0] = 4; - Tuner->CH_Ctrl[6].val[0] = 1; - - Tuner->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ; - Tuner->CH_Ctrl[7].size = 1 ; - Tuner->CH_Ctrl[7].addr[0] = 111; - Tuner->CH_Ctrl[7].bit[0] = 4; - Tuner->CH_Ctrl[7].val[0] = 0; - - Tuner->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ; - Tuner->CH_Ctrl[8].size = 1 ; - Tuner->CH_Ctrl[8].addr[0] = 111; - Tuner->CH_Ctrl[8].bit[0] = 7; - Tuner->CH_Ctrl[8].val[0] = 1; - - Tuner->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ; - Tuner->CH_Ctrl[9].size = 1 ; - Tuner->CH_Ctrl[9].addr[0] = 111; - Tuner->CH_Ctrl[9].bit[0] = 6; - Tuner->CH_Ctrl[9].val[0] = 1; - - Tuner->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ; - Tuner->CH_Ctrl[10].size = 1 ; - Tuner->CH_Ctrl[10].addr[0] = 111; - Tuner->CH_Ctrl[10].bit[0] = 5; - Tuner->CH_Ctrl[10].val[0] = 0; - - Tuner->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ; - Tuner->CH_Ctrl[11].size = 2 ; - Tuner->CH_Ctrl[11].addr[0] = 110; - Tuner->CH_Ctrl[11].bit[0] = 0; - Tuner->CH_Ctrl[11].val[0] = 1; - Tuner->CH_Ctrl[11].addr[1] = 110; - Tuner->CH_Ctrl[11].bit[1] = 1; - Tuner->CH_Ctrl[11].val[1] = 0; - - Tuner->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ; - Tuner->CH_Ctrl[12].size = 3 ; - Tuner->CH_Ctrl[12].addr[0] = 69; - Tuner->CH_Ctrl[12].bit[0] = 2; - Tuner->CH_Ctrl[12].val[0] = 0; - Tuner->CH_Ctrl[12].addr[1] = 69; - Tuner->CH_Ctrl[12].bit[1] = 3; - Tuner->CH_Ctrl[12].val[1] = 0; - Tuner->CH_Ctrl[12].addr[2] = 69; - Tuner->CH_Ctrl[12].bit[2] = 4; - Tuner->CH_Ctrl[12].val[2] = 0; - - Tuner->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ; - Tuner->CH_Ctrl[13].size = 6 ; - Tuner->CH_Ctrl[13].addr[0] = 110; - Tuner->CH_Ctrl[13].bit[0] = 2; - Tuner->CH_Ctrl[13].val[0] = 0; - Tuner->CH_Ctrl[13].addr[1] = 110; - Tuner->CH_Ctrl[13].bit[1] = 3; - Tuner->CH_Ctrl[13].val[1] = 0; - Tuner->CH_Ctrl[13].addr[2] = 110; - Tuner->CH_Ctrl[13].bit[2] = 4; - Tuner->CH_Ctrl[13].val[2] = 0; - Tuner->CH_Ctrl[13].addr[3] = 110; - Tuner->CH_Ctrl[13].bit[3] = 5; - Tuner->CH_Ctrl[13].val[3] = 0; - Tuner->CH_Ctrl[13].addr[4] = 110; - Tuner->CH_Ctrl[13].bit[4] = 6; - Tuner->CH_Ctrl[13].val[4] = 0; - Tuner->CH_Ctrl[13].addr[5] = 110; - Tuner->CH_Ctrl[13].bit[5] = 7; - Tuner->CH_Ctrl[13].val[5] = 1; - - Tuner->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ; - Tuner->CH_Ctrl[14].size = 7 ; - Tuner->CH_Ctrl[14].addr[0] = 14; - Tuner->CH_Ctrl[14].bit[0] = 0; - Tuner->CH_Ctrl[14].val[0] = 0; - Tuner->CH_Ctrl[14].addr[1] = 14; - Tuner->CH_Ctrl[14].bit[1] = 1; - Tuner->CH_Ctrl[14].val[1] = 0; - Tuner->CH_Ctrl[14].addr[2] = 14; - Tuner->CH_Ctrl[14].bit[2] = 2; - Tuner->CH_Ctrl[14].val[2] = 0; - Tuner->CH_Ctrl[14].addr[3] = 14; - Tuner->CH_Ctrl[14].bit[3] = 3; - Tuner->CH_Ctrl[14].val[3] = 0; - Tuner->CH_Ctrl[14].addr[4] = 14; - Tuner->CH_Ctrl[14].bit[4] = 4; - Tuner->CH_Ctrl[14].val[4] = 0; - Tuner->CH_Ctrl[14].addr[5] = 14; - Tuner->CH_Ctrl[14].bit[5] = 5; - Tuner->CH_Ctrl[14].val[5] = 0; - Tuner->CH_Ctrl[14].addr[6] = 14; - Tuner->CH_Ctrl[14].bit[6] = 6; - Tuner->CH_Ctrl[14].val[6] = 0; - - Tuner->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ; - Tuner->CH_Ctrl[15].size = 18 ; - Tuner->CH_Ctrl[15].addr[0] = 17; - Tuner->CH_Ctrl[15].bit[0] = 6; - Tuner->CH_Ctrl[15].val[0] = 0; - Tuner->CH_Ctrl[15].addr[1] = 17; - Tuner->CH_Ctrl[15].bit[1] = 7; - Tuner->CH_Ctrl[15].val[1] = 0; - Tuner->CH_Ctrl[15].addr[2] = 16; - Tuner->CH_Ctrl[15].bit[2] = 0; - Tuner->CH_Ctrl[15].val[2] = 0; - Tuner->CH_Ctrl[15].addr[3] = 16; - Tuner->CH_Ctrl[15].bit[3] = 1; - Tuner->CH_Ctrl[15].val[3] = 0; - Tuner->CH_Ctrl[15].addr[4] = 16; - Tuner->CH_Ctrl[15].bit[4] = 2; - Tuner->CH_Ctrl[15].val[4] = 0; - Tuner->CH_Ctrl[15].addr[5] = 16; - Tuner->CH_Ctrl[15].bit[5] = 3; - Tuner->CH_Ctrl[15].val[5] = 0; - Tuner->CH_Ctrl[15].addr[6] = 16; - Tuner->CH_Ctrl[15].bit[6] = 4; - Tuner->CH_Ctrl[15].val[6] = 0; - Tuner->CH_Ctrl[15].addr[7] = 16; - Tuner->CH_Ctrl[15].bit[7] = 5; - Tuner->CH_Ctrl[15].val[7] = 0; - Tuner->CH_Ctrl[15].addr[8] = 16; - Tuner->CH_Ctrl[15].bit[8] = 6; - Tuner->CH_Ctrl[15].val[8] = 0; - Tuner->CH_Ctrl[15].addr[9] = 16; - Tuner->CH_Ctrl[15].bit[9] = 7; - Tuner->CH_Ctrl[15].val[9] = 0; - Tuner->CH_Ctrl[15].addr[10] = 15; - Tuner->CH_Ctrl[15].bit[10] = 0; - Tuner->CH_Ctrl[15].val[10] = 0; - Tuner->CH_Ctrl[15].addr[11] = 15; - Tuner->CH_Ctrl[15].bit[11] = 1; - Tuner->CH_Ctrl[15].val[11] = 0; - Tuner->CH_Ctrl[15].addr[12] = 15; - Tuner->CH_Ctrl[15].bit[12] = 2; - Tuner->CH_Ctrl[15].val[12] = 0; - Tuner->CH_Ctrl[15].addr[13] = 15; - Tuner->CH_Ctrl[15].bit[13] = 3; - Tuner->CH_Ctrl[15].val[13] = 0; - Tuner->CH_Ctrl[15].addr[14] = 15; - Tuner->CH_Ctrl[15].bit[14] = 4; - Tuner->CH_Ctrl[15].val[14] = 0; - Tuner->CH_Ctrl[15].addr[15] = 15; - Tuner->CH_Ctrl[15].bit[15] = 5; - Tuner->CH_Ctrl[15].val[15] = 0; - Tuner->CH_Ctrl[15].addr[16] = 15; - Tuner->CH_Ctrl[15].bit[16] = 6; - Tuner->CH_Ctrl[15].val[16] = 1; - Tuner->CH_Ctrl[15].addr[17] = 15; - Tuner->CH_Ctrl[15].bit[17] = 7; - Tuner->CH_Ctrl[15].val[17] = 1; - - Tuner->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ; - Tuner->CH_Ctrl[16].size = 5 ; - Tuner->CH_Ctrl[16].addr[0] = 112; - Tuner->CH_Ctrl[16].bit[0] = 0; - Tuner->CH_Ctrl[16].val[0] = 0; - Tuner->CH_Ctrl[16].addr[1] = 112; - Tuner->CH_Ctrl[16].bit[1] = 1; - Tuner->CH_Ctrl[16].val[1] = 0; - Tuner->CH_Ctrl[16].addr[2] = 112; - Tuner->CH_Ctrl[16].bit[2] = 2; - Tuner->CH_Ctrl[16].val[2] = 0; - Tuner->CH_Ctrl[16].addr[3] = 112; - Tuner->CH_Ctrl[16].bit[3] = 3; - Tuner->CH_Ctrl[16].val[3] = 0; - Tuner->CH_Ctrl[16].addr[4] = 112; - Tuner->CH_Ctrl[16].bit[4] = 4; - Tuner->CH_Ctrl[16].val[4] = 1; - - Tuner->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ; - Tuner->CH_Ctrl[17].size = 1 ; - Tuner->CH_Ctrl[17].addr[0] = 14; - Tuner->CH_Ctrl[17].bit[0] = 7; - Tuner->CH_Ctrl[17].val[0] = 0; - - Tuner->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ; - Tuner->CH_Ctrl[18].size = 4 ; - Tuner->CH_Ctrl[18].addr[0] = 107; - Tuner->CH_Ctrl[18].bit[0] = 3; - Tuner->CH_Ctrl[18].val[0] = 0; - Tuner->CH_Ctrl[18].addr[1] = 107; - Tuner->CH_Ctrl[18].bit[1] = 4; - Tuner->CH_Ctrl[18].val[1] = 0; - Tuner->CH_Ctrl[18].addr[2] = 107; - Tuner->CH_Ctrl[18].bit[2] = 5; - Tuner->CH_Ctrl[18].val[2] = 0; - Tuner->CH_Ctrl[18].addr[3] = 107; - Tuner->CH_Ctrl[18].bit[3] = 6; - Tuner->CH_Ctrl[18].val[3] = 0; - - Tuner->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ; - Tuner->CH_Ctrl[19].size = 3 ; - Tuner->CH_Ctrl[19].addr[0] = 107; - Tuner->CH_Ctrl[19].bit[0] = 7; - Tuner->CH_Ctrl[19].val[0] = 1; - Tuner->CH_Ctrl[19].addr[1] = 106; - Tuner->CH_Ctrl[19].bit[1] = 0; - Tuner->CH_Ctrl[19].val[1] = 1; - Tuner->CH_Ctrl[19].addr[2] = 106; - Tuner->CH_Ctrl[19].bit[2] = 1; - Tuner->CH_Ctrl[19].val[2] = 1; - - Tuner->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ; - Tuner->CH_Ctrl[20].size = 11 ; - Tuner->CH_Ctrl[20].addr[0] = 109; - Tuner->CH_Ctrl[20].bit[0] = 2; - Tuner->CH_Ctrl[20].val[0] = 0; - Tuner->CH_Ctrl[20].addr[1] = 109; - Tuner->CH_Ctrl[20].bit[1] = 3; - Tuner->CH_Ctrl[20].val[1] = 0; - Tuner->CH_Ctrl[20].addr[2] = 109; - Tuner->CH_Ctrl[20].bit[2] = 4; - Tuner->CH_Ctrl[20].val[2] = 0; - Tuner->CH_Ctrl[20].addr[3] = 109; - Tuner->CH_Ctrl[20].bit[3] = 5; - Tuner->CH_Ctrl[20].val[3] = 0; - Tuner->CH_Ctrl[20].addr[4] = 109; - Tuner->CH_Ctrl[20].bit[4] = 6; - Tuner->CH_Ctrl[20].val[4] = 0; - Tuner->CH_Ctrl[20].addr[5] = 109; - Tuner->CH_Ctrl[20].bit[5] = 7; - Tuner->CH_Ctrl[20].val[5] = 0; - Tuner->CH_Ctrl[20].addr[6] = 108; - Tuner->CH_Ctrl[20].bit[6] = 0; - Tuner->CH_Ctrl[20].val[6] = 0; - Tuner->CH_Ctrl[20].addr[7] = 108; - Tuner->CH_Ctrl[20].bit[7] = 1; - Tuner->CH_Ctrl[20].val[7] = 0; - Tuner->CH_Ctrl[20].addr[8] = 108; - Tuner->CH_Ctrl[20].bit[8] = 2; - Tuner->CH_Ctrl[20].val[8] = 1; - Tuner->CH_Ctrl[20].addr[9] = 108; - Tuner->CH_Ctrl[20].bit[9] = 3; - Tuner->CH_Ctrl[20].val[9] = 1; - Tuner->CH_Ctrl[20].addr[10] = 108; - Tuner->CH_Ctrl[20].bit[10] = 4; - Tuner->CH_Ctrl[20].val[10] = 1; - - Tuner->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ; - Tuner->CH_Ctrl[21].size = 6 ; - Tuner->CH_Ctrl[21].addr[0] = 106; - Tuner->CH_Ctrl[21].bit[0] = 2; - Tuner->CH_Ctrl[21].val[0] = 0; - Tuner->CH_Ctrl[21].addr[1] = 106; - Tuner->CH_Ctrl[21].bit[1] = 3; - Tuner->CH_Ctrl[21].val[1] = 0; - Tuner->CH_Ctrl[21].addr[2] = 106; - Tuner->CH_Ctrl[21].bit[2] = 4; - Tuner->CH_Ctrl[21].val[2] = 0; - Tuner->CH_Ctrl[21].addr[3] = 106; - Tuner->CH_Ctrl[21].bit[3] = 5; - Tuner->CH_Ctrl[21].val[3] = 0; - Tuner->CH_Ctrl[21].addr[4] = 106; - Tuner->CH_Ctrl[21].bit[4] = 6; - Tuner->CH_Ctrl[21].val[4] = 0; - Tuner->CH_Ctrl[21].addr[5] = 106; - Tuner->CH_Ctrl[21].bit[5] = 7; - Tuner->CH_Ctrl[21].val[5] = 1; - - Tuner->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ; - Tuner->CH_Ctrl[22].size = 1 ; - Tuner->CH_Ctrl[22].addr[0] = 138; - Tuner->CH_Ctrl[22].bit[0] = 4; - Tuner->CH_Ctrl[22].val[0] = 1; - - Tuner->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ; - Tuner->CH_Ctrl[23].size = 1 ; - Tuner->CH_Ctrl[23].addr[0] = 17; - Tuner->CH_Ctrl[23].bit[0] = 5; - Tuner->CH_Ctrl[23].val[0] = 0; - - Tuner->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ; - Tuner->CH_Ctrl[24].size = 1 ; - Tuner->CH_Ctrl[24].addr[0] = 111; - Tuner->CH_Ctrl[24].bit[0] = 3; - Tuner->CH_Ctrl[24].val[0] = 0; - - Tuner->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ; - Tuner->CH_Ctrl[25].size = 1 ; - Tuner->CH_Ctrl[25].addr[0] = 112; - Tuner->CH_Ctrl[25].bit[0] = 7; - Tuner->CH_Ctrl[25].val[0] = 0; - - Tuner->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ; - Tuner->CH_Ctrl[26].size = 1 ; - Tuner->CH_Ctrl[26].addr[0] = 136; - Tuner->CH_Ctrl[26].bit[0] = 7; - Tuner->CH_Ctrl[26].val[0] = 0; - - Tuner->CH_Ctrl[27].Ctrl_Num = GPIO_4B ; - Tuner->CH_Ctrl[27].size = 1 ; - Tuner->CH_Ctrl[27].addr[0] = 149; - Tuner->CH_Ctrl[27].bit[0] = 7; - Tuner->CH_Ctrl[27].val[0] = 0; - - Tuner->CH_Ctrl[28].Ctrl_Num = GPIO_3B ; - Tuner->CH_Ctrl[28].size = 1 ; - Tuner->CH_Ctrl[28].addr[0] = 149; - Tuner->CH_Ctrl[28].bit[0] = 6; - Tuner->CH_Ctrl[28].val[0] = 0; - - Tuner->CH_Ctrl[29].Ctrl_Num = GPIO_4 ; - Tuner->CH_Ctrl[29].size = 1 ; - Tuner->CH_Ctrl[29].addr[0] = 149; - Tuner->CH_Ctrl[29].bit[0] = 5; - Tuner->CH_Ctrl[29].val[0] = 1; - - Tuner->CH_Ctrl[30].Ctrl_Num = GPIO_3 ; - Tuner->CH_Ctrl[30].size = 1 ; - Tuner->CH_Ctrl[30].addr[0] = 149; - Tuner->CH_Ctrl[30].bit[0] = 4; - Tuner->CH_Ctrl[30].val[0] = 1; - - Tuner->CH_Ctrl[31].Ctrl_Num = GPIO_1B ; - Tuner->CH_Ctrl[31].size = 1 ; - Tuner->CH_Ctrl[31].addr[0] = 149; - Tuner->CH_Ctrl[31].bit[0] = 3; - Tuner->CH_Ctrl[31].val[0] = 0; - - Tuner->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ; - Tuner->CH_Ctrl[32].size = 1 ; - Tuner->CH_Ctrl[32].addr[0] = 93; - Tuner->CH_Ctrl[32].bit[0] = 1; - Tuner->CH_Ctrl[32].val[0] = 0; - - Tuner->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ; - Tuner->CH_Ctrl[33].size = 1 ; - Tuner->CH_Ctrl[33].addr[0] = 93; - Tuner->CH_Ctrl[33].bit[0] = 0; - Tuner->CH_Ctrl[33].val[0] = 0; - - Tuner->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ; - Tuner->CH_Ctrl[34].size = 6 ; - Tuner->CH_Ctrl[34].addr[0] = 92; - Tuner->CH_Ctrl[34].bit[0] = 2; - Tuner->CH_Ctrl[34].val[0] = 0; - Tuner->CH_Ctrl[34].addr[1] = 92; - Tuner->CH_Ctrl[34].bit[1] = 3; - Tuner->CH_Ctrl[34].val[1] = 0; - Tuner->CH_Ctrl[34].addr[2] = 92; - Tuner->CH_Ctrl[34].bit[2] = 4; - Tuner->CH_Ctrl[34].val[2] = 0; - Tuner->CH_Ctrl[34].addr[3] = 92; - Tuner->CH_Ctrl[34].bit[3] = 5; - Tuner->CH_Ctrl[34].val[3] = 0; - Tuner->CH_Ctrl[34].addr[4] = 92; - Tuner->CH_Ctrl[34].bit[4] = 6; - Tuner->CH_Ctrl[34].val[4] = 0; - Tuner->CH_Ctrl[34].addr[5] = 92; - Tuner->CH_Ctrl[34].bit[5] = 7; - Tuner->CH_Ctrl[34].val[5] = 0; - - Tuner->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ; - Tuner->CH_Ctrl[35].size = 6 ; - Tuner->CH_Ctrl[35].addr[0] = 93; - Tuner->CH_Ctrl[35].bit[0] = 2; - Tuner->CH_Ctrl[35].val[0] = 0; - Tuner->CH_Ctrl[35].addr[1] = 93; - Tuner->CH_Ctrl[35].bit[1] = 3; - Tuner->CH_Ctrl[35].val[1] = 0; - Tuner->CH_Ctrl[35].addr[2] = 93; - Tuner->CH_Ctrl[35].bit[2] = 4; - Tuner->CH_Ctrl[35].val[2] = 0; - Tuner->CH_Ctrl[35].addr[3] = 93; - Tuner->CH_Ctrl[35].bit[3] = 5; - Tuner->CH_Ctrl[35].val[3] = 0; - Tuner->CH_Ctrl[35].addr[4] = 93; - Tuner->CH_Ctrl[35].bit[4] = 6; - Tuner->CH_Ctrl[35].val[4] = 0; - Tuner->CH_Ctrl[35].addr[5] = 93; - Tuner->CH_Ctrl[35].bit[5] = 7; - Tuner->CH_Ctrl[35].val[5] = 0; + struct mxl5005s_state *state = fe->demodulator_priv; + state->Init_Ctrl_Num = INITCTRL_NUM; + + state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; + state->Init_Ctrl[0].size = 1 ; + state->Init_Ctrl[0].addr[0] = 73; + state->Init_Ctrl[0].bit[0] = 7; + state->Init_Ctrl[0].val[0] = 0; + + state->Init_Ctrl[1].Ctrl_Num = BB_MODE ; + state->Init_Ctrl[1].size = 1 ; + state->Init_Ctrl[1].addr[0] = 53; + state->Init_Ctrl[1].bit[0] = 2; + state->Init_Ctrl[1].val[0] = 1; + + state->Init_Ctrl[2].Ctrl_Num = BB_BUF ; + state->Init_Ctrl[2].size = 2 ; + state->Init_Ctrl[2].addr[0] = 53; + state->Init_Ctrl[2].bit[0] = 1; + state->Init_Ctrl[2].val[0] = 0; + state->Init_Ctrl[2].addr[1] = 57; + state->Init_Ctrl[2].bit[1] = 0; + state->Init_Ctrl[2].val[1] = 1; + + state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ; + state->Init_Ctrl[3].size = 1 ; + state->Init_Ctrl[3].addr[0] = 53; + state->Init_Ctrl[3].bit[0] = 0; + state->Init_Ctrl[3].val[0] = 0; + + state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ; + state->Init_Ctrl[4].size = 3 ; + state->Init_Ctrl[4].addr[0] = 53; + state->Init_Ctrl[4].bit[0] = 5; + state->Init_Ctrl[4].val[0] = 0; + state->Init_Ctrl[4].addr[1] = 53; + state->Init_Ctrl[4].bit[1] = 6; + state->Init_Ctrl[4].val[1] = 0; + state->Init_Ctrl[4].addr[2] = 53; + state->Init_Ctrl[4].bit[2] = 7; + state->Init_Ctrl[4].val[2] = 1; + + state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ; + state->Init_Ctrl[5].size = 1 ; + state->Init_Ctrl[5].addr[0] = 59; + state->Init_Ctrl[5].bit[0] = 0; + state->Init_Ctrl[5].val[0] = 0; + + state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ; + state->Init_Ctrl[6].size = 2 ; + state->Init_Ctrl[6].addr[0] = 53; + state->Init_Ctrl[6].bit[0] = 3; + state->Init_Ctrl[6].val[0] = 0; + state->Init_Ctrl[6].addr[1] = 53; + state->Init_Ctrl[6].bit[1] = 4; + state->Init_Ctrl[6].val[1] = 1; + + state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ; + state->Init_Ctrl[7].size = 4 ; + state->Init_Ctrl[7].addr[0] = 22; + state->Init_Ctrl[7].bit[0] = 4; + state->Init_Ctrl[7].val[0] = 0; + state->Init_Ctrl[7].addr[1] = 22; + state->Init_Ctrl[7].bit[1] = 5; + state->Init_Ctrl[7].val[1] = 1; + state->Init_Ctrl[7].addr[2] = 22; + state->Init_Ctrl[7].bit[2] = 6; + state->Init_Ctrl[7].val[2] = 1; + state->Init_Ctrl[7].addr[3] = 22; + state->Init_Ctrl[7].bit[3] = 7; + state->Init_Ctrl[7].val[3] = 0; + + state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ; + state->Init_Ctrl[8].size = 1 ; + state->Init_Ctrl[8].addr[0] = 22; + state->Init_Ctrl[8].bit[0] = 2; + state->Init_Ctrl[8].val[0] = 0; + + state->Init_Ctrl[9].Ctrl_Num = AGC_IF ; + state->Init_Ctrl[9].size = 4 ; + state->Init_Ctrl[9].addr[0] = 76; + state->Init_Ctrl[9].bit[0] = 0; + state->Init_Ctrl[9].val[0] = 1; + state->Init_Ctrl[9].addr[1] = 76; + state->Init_Ctrl[9].bit[1] = 1; + state->Init_Ctrl[9].val[1] = 1; + state->Init_Ctrl[9].addr[2] = 76; + state->Init_Ctrl[9].bit[2] = 2; + state->Init_Ctrl[9].val[2] = 0; + state->Init_Ctrl[9].addr[3] = 76; + state->Init_Ctrl[9].bit[3] = 3; + state->Init_Ctrl[9].val[3] = 1; + + state->Init_Ctrl[10].Ctrl_Num = AGC_RF ; + state->Init_Ctrl[10].size = 4 ; + state->Init_Ctrl[10].addr[0] = 76; + state->Init_Ctrl[10].bit[0] = 4; + state->Init_Ctrl[10].val[0] = 1; + state->Init_Ctrl[10].addr[1] = 76; + state->Init_Ctrl[10].bit[1] = 5; + state->Init_Ctrl[10].val[1] = 1; + state->Init_Ctrl[10].addr[2] = 76; + state->Init_Ctrl[10].bit[2] = 6; + state->Init_Ctrl[10].val[2] = 0; + state->Init_Ctrl[10].addr[3] = 76; + state->Init_Ctrl[10].bit[3] = 7; + state->Init_Ctrl[10].val[3] = 1; + + state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ; + state->Init_Ctrl[11].size = 5 ; + state->Init_Ctrl[11].addr[0] = 43; + state->Init_Ctrl[11].bit[0] = 3; + state->Init_Ctrl[11].val[0] = 0; + state->Init_Ctrl[11].addr[1] = 43; + state->Init_Ctrl[11].bit[1] = 4; + state->Init_Ctrl[11].val[1] = 0; + state->Init_Ctrl[11].addr[2] = 43; + state->Init_Ctrl[11].bit[2] = 5; + state->Init_Ctrl[11].val[2] = 0; + state->Init_Ctrl[11].addr[3] = 43; + state->Init_Ctrl[11].bit[3] = 6; + state->Init_Ctrl[11].val[3] = 1; + state->Init_Ctrl[11].addr[4] = 43; + state->Init_Ctrl[11].bit[4] = 7; + state->Init_Ctrl[11].val[4] = 0; + + state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ; + state->Init_Ctrl[12].size = 6 ; + state->Init_Ctrl[12].addr[0] = 44; + state->Init_Ctrl[12].bit[0] = 2; + state->Init_Ctrl[12].val[0] = 0; + state->Init_Ctrl[12].addr[1] = 44; + state->Init_Ctrl[12].bit[1] = 3; + state->Init_Ctrl[12].val[1] = 0; + state->Init_Ctrl[12].addr[2] = 44; + state->Init_Ctrl[12].bit[2] = 4; + state->Init_Ctrl[12].val[2] = 0; + state->Init_Ctrl[12].addr[3] = 44; + state->Init_Ctrl[12].bit[3] = 5; + state->Init_Ctrl[12].val[3] = 1; + state->Init_Ctrl[12].addr[4] = 44; + state->Init_Ctrl[12].bit[4] = 6; + state->Init_Ctrl[12].val[4] = 0; + state->Init_Ctrl[12].addr[5] = 44; + state->Init_Ctrl[12].bit[5] = 7; + state->Init_Ctrl[12].val[5] = 0; + + state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ; + state->Init_Ctrl[13].size = 7 ; + state->Init_Ctrl[13].addr[0] = 11; + state->Init_Ctrl[13].bit[0] = 0; + state->Init_Ctrl[13].val[0] = 1; + state->Init_Ctrl[13].addr[1] = 11; + state->Init_Ctrl[13].bit[1] = 1; + state->Init_Ctrl[13].val[1] = 0; + state->Init_Ctrl[13].addr[2] = 11; + state->Init_Ctrl[13].bit[2] = 2; + state->Init_Ctrl[13].val[2] = 0; + state->Init_Ctrl[13].addr[3] = 11; + state->Init_Ctrl[13].bit[3] = 3; + state->Init_Ctrl[13].val[3] = 1; + state->Init_Ctrl[13].addr[4] = 11; + state->Init_Ctrl[13].bit[4] = 4; + state->Init_Ctrl[13].val[4] = 1; + state->Init_Ctrl[13].addr[5] = 11; + state->Init_Ctrl[13].bit[5] = 5; + state->Init_Ctrl[13].val[5] = 0; + state->Init_Ctrl[13].addr[6] = 11; + state->Init_Ctrl[13].bit[6] = 6; + state->Init_Ctrl[13].val[6] = 0; + + state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ; + state->Init_Ctrl[14].size = 16 ; + state->Init_Ctrl[14].addr[0] = 13; + state->Init_Ctrl[14].bit[0] = 0; + state->Init_Ctrl[14].val[0] = 0; + state->Init_Ctrl[14].addr[1] = 13; + state->Init_Ctrl[14].bit[1] = 1; + state->Init_Ctrl[14].val[1] = 0; + state->Init_Ctrl[14].addr[2] = 13; + state->Init_Ctrl[14].bit[2] = 2; + state->Init_Ctrl[14].val[2] = 0; + state->Init_Ctrl[14].addr[3] = 13; + state->Init_Ctrl[14].bit[3] = 3; + state->Init_Ctrl[14].val[3] = 0; + state->Init_Ctrl[14].addr[4] = 13; + state->Init_Ctrl[14].bit[4] = 4; + state->Init_Ctrl[14].val[4] = 0; + state->Init_Ctrl[14].addr[5] = 13; + state->Init_Ctrl[14].bit[5] = 5; + state->Init_Ctrl[14].val[5] = 0; + state->Init_Ctrl[14].addr[6] = 13; + state->Init_Ctrl[14].bit[6] = 6; + state->Init_Ctrl[14].val[6] = 0; + state->Init_Ctrl[14].addr[7] = 13; + state->Init_Ctrl[14].bit[7] = 7; + state->Init_Ctrl[14].val[7] = 0; + state->Init_Ctrl[14].addr[8] = 12; + state->Init_Ctrl[14].bit[8] = 0; + state->Init_Ctrl[14].val[8] = 0; + state->Init_Ctrl[14].addr[9] = 12; + state->Init_Ctrl[14].bit[9] = 1; + state->Init_Ctrl[14].val[9] = 0; + state->Init_Ctrl[14].addr[10] = 12; + state->Init_Ctrl[14].bit[10] = 2; + state->Init_Ctrl[14].val[10] = 0; + state->Init_Ctrl[14].addr[11] = 12; + state->Init_Ctrl[14].bit[11] = 3; + state->Init_Ctrl[14].val[11] = 0; + state->Init_Ctrl[14].addr[12] = 12; + state->Init_Ctrl[14].bit[12] = 4; + state->Init_Ctrl[14].val[12] = 0; + state->Init_Ctrl[14].addr[13] = 12; + state->Init_Ctrl[14].bit[13] = 5; + state->Init_Ctrl[14].val[13] = 1; + state->Init_Ctrl[14].addr[14] = 12; + state->Init_Ctrl[14].bit[14] = 6; + state->Init_Ctrl[14].val[14] = 1; + state->Init_Ctrl[14].addr[15] = 12; + state->Init_Ctrl[14].bit[15] = 7; + state->Init_Ctrl[14].val[15] = 0; + + state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ; + state->Init_Ctrl[15].size = 3 ; + state->Init_Ctrl[15].addr[0] = 147; + state->Init_Ctrl[15].bit[0] = 2; + state->Init_Ctrl[15].val[0] = 0; + state->Init_Ctrl[15].addr[1] = 147; + state->Init_Ctrl[15].bit[1] = 3; + state->Init_Ctrl[15].val[1] = 1; + state->Init_Ctrl[15].addr[2] = 147; + state->Init_Ctrl[15].bit[2] = 4; + state->Init_Ctrl[15].val[2] = 1; + + state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ; + state->Init_Ctrl[16].size = 2 ; + state->Init_Ctrl[16].addr[0] = 147; + state->Init_Ctrl[16].bit[0] = 0; + state->Init_Ctrl[16].val[0] = 0; + state->Init_Ctrl[16].addr[1] = 147; + state->Init_Ctrl[16].bit[1] = 1; + state->Init_Ctrl[16].val[1] = 1; + + state->Init_Ctrl[17].Ctrl_Num = EN_AAF ; + state->Init_Ctrl[17].size = 1 ; + state->Init_Ctrl[17].addr[0] = 147; + state->Init_Ctrl[17].bit[0] = 7; + state->Init_Ctrl[17].val[0] = 0; + + state->Init_Ctrl[18].Ctrl_Num = EN_3P ; + state->Init_Ctrl[18].size = 1 ; + state->Init_Ctrl[18].addr[0] = 147; + state->Init_Ctrl[18].bit[0] = 6; + state->Init_Ctrl[18].val[0] = 0; + + state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ; + state->Init_Ctrl[19].size = 1 ; + state->Init_Ctrl[19].addr[0] = 156; + state->Init_Ctrl[19].bit[0] = 0; + state->Init_Ctrl[19].val[0] = 0; + + state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ; + state->Init_Ctrl[20].size = 1 ; + state->Init_Ctrl[20].addr[0] = 147; + state->Init_Ctrl[20].bit[0] = 5; + state->Init_Ctrl[20].val[0] = 0; + + state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ; + state->Init_Ctrl[21].size = 1 ; + state->Init_Ctrl[21].addr[0] = 137; + state->Init_Ctrl[21].bit[0] = 4; + state->Init_Ctrl[21].val[0] = 0; + + state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ; + state->Init_Ctrl[22].size = 1 ; + state->Init_Ctrl[22].addr[0] = 137; + state->Init_Ctrl[22].bit[0] = 7; + state->Init_Ctrl[22].val[0] = 0; + + state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ; + state->Init_Ctrl[23].size = 1 ; + state->Init_Ctrl[23].addr[0] = 91; + state->Init_Ctrl[23].bit[0] = 5; + state->Init_Ctrl[23].val[0] = 1; + + state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ; + state->Init_Ctrl[24].size = 1 ; + state->Init_Ctrl[24].addr[0] = 43; + state->Init_Ctrl[24].bit[0] = 0; + state->Init_Ctrl[24].val[0] = 1; + + state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ; + state->Init_Ctrl[25].size = 2 ; + state->Init_Ctrl[25].addr[0] = 22; + state->Init_Ctrl[25].bit[0] = 0; + state->Init_Ctrl[25].val[0] = 1; + state->Init_Ctrl[25].addr[1] = 22; + state->Init_Ctrl[25].bit[1] = 1; + state->Init_Ctrl[25].val[1] = 1; + + state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ; + state->Init_Ctrl[26].size = 1 ; + state->Init_Ctrl[26].addr[0] = 134; + state->Init_Ctrl[26].bit[0] = 2; + state->Init_Ctrl[26].val[0] = 0; + + state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ; + state->Init_Ctrl[27].size = 1 ; + state->Init_Ctrl[27].addr[0] = 137; + state->Init_Ctrl[27].bit[0] = 3; + state->Init_Ctrl[27].val[0] = 0; + + state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ; + state->Init_Ctrl[28].size = 1 ; + state->Init_Ctrl[28].addr[0] = 77; + state->Init_Ctrl[28].bit[0] = 7; + state->Init_Ctrl[28].val[0] = 0; + + state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ; + state->Init_Ctrl[29].size = 1 ; + state->Init_Ctrl[29].addr[0] = 166; + state->Init_Ctrl[29].bit[0] = 7; + state->Init_Ctrl[29].val[0] = 1; + + state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ; + state->Init_Ctrl[30].size = 3 ; + state->Init_Ctrl[30].addr[0] = 166; + state->Init_Ctrl[30].bit[0] = 0; + state->Init_Ctrl[30].val[0] = 0; + state->Init_Ctrl[30].addr[1] = 166; + state->Init_Ctrl[30].bit[1] = 1; + state->Init_Ctrl[30].val[1] = 1; + state->Init_Ctrl[30].addr[2] = 166; + state->Init_Ctrl[30].bit[2] = 2; + state->Init_Ctrl[30].val[2] = 1; + + state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ; + state->Init_Ctrl[31].size = 3 ; + state->Init_Ctrl[31].addr[0] = 166; + state->Init_Ctrl[31].bit[0] = 3; + state->Init_Ctrl[31].val[0] = 1; + state->Init_Ctrl[31].addr[1] = 166; + state->Init_Ctrl[31].bit[1] = 4; + state->Init_Ctrl[31].val[1] = 0; + state->Init_Ctrl[31].addr[2] = 166; + state->Init_Ctrl[31].bit[2] = 5; + state->Init_Ctrl[31].val[2] = 1; + + state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ; + state->Init_Ctrl[32].size = 3 ; + state->Init_Ctrl[32].addr[0] = 167; + state->Init_Ctrl[32].bit[0] = 0; + state->Init_Ctrl[32].val[0] = 1; + state->Init_Ctrl[32].addr[1] = 167; + state->Init_Ctrl[32].bit[1] = 1; + state->Init_Ctrl[32].val[1] = 1; + state->Init_Ctrl[32].addr[2] = 167; + state->Init_Ctrl[32].bit[2] = 2; + state->Init_Ctrl[32].val[2] = 0; + + state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ; + state->Init_Ctrl[33].size = 4 ; + state->Init_Ctrl[33].addr[0] = 168; + state->Init_Ctrl[33].bit[0] = 0; + state->Init_Ctrl[33].val[0] = 0; + state->Init_Ctrl[33].addr[1] = 168; + state->Init_Ctrl[33].bit[1] = 1; + state->Init_Ctrl[33].val[1] = 1; + state->Init_Ctrl[33].addr[2] = 168; + state->Init_Ctrl[33].bit[2] = 2; + state->Init_Ctrl[33].val[2] = 0; + state->Init_Ctrl[33].addr[3] = 168; + state->Init_Ctrl[33].bit[3] = 3; + state->Init_Ctrl[33].val[3] = 0; + + state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ; + state->Init_Ctrl[34].size = 4 ; + state->Init_Ctrl[34].addr[0] = 168; + state->Init_Ctrl[34].bit[0] = 4; + state->Init_Ctrl[34].val[0] = 1; + state->Init_Ctrl[34].addr[1] = 168; + state->Init_Ctrl[34].bit[1] = 5; + state->Init_Ctrl[34].val[1] = 1; + state->Init_Ctrl[34].addr[2] = 168; + state->Init_Ctrl[34].bit[2] = 6; + state->Init_Ctrl[34].val[2] = 1; + state->Init_Ctrl[34].addr[3] = 168; + state->Init_Ctrl[34].bit[3] = 7; + state->Init_Ctrl[34].val[3] = 1; + + state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ; + state->Init_Ctrl[35].size = 1 ; + state->Init_Ctrl[35].addr[0] = 135; + state->Init_Ctrl[35].bit[0] = 0; + state->Init_Ctrl[35].val[0] = 0; + + state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ; + state->Init_Ctrl[36].size = 1 ; + state->Init_Ctrl[36].addr[0] = 56; + state->Init_Ctrl[36].bit[0] = 3; + state->Init_Ctrl[36].val[0] = 0; + + state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ; + state->Init_Ctrl[37].size = 7 ; + state->Init_Ctrl[37].addr[0] = 59; + state->Init_Ctrl[37].bit[0] = 1; + state->Init_Ctrl[37].val[0] = 0; + state->Init_Ctrl[37].addr[1] = 59; + state->Init_Ctrl[37].bit[1] = 2; + state->Init_Ctrl[37].val[1] = 0; + state->Init_Ctrl[37].addr[2] = 59; + state->Init_Ctrl[37].bit[2] = 3; + state->Init_Ctrl[37].val[2] = 0; + state->Init_Ctrl[37].addr[3] = 59; + state->Init_Ctrl[37].bit[3] = 4; + state->Init_Ctrl[37].val[3] = 0; + state->Init_Ctrl[37].addr[4] = 59; + state->Init_Ctrl[37].bit[4] = 5; + state->Init_Ctrl[37].val[4] = 0; + state->Init_Ctrl[37].addr[5] = 59; + state->Init_Ctrl[37].bit[5] = 6; + state->Init_Ctrl[37].val[5] = 0; + state->Init_Ctrl[37].addr[6] = 59; + state->Init_Ctrl[37].bit[6] = 7; + state->Init_Ctrl[37].val[6] = 0; + + state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ; + state->Init_Ctrl[38].size = 6 ; + state->Init_Ctrl[38].addr[0] = 32; + state->Init_Ctrl[38].bit[0] = 2; + state->Init_Ctrl[38].val[0] = 0; + state->Init_Ctrl[38].addr[1] = 32; + state->Init_Ctrl[38].bit[1] = 3; + state->Init_Ctrl[38].val[1] = 0; + state->Init_Ctrl[38].addr[2] = 32; + state->Init_Ctrl[38].bit[2] = 4; + state->Init_Ctrl[38].val[2] = 0; + state->Init_Ctrl[38].addr[3] = 32; + state->Init_Ctrl[38].bit[3] = 5; + state->Init_Ctrl[38].val[3] = 0; + state->Init_Ctrl[38].addr[4] = 32; + state->Init_Ctrl[38].bit[4] = 6; + state->Init_Ctrl[38].val[4] = 1; + state->Init_Ctrl[38].addr[5] = 32; + state->Init_Ctrl[38].bit[5] = 7; + state->Init_Ctrl[38].val[5] = 0; + + state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ; + state->Init_Ctrl[39].size = 1 ; + state->Init_Ctrl[39].addr[0] = 25; + state->Init_Ctrl[39].bit[0] = 3; + state->Init_Ctrl[39].val[0] = 1; + + + state->CH_Ctrl_Num = CHCTRL_NUM ; + + state->CH_Ctrl[0].Ctrl_Num = DN_POLY ; + state->CH_Ctrl[0].size = 2 ; + state->CH_Ctrl[0].addr[0] = 68; + state->CH_Ctrl[0].bit[0] = 6; + state->CH_Ctrl[0].val[0] = 1; + state->CH_Ctrl[0].addr[1] = 68; + state->CH_Ctrl[0].bit[1] = 7; + state->CH_Ctrl[0].val[1] = 1; + + state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ; + state->CH_Ctrl[1].size = 2 ; + state->CH_Ctrl[1].addr[0] = 70; + state->CH_Ctrl[1].bit[0] = 6; + state->CH_Ctrl[1].val[0] = 1; + state->CH_Ctrl[1].addr[1] = 70; + state->CH_Ctrl[1].bit[1] = 7; + state->CH_Ctrl[1].val[1] = 0; + + state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ; + state->CH_Ctrl[2].size = 9 ; + state->CH_Ctrl[2].addr[0] = 69; + state->CH_Ctrl[2].bit[0] = 5; + state->CH_Ctrl[2].val[0] = 0; + state->CH_Ctrl[2].addr[1] = 69; + state->CH_Ctrl[2].bit[1] = 6; + state->CH_Ctrl[2].val[1] = 0; + state->CH_Ctrl[2].addr[2] = 69; + state->CH_Ctrl[2].bit[2] = 7; + state->CH_Ctrl[2].val[2] = 0; + state->CH_Ctrl[2].addr[3] = 68; + state->CH_Ctrl[2].bit[3] = 0; + state->CH_Ctrl[2].val[3] = 0; + state->CH_Ctrl[2].addr[4] = 68; + state->CH_Ctrl[2].bit[4] = 1; + state->CH_Ctrl[2].val[4] = 0; + state->CH_Ctrl[2].addr[5] = 68; + state->CH_Ctrl[2].bit[5] = 2; + state->CH_Ctrl[2].val[5] = 0; + state->CH_Ctrl[2].addr[6] = 68; + state->CH_Ctrl[2].bit[6] = 3; + state->CH_Ctrl[2].val[6] = 0; + state->CH_Ctrl[2].addr[7] = 68; + state->CH_Ctrl[2].bit[7] = 4; + state->CH_Ctrl[2].val[7] = 0; + state->CH_Ctrl[2].addr[8] = 68; + state->CH_Ctrl[2].bit[8] = 5; + state->CH_Ctrl[2].val[8] = 0; + + state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ; + state->CH_Ctrl[3].size = 1 ; + state->CH_Ctrl[3].addr[0] = 70; + state->CH_Ctrl[3].bit[0] = 5; + state->CH_Ctrl[3].val[0] = 0; + + state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ; + state->CH_Ctrl[4].size = 3 ; + state->CH_Ctrl[4].addr[0] = 73; + state->CH_Ctrl[4].bit[0] = 4; + state->CH_Ctrl[4].val[0] = 0; + state->CH_Ctrl[4].addr[1] = 73; + state->CH_Ctrl[4].bit[1] = 5; + state->CH_Ctrl[4].val[1] = 1; + state->CH_Ctrl[4].addr[2] = 73; + state->CH_Ctrl[4].bit[2] = 6; + state->CH_Ctrl[4].val[2] = 0; + + state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ; + state->CH_Ctrl[5].size = 4 ; + state->CH_Ctrl[5].addr[0] = 70; + state->CH_Ctrl[5].bit[0] = 0; + state->CH_Ctrl[5].val[0] = 0; + state->CH_Ctrl[5].addr[1] = 70; + state->CH_Ctrl[5].bit[1] = 1; + state->CH_Ctrl[5].val[1] = 0; + state->CH_Ctrl[5].addr[2] = 70; + state->CH_Ctrl[5].bit[2] = 2; + state->CH_Ctrl[5].val[2] = 0; + state->CH_Ctrl[5].addr[3] = 70; + state->CH_Ctrl[5].bit[3] = 3; + state->CH_Ctrl[5].val[3] = 0; + + state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ; + state->CH_Ctrl[6].size = 1 ; + state->CH_Ctrl[6].addr[0] = 70; + state->CH_Ctrl[6].bit[0] = 4; + state->CH_Ctrl[6].val[0] = 1; + + state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ; + state->CH_Ctrl[7].size = 1 ; + state->CH_Ctrl[7].addr[0] = 111; + state->CH_Ctrl[7].bit[0] = 4; + state->CH_Ctrl[7].val[0] = 0; + + state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ; + state->CH_Ctrl[8].size = 1 ; + state->CH_Ctrl[8].addr[0] = 111; + state->CH_Ctrl[8].bit[0] = 7; + state->CH_Ctrl[8].val[0] = 1; + + state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ; + state->CH_Ctrl[9].size = 1 ; + state->CH_Ctrl[9].addr[0] = 111; + state->CH_Ctrl[9].bit[0] = 6; + state->CH_Ctrl[9].val[0] = 1; + + state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ; + state->CH_Ctrl[10].size = 1 ; + state->CH_Ctrl[10].addr[0] = 111; + state->CH_Ctrl[10].bit[0] = 5; + state->CH_Ctrl[10].val[0] = 0; + + state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ; + state->CH_Ctrl[11].size = 2 ; + state->CH_Ctrl[11].addr[0] = 110; + state->CH_Ctrl[11].bit[0] = 0; + state->CH_Ctrl[11].val[0] = 1; + state->CH_Ctrl[11].addr[1] = 110; + state->CH_Ctrl[11].bit[1] = 1; + state->CH_Ctrl[11].val[1] = 0; + + state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ; + state->CH_Ctrl[12].size = 3 ; + state->CH_Ctrl[12].addr[0] = 69; + state->CH_Ctrl[12].bit[0] = 2; + state->CH_Ctrl[12].val[0] = 0; + state->CH_Ctrl[12].addr[1] = 69; + state->CH_Ctrl[12].bit[1] = 3; + state->CH_Ctrl[12].val[1] = 0; + state->CH_Ctrl[12].addr[2] = 69; + state->CH_Ctrl[12].bit[2] = 4; + state->CH_Ctrl[12].val[2] = 0; + + state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ; + state->CH_Ctrl[13].size = 6 ; + state->CH_Ctrl[13].addr[0] = 110; + state->CH_Ctrl[13].bit[0] = 2; + state->CH_Ctrl[13].val[0] = 0; + state->CH_Ctrl[13].addr[1] = 110; + state->CH_Ctrl[13].bit[1] = 3; + state->CH_Ctrl[13].val[1] = 0; + state->CH_Ctrl[13].addr[2] = 110; + state->CH_Ctrl[13].bit[2] = 4; + state->CH_Ctrl[13].val[2] = 0; + state->CH_Ctrl[13].addr[3] = 110; + state->CH_Ctrl[13].bit[3] = 5; + state->CH_Ctrl[13].val[3] = 0; + state->CH_Ctrl[13].addr[4] = 110; + state->CH_Ctrl[13].bit[4] = 6; + state->CH_Ctrl[13].val[4] = 0; + state->CH_Ctrl[13].addr[5] = 110; + state->CH_Ctrl[13].bit[5] = 7; + state->CH_Ctrl[13].val[5] = 1; + + state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ; + state->CH_Ctrl[14].size = 7 ; + state->CH_Ctrl[14].addr[0] = 14; + state->CH_Ctrl[14].bit[0] = 0; + state->CH_Ctrl[14].val[0] = 0; + state->CH_Ctrl[14].addr[1] = 14; + state->CH_Ctrl[14].bit[1] = 1; + state->CH_Ctrl[14].val[1] = 0; + state->CH_Ctrl[14].addr[2] = 14; + state->CH_Ctrl[14].bit[2] = 2; + state->CH_Ctrl[14].val[2] = 0; + state->CH_Ctrl[14].addr[3] = 14; + state->CH_Ctrl[14].bit[3] = 3; + state->CH_Ctrl[14].val[3] = 0; + state->CH_Ctrl[14].addr[4] = 14; + state->CH_Ctrl[14].bit[4] = 4; + state->CH_Ctrl[14].val[4] = 0; + state->CH_Ctrl[14].addr[5] = 14; + state->CH_Ctrl[14].bit[5] = 5; + state->CH_Ctrl[14].val[5] = 0; + state->CH_Ctrl[14].addr[6] = 14; + state->CH_Ctrl[14].bit[6] = 6; + state->CH_Ctrl[14].val[6] = 0; + + state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ; + state->CH_Ctrl[15].size = 18 ; + state->CH_Ctrl[15].addr[0] = 17; + state->CH_Ctrl[15].bit[0] = 6; + state->CH_Ctrl[15].val[0] = 0; + state->CH_Ctrl[15].addr[1] = 17; + state->CH_Ctrl[15].bit[1] = 7; + state->CH_Ctrl[15].val[1] = 0; + state->CH_Ctrl[15].addr[2] = 16; + state->CH_Ctrl[15].bit[2] = 0; + state->CH_Ctrl[15].val[2] = 0; + state->CH_Ctrl[15].addr[3] = 16; + state->CH_Ctrl[15].bit[3] = 1; + state->CH_Ctrl[15].val[3] = 0; + state->CH_Ctrl[15].addr[4] = 16; + state->CH_Ctrl[15].bit[4] = 2; + state->CH_Ctrl[15].val[4] = 0; + state->CH_Ctrl[15].addr[5] = 16; + state->CH_Ctrl[15].bit[5] = 3; + state->CH_Ctrl[15].val[5] = 0; + state->CH_Ctrl[15].addr[6] = 16; + state->CH_Ctrl[15].bit[6] = 4; + state->CH_Ctrl[15].val[6] = 0; + state->CH_Ctrl[15].addr[7] = 16; + state->CH_Ctrl[15].bit[7] = 5; + state->CH_Ctrl[15].val[7] = 0; + state->CH_Ctrl[15].addr[8] = 16; + state->CH_Ctrl[15].bit[8] = 6; + state->CH_Ctrl[15].val[8] = 0; + state->CH_Ctrl[15].addr[9] = 16; + state->CH_Ctrl[15].bit[9] = 7; + state->CH_Ctrl[15].val[9] = 0; + state->CH_Ctrl[15].addr[10] = 15; + state->CH_Ctrl[15].bit[10] = 0; + state->CH_Ctrl[15].val[10] = 0; + state->CH_Ctrl[15].addr[11] = 15; + state->CH_Ctrl[15].bit[11] = 1; + state->CH_Ctrl[15].val[11] = 0; + state->CH_Ctrl[15].addr[12] = 15; + state->CH_Ctrl[15].bit[12] = 2; + state->CH_Ctrl[15].val[12] = 0; + state->CH_Ctrl[15].addr[13] = 15; + state->CH_Ctrl[15].bit[13] = 3; + state->CH_Ctrl[15].val[13] = 0; + state->CH_Ctrl[15].addr[14] = 15; + state->CH_Ctrl[15].bit[14] = 4; + state->CH_Ctrl[15].val[14] = 0; + state->CH_Ctrl[15].addr[15] = 15; + state->CH_Ctrl[15].bit[15] = 5; + state->CH_Ctrl[15].val[15] = 0; + state->CH_Ctrl[15].addr[16] = 15; + state->CH_Ctrl[15].bit[16] = 6; + state->CH_Ctrl[15].val[16] = 1; + state->CH_Ctrl[15].addr[17] = 15; + state->CH_Ctrl[15].bit[17] = 7; + state->CH_Ctrl[15].val[17] = 1; + + state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ; + state->CH_Ctrl[16].size = 5 ; + state->CH_Ctrl[16].addr[0] = 112; + state->CH_Ctrl[16].bit[0] = 0; + state->CH_Ctrl[16].val[0] = 0; + state->CH_Ctrl[16].addr[1] = 112; + state->CH_Ctrl[16].bit[1] = 1; + state->CH_Ctrl[16].val[1] = 0; + state->CH_Ctrl[16].addr[2] = 112; + state->CH_Ctrl[16].bit[2] = 2; + state->CH_Ctrl[16].val[2] = 0; + state->CH_Ctrl[16].addr[3] = 112; + state->CH_Ctrl[16].bit[3] = 3; + state->CH_Ctrl[16].val[3] = 0; + state->CH_Ctrl[16].addr[4] = 112; + state->CH_Ctrl[16].bit[4] = 4; + state->CH_Ctrl[16].val[4] = 1; + + state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ; + state->CH_Ctrl[17].size = 1 ; + state->CH_Ctrl[17].addr[0] = 14; + state->CH_Ctrl[17].bit[0] = 7; + state->CH_Ctrl[17].val[0] = 0; + + state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ; + state->CH_Ctrl[18].size = 4 ; + state->CH_Ctrl[18].addr[0] = 107; + state->CH_Ctrl[18].bit[0] = 3; + state->CH_Ctrl[18].val[0] = 0; + state->CH_Ctrl[18].addr[1] = 107; + state->CH_Ctrl[18].bit[1] = 4; + state->CH_Ctrl[18].val[1] = 0; + state->CH_Ctrl[18].addr[2] = 107; + state->CH_Ctrl[18].bit[2] = 5; + state->CH_Ctrl[18].val[2] = 0; + state->CH_Ctrl[18].addr[3] = 107; + state->CH_Ctrl[18].bit[3] = 6; + state->CH_Ctrl[18].val[3] = 0; + + state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ; + state->CH_Ctrl[19].size = 3 ; + state->CH_Ctrl[19].addr[0] = 107; + state->CH_Ctrl[19].bit[0] = 7; + state->CH_Ctrl[19].val[0] = 1; + state->CH_Ctrl[19].addr[1] = 106; + state->CH_Ctrl[19].bit[1] = 0; + state->CH_Ctrl[19].val[1] = 1; + state->CH_Ctrl[19].addr[2] = 106; + state->CH_Ctrl[19].bit[2] = 1; + state->CH_Ctrl[19].val[2] = 1; + + state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ; + state->CH_Ctrl[20].size = 11 ; + state->CH_Ctrl[20].addr[0] = 109; + state->CH_Ctrl[20].bit[0] = 2; + state->CH_Ctrl[20].val[0] = 0; + state->CH_Ctrl[20].addr[1] = 109; + state->CH_Ctrl[20].bit[1] = 3; + state->CH_Ctrl[20].val[1] = 0; + state->CH_Ctrl[20].addr[2] = 109; + state->CH_Ctrl[20].bit[2] = 4; + state->CH_Ctrl[20].val[2] = 0; + state->CH_Ctrl[20].addr[3] = 109; + state->CH_Ctrl[20].bit[3] = 5; + state->CH_Ctrl[20].val[3] = 0; + state->CH_Ctrl[20].addr[4] = 109; + state->CH_Ctrl[20].bit[4] = 6; + state->CH_Ctrl[20].val[4] = 0; + state->CH_Ctrl[20].addr[5] = 109; + state->CH_Ctrl[20].bit[5] = 7; + state->CH_Ctrl[20].val[5] = 0; + state->CH_Ctrl[20].addr[6] = 108; + state->CH_Ctrl[20].bit[6] = 0; + state->CH_Ctrl[20].val[6] = 0; + state->CH_Ctrl[20].addr[7] = 108; + state->CH_Ctrl[20].bit[7] = 1; + state->CH_Ctrl[20].val[7] = 0; + state->CH_Ctrl[20].addr[8] = 108; + state->CH_Ctrl[20].bit[8] = 2; + state->CH_Ctrl[20].val[8] = 1; + state->CH_Ctrl[20].addr[9] = 108; + state->CH_Ctrl[20].bit[9] = 3; + state->CH_Ctrl[20].val[9] = 1; + state->CH_Ctrl[20].addr[10] = 108; + state->CH_Ctrl[20].bit[10] = 4; + state->CH_Ctrl[20].val[10] = 1; + + state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ; + state->CH_Ctrl[21].size = 6 ; + state->CH_Ctrl[21].addr[0] = 106; + state->CH_Ctrl[21].bit[0] = 2; + state->CH_Ctrl[21].val[0] = 0; + state->CH_Ctrl[21].addr[1] = 106; + state->CH_Ctrl[21].bit[1] = 3; + state->CH_Ctrl[21].val[1] = 0; + state->CH_Ctrl[21].addr[2] = 106; + state->CH_Ctrl[21].bit[2] = 4; + state->CH_Ctrl[21].val[2] = 0; + state->CH_Ctrl[21].addr[3] = 106; + state->CH_Ctrl[21].bit[3] = 5; + state->CH_Ctrl[21].val[3] = 0; + state->CH_Ctrl[21].addr[4] = 106; + state->CH_Ctrl[21].bit[4] = 6; + state->CH_Ctrl[21].val[4] = 0; + state->CH_Ctrl[21].addr[5] = 106; + state->CH_Ctrl[21].bit[5] = 7; + state->CH_Ctrl[21].val[5] = 1; + + state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ; + state->CH_Ctrl[22].size = 1 ; + state->CH_Ctrl[22].addr[0] = 138; + state->CH_Ctrl[22].bit[0] = 4; + state->CH_Ctrl[22].val[0] = 1; + + state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ; + state->CH_Ctrl[23].size = 1 ; + state->CH_Ctrl[23].addr[0] = 17; + state->CH_Ctrl[23].bit[0] = 5; + state->CH_Ctrl[23].val[0] = 0; + + state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ; + state->CH_Ctrl[24].size = 1 ; + state->CH_Ctrl[24].addr[0] = 111; + state->CH_Ctrl[24].bit[0] = 3; + state->CH_Ctrl[24].val[0] = 0; + + state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ; + state->CH_Ctrl[25].size = 1 ; + state->CH_Ctrl[25].addr[0] = 112; + state->CH_Ctrl[25].bit[0] = 7; + state->CH_Ctrl[25].val[0] = 0; + + state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ; + state->CH_Ctrl[26].size = 1 ; + state->CH_Ctrl[26].addr[0] = 136; + state->CH_Ctrl[26].bit[0] = 7; + state->CH_Ctrl[26].val[0] = 0; + + state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ; + state->CH_Ctrl[27].size = 1 ; + state->CH_Ctrl[27].addr[0] = 149; + state->CH_Ctrl[27].bit[0] = 7; + state->CH_Ctrl[27].val[0] = 0; + + state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ; + state->CH_Ctrl[28].size = 1 ; + state->CH_Ctrl[28].addr[0] = 149; + state->CH_Ctrl[28].bit[0] = 6; + state->CH_Ctrl[28].val[0] = 0; + + state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ; + state->CH_Ctrl[29].size = 1 ; + state->CH_Ctrl[29].addr[0] = 149; + state->CH_Ctrl[29].bit[0] = 5; + state->CH_Ctrl[29].val[0] = 1; + + state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ; + state->CH_Ctrl[30].size = 1 ; + state->CH_Ctrl[30].addr[0] = 149; + state->CH_Ctrl[30].bit[0] = 4; + state->CH_Ctrl[30].val[0] = 1; + + state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ; + state->CH_Ctrl[31].size = 1 ; + state->CH_Ctrl[31].addr[0] = 149; + state->CH_Ctrl[31].bit[0] = 3; + state->CH_Ctrl[31].val[0] = 0; + + state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ; + state->CH_Ctrl[32].size = 1 ; + state->CH_Ctrl[32].addr[0] = 93; + state->CH_Ctrl[32].bit[0] = 1; + state->CH_Ctrl[32].val[0] = 0; + + state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ; + state->CH_Ctrl[33].size = 1 ; + state->CH_Ctrl[33].addr[0] = 93; + state->CH_Ctrl[33].bit[0] = 0; + state->CH_Ctrl[33].val[0] = 0; + + state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ; + state->CH_Ctrl[34].size = 6 ; + state->CH_Ctrl[34].addr[0] = 92; + state->CH_Ctrl[34].bit[0] = 2; + state->CH_Ctrl[34].val[0] = 0; + state->CH_Ctrl[34].addr[1] = 92; + state->CH_Ctrl[34].bit[1] = 3; + state->CH_Ctrl[34].val[1] = 0; + state->CH_Ctrl[34].addr[2] = 92; + state->CH_Ctrl[34].bit[2] = 4; + state->CH_Ctrl[34].val[2] = 0; + state->CH_Ctrl[34].addr[3] = 92; + state->CH_Ctrl[34].bit[3] = 5; + state->CH_Ctrl[34].val[3] = 0; + state->CH_Ctrl[34].addr[4] = 92; + state->CH_Ctrl[34].bit[4] = 6; + state->CH_Ctrl[34].val[4] = 0; + state->CH_Ctrl[34].addr[5] = 92; + state->CH_Ctrl[34].bit[5] = 7; + state->CH_Ctrl[34].val[5] = 0; + + state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ; + state->CH_Ctrl[35].size = 6 ; + state->CH_Ctrl[35].addr[0] = 93; + state->CH_Ctrl[35].bit[0] = 2; + state->CH_Ctrl[35].val[0] = 0; + state->CH_Ctrl[35].addr[1] = 93; + state->CH_Ctrl[35].bit[1] = 3; + state->CH_Ctrl[35].val[1] = 0; + state->CH_Ctrl[35].addr[2] = 93; + state->CH_Ctrl[35].bit[2] = 4; + state->CH_Ctrl[35].val[2] = 0; + state->CH_Ctrl[35].addr[3] = 93; + state->CH_Ctrl[35].bit[3] = 5; + state->CH_Ctrl[35].val[3] = 0; + state->CH_Ctrl[35].addr[4] = 93; + state->CH_Ctrl[35].bit[4] = 6; + state->CH_Ctrl[35].val[4] = 0; + state->CH_Ctrl[35].addr[5] = 93; + state->CH_Ctrl[35].bit[5] = 7; + state->CH_Ctrl[35].val[5] = 0; #ifdef _MXL_PRODUCTION - Tuner->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ; - Tuner->CH_Ctrl[36].size = 1 ; - Tuner->CH_Ctrl[36].addr[0] = 109; - Tuner->CH_Ctrl[36].bit[0] = 1; - Tuner->CH_Ctrl[36].val[0] = 1; - - Tuner->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ; - Tuner->CH_Ctrl[37].size = 2 ; - Tuner->CH_Ctrl[37].addr[0] = 112; - Tuner->CH_Ctrl[37].bit[0] = 5; - Tuner->CH_Ctrl[37].val[0] = 0; - Tuner->CH_Ctrl[37].addr[1] = 112; - Tuner->CH_Ctrl[37].bit[1] = 6; - Tuner->CH_Ctrl[37].val[1] = 0; - - Tuner->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ; - Tuner->CH_Ctrl[38].size = 1 ; - Tuner->CH_Ctrl[38].addr[0] = 65; - Tuner->CH_Ctrl[38].bit[0] = 1; - Tuner->CH_Ctrl[38].val[0] = 0; + state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ; + state->CH_Ctrl[36].size = 1 ; + state->CH_Ctrl[36].addr[0] = 109; + state->CH_Ctrl[36].bit[0] = 1; + state->CH_Ctrl[36].val[0] = 1; + + state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ; + state->CH_Ctrl[37].size = 2 ; + state->CH_Ctrl[37].addr[0] = 112; + state->CH_Ctrl[37].bit[0] = 5; + state->CH_Ctrl[37].val[0] = 0; + state->CH_Ctrl[37].addr[1] = 112; + state->CH_Ctrl[37].bit[1] = 6; + state->CH_Ctrl[37].val[1] = 0; + + state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ; + state->CH_Ctrl[38].size = 1 ; + state->CH_Ctrl[38].addr[0] = 65; + state->CH_Ctrl[38].bit[0] = 1; + state->CH_Ctrl[38].val[0] = 0; #endif return 0 ; @@ -1832,13 +1681,14 @@ u16 MXL5005_ControlInit(Tuner_struct *Tuner) // MaxLinear source code - MXL5005_c.cpp // MXL5005.cpp : Defines the initialization routines for the DLL. // 2.6.12 - -void InitTunerControls(Tuner_struct *Tuner) +// DONE +void InitTunerControls(struct dvb_frontend *fe) { - MXL5005_RegisterInit(Tuner) ; - MXL5005_ControlInit(Tuner) ; + struct mxl5005s_state *state = fe->demodulator_priv; + MXL5005_RegisterInit(fe); + MXL5005_ControlInit(fe); #ifdef _MXL_INTERNAL - MXL5005_MXLControlInit(Tuner) ; + MXL5005_MXLControlInit(fe); #endif } @@ -1857,15 +1707,15 @@ void InitTunerControls(Tuner_struct *Tuner) // Tuner_struct: structure defined at higher level // // Mode: Tuner Mode (Analog/Digital) // // IF_Mode: IF Mode ( Zero/Low ) // -// Bandwidth: Filter Channel Bandwidth (in Hz) // +// Bandwidth: Filter Channel Bandwidth (in Hz) // // IF_out: Desired IF out Frequency (in Hz) // // Fxtal: Crystal Frerquency (in Hz) // -// TOP: 0: Dual AGC; Value: take over point // -// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // -// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // -// DIV_OUT: 0: Div-1; 1: Div-4 // -// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // -// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // +// TOP: 0: Dual AGC; Value: take over point // +// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // +// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // +// DIV_OUT: 0: Div-1; 1: Div-4 // +// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // +// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // // // // Outputs: // // Tuner // @@ -1875,49 +1725,51 @@ void InitTunerControls(Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL5005_TunerConfig(Tuner_struct *Tuner, - u8 Mode, // 0: Analog Mode ; 1: Digital Mode - u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF - u32 Bandwidth, // filter channel bandwidth (6, 7, 8) - u32 IF_out, // Desired IF Out Frequency - u32 Fxtal, // XTAL Frequency - u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 - u16 TOP, // 0: Dual AGC; Value: take over point - u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms) - u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out - u8 DIV_OUT, // 0: Div-1; 1: Div-4 - u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable - u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI - u8 Mod_Type, // Modulation Type; - // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable - u8 TF_Type // Tracking Filter - // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H +// DONE +u16 MXL5005_TunerConfig(struct dvb_frontend *fe, + u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ + u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ + u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ + u32 IF_out, /* Desired IF Out Frequency */ + u32 Fxtal, /* XTAL Frequency */ + u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ + u16 TOP, /* 0: Dual AGC; Value: take over point */ + u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ + u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */ + u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */ + u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ + u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ + u8 Mod_Type, /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 TF_Type /* Tracking Filter */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ ) { - u16 status = 0 ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; - Tuner->Mode = Mode ; - Tuner->IF_Mode = IF_mode ; - Tuner->Chan_Bandwidth = Bandwidth ; - Tuner->IF_OUT = IF_out ; - Tuner->Fxtal = Fxtal ; - Tuner->AGC_Mode = AGC_Mode ; - Tuner->TOP = TOP ; - Tuner->IF_OUT_LOAD = IF_OUT_LOAD ; - Tuner->CLOCK_OUT = CLOCK_OUT ; - Tuner->DIV_OUT = DIV_OUT ; - Tuner->CAPSELECT = CAPSELECT ; - Tuner->EN_RSSI = EN_RSSI ; - Tuner->Mod_Type = Mod_Type ; - Tuner->TF_Type = TF_Type ; + state->Mode = Mode; + state->IF_Mode = IF_mode; + state->Chan_Bandwidth = Bandwidth; + state->IF_OUT = IF_out; + state->Fxtal = Fxtal; + state->AGC_Mode = AGC_Mode; + state->TOP = TOP; + state->IF_OUT_LOAD = IF_OUT_LOAD; + state->CLOCK_OUT = CLOCK_OUT; + state->DIV_OUT = DIV_OUT; + state->CAPSELECT = CAPSELECT; + state->EN_RSSI = EN_RSSI; + state->Mod_Type = Mod_Type; + state->TF_Type = TF_Type; /* Initialize all the controls and registers */ - InitTunerControls (Tuner) ; + InitTunerControls(fe); /* Synthesizer LO frequency calculation */ - MXL_SynthIFLO_Calc( Tuner ) ; + MXL_SynthIFLO_Calc(fe); - return status ; + return status; } /////////////////////////////////////////////////////////////////////////////// @@ -1943,22 +1795,18 @@ u16 MXL5005_TunerConfig(Tuner_struct *Tuner, // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) +// DONE +void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { - if (Tuner->Mode == 1) // Digital Mode - { - Tuner->IF_LO = Tuner->IF_OUT ; - } - else // Analog Mode + struct mxl5005s_state *state = fe->demodulator_priv; + if (Tuner->Mode == 1) /* Digital Mode */ + state->IF_LO = state->IF_OUT; + else /* Analog Mode */ { - if(Tuner->IF_Mode == 0) // Analog Zero IF mode - { - Tuner->IF_LO = Tuner->IF_OUT + 400000 ; - } - else // Analog Low IF mode - { - Tuner->IF_LO = Tuner->IF_OUT + Tuner->Chan_Bandwidth/2 ; - } + if(state->IF_Mode == 0) /* Analog Zero IF mode */ + state->IF_LO = state->IF_OUT + 400000; + else /* Analog Low IF mode */ + state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2; } } @@ -1986,25 +1834,22 @@ void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) +// DONE +void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { - if (Tuner->Mode == 1) // Digital Mode - { + struct mxl5005s_state *state = fe->demodulator_priv; + + if (state->Mode == 1) /* Digital Mode */ { //remove 20.48MHz setting for 2.6.10 - Tuner->RF_LO = Tuner->RF_IN ; - Tuner->TG_LO = Tuner->RF_IN - 750000 ; //change for 2.6.6 - } - else // Analog Mode - { - if(Tuner->IF_Mode == 0) // Analog Zero IF mode - { - Tuner->RF_LO = Tuner->RF_IN - 400000 ; - Tuner->TG_LO = Tuner->RF_IN - 1750000 ; - } - else // Analog Low IF mode - { - Tuner->RF_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth/2 ; - Tuner->TG_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth + 500000 ; + state->RF_LO = state->RF_IN; + state->TG_LO = state->RF_IN - 750000; //change for 2.6.6 + } else /* Analog Mode */ { + if(state->IF_Mode == 0) /* Analog Zero IF mode */ { + state->RF_LO = state->RF_IN - 400000; + state->TG_LO = state->RF_IN - 1750000; + } else /* Analog Low IF mode */ { + state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2; + state->TG_LO = state->RF_IN - state->Chan_Bandwidth + 500000; } } } @@ -2028,16 +1873,18 @@ void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) +// DONE +u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { - u16 status = 0 ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; - status += MXL_ControlWrite(Tuner, OVERRIDE_1, 1) ; - status += MXL_ControlWrite(Tuner, OVERRIDE_2, 1) ; - status += MXL_ControlWrite(Tuner, OVERRIDE_3, 1) ; - status += MXL_ControlWrite(Tuner, OVERRIDE_4, 1) ; + status += MXL_ControlWrite(fe, OVERRIDE_1, 1); + status += MXL_ControlWrite(fe, OVERRIDE_2, 1); + status += MXL_ControlWrite(fe, OVERRIDE_3, 1); + status += MXL_ControlWrite(fe, OVERRIDE_4, 1); - return status ; + return status; } /////////////////////////////////////////////////////////////////////////////// @@ -2065,363 +1912,338 @@ u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_BlockInit( Tuner_struct *Tuner ) +// DONE +u16 MXL_BlockInit(struct dvb_frontend *fe) { - u16 status = 0 ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; - status += MXL_OverwriteICDefault(Tuner) ; + status += MXL_OverwriteICDefault(fe); - // - // Downconverter Control - // Dig Ana - status += MXL_ControlWrite(Tuner, DN_IQTN_AMP_CUT, Tuner->Mode ? 1 : 0) ; + /* Downconverter Control Dig Ana */ + status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0); - // - // Filter Control - // Dig Ana - status += MXL_ControlWrite(Tuner, BB_MODE, Tuner->Mode ? 0 : 1) ; - status += MXL_ControlWrite(Tuner, BB_BUF, Tuner->Mode ? 3 : 2) ; - status += MXL_ControlWrite(Tuner, BB_BUF_OA, Tuner->Mode ? 1 : 0) ; - - status += MXL_ControlWrite(Tuner, BB_IQSWAP, Tuner->Mode ? 0 : 1) ; - status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 0) ; - - // Initialize Low-Pass Filter - if (Tuner->Mode) { // Digital Mode - switch (Tuner->Chan_Bandwidth) { + /* Filter Control Dig Ana */ + status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1); + status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2); + status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0); + status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1); + status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0); + + /* Initialize Low-Pass Filter */ + if (state->Mode) { /* Digital Mode */ + switch (state->Chan_Bandwidth) { case 8000000: - status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 0) ; - break ; + status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0); + break; case 7000000: - status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 2) ; - break ; + status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); + break; case 6000000: - status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 3) ; - break ; - } - } else { // Analog Mode - switch (Tuner->Chan_Bandwidth) { - case 8000000: // Low Zero - status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 0 : 3)) ; - break ; + status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); + break; + } + } else { /* Analog Mode */ + switch (state->Chan_Bandwidth) { + case 8000000: /* Low Zero */ + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 0 : 3)); + break; case 7000000: - status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 1 : 4)) ; - break ; + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 1 : 4)); + break; case 6000000: - status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 2 : 5)) ; - break ; + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 2 : 5)); + break; } } - // - // Charge Pump Control - // Dig Ana - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, Tuner->Mode ? 5 : 8) ; - status += MXL_ControlWrite(Tuner, RFSYN_EN_CHP_HIGAIN, Tuner->Mode ? 1 : 1) ; - status += MXL_ControlWrite(Tuner, EN_CHP_LIN_B, Tuner->Mode ? 0 : 0) ; + /* Charge Pump Control Dig Ana */ + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8); + status += MXL_ControlWrite(fe, RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1); + status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0); - // - // AGC TOP Control - // - if (Tuner->AGC_Mode == 0) // Dual AGC - { - status += MXL_ControlWrite(Tuner, AGC_IF, 15) ; - status += MXL_ControlWrite(Tuner, AGC_RF, 15) ; + /* AGC TOP Control */ + if (state->AGC_Mode == 0) /* Dual AGC */ { + status += MXL_ControlWrite(fe, AGC_IF, 15); + status += MXL_ControlWrite(fe, AGC_RF, 15); } - else // Single AGC Mode Dig Ana - status += MXL_ControlWrite(Tuner, AGC_RF, Tuner->Mode? 15 : 12) ; + else /* Single AGC Mode Dig Ana */ + status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); - if (Tuner->TOP == 55) // TOP == 5.5 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x0) ; + if (state->TOP == 55) /* TOP == 5.5 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x0); - if (Tuner->TOP == 72) // TOP == 7.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x1) ; + if (state->TOP == 72) /* TOP == 7.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x1); - if (Tuner->TOP == 92) // TOP == 9.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x2) ; + if (state->TOP == 92) /* TOP == 9.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x2); - if (Tuner->TOP == 110) // TOP == 11.0 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x3) ; + if (state->TOP == 110) /* TOP == 11.0 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x3); - if (Tuner->TOP == 129) // TOP == 12.9 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x4) ; + if (state->TOP == 129) /* TOP == 12.9 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x4); - if (Tuner->TOP == 147) // TOP == 14.7 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x5) ; + if (state->TOP == 147) /* TOP == 14.7 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x5); - if (Tuner->TOP == 168) // TOP == 16.8 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x6) ; + if (state->TOP == 168) /* TOP == 16.8 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x6); - if (Tuner->TOP == 194) // TOP == 19.4 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x7) ; + if (state->TOP == 194) /* TOP == 19.4 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x7); - if (Tuner->TOP == 212) // TOP == 21.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x9) ; + if (state->TOP == 212) /* TOP == 21.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x9); - if (Tuner->TOP == 232) // TOP == 23.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xA) ; + if (state->TOP == 232) /* TOP == 23.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xA); - if (Tuner->TOP == 252) // TOP == 25.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xB) ; + if (state->TOP == 252) /* TOP == 25.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xB); - if (Tuner->TOP == 271) // TOP == 27.1 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xC) ; + if (state->TOP == 271) /* TOP == 27.1 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xC); - if (Tuner->TOP == 292) // TOP == 29.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xD) ; + if (state->TOP == 292) /* TOP == 29.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xD); - if (Tuner->TOP == 317) // TOP == 31.7 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xE) ; + if (state->TOP == 317) /* TOP == 31.7 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xE); - if (Tuner->TOP == 349) // TOP == 34.9 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xF) ; + if (state->TOP == 349) /* TOP == 34.9 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xF); - // - // IF Synthesizer Control - // - status += MXL_IFSynthInit( Tuner ) ; + /* IF Synthesizer Control */ + status += MXL_IFSynthInit(fe); - // - // IF UpConverter Control - if (Tuner->IF_OUT_LOAD == 200) - { - status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 6) ; - status += MXL_ControlWrite(Tuner, I_DRIVER, 2) ; + /* IF UpConverter Control */ + if (state->IF_OUT_LOAD == 200) { + status += MXL_ControlWrite(fe, DRV_RES_SEL, 6); + status += MXL_ControlWrite(fe, I_DRIVER, 2); } - if (Tuner->IF_OUT_LOAD == 300) - { - status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 4) ; - status += MXL_ControlWrite(Tuner, I_DRIVER, 1) ; + if (state->IF_OUT_LOAD == 300) { + status += MXL_ControlWrite(fe, DRV_RES_SEL, 4); + status += MXL_ControlWrite(fe, I_DRIVER, 1); } - // - // Anti-Alias Filtering Control - // - // initialise Anti-Aliasing Filter - if (Tuner->Mode) {// Digital Mode - if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 6280000UL) { - status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; - status += MXL_ControlWrite(Tuner, EN_3P, 1) ; - status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; - status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; - } - if ((Tuner->IF_OUT == 36125000UL) || (Tuner->IF_OUT == 36150000UL)) { - status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; - status += MXL_ControlWrite(Tuner, EN_3P, 1) ; - status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; - status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ; - } - if (Tuner->IF_OUT > 36150000UL) { - status += MXL_ControlWrite(Tuner, EN_AAF, 0) ; - status += MXL_ControlWrite(Tuner, EN_3P, 1) ; - status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; - status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ; - } - } else { // Analog Mode - if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 5000000UL) + /* Anti-Alias Filtering Control + * initialise Anti-Aliasing Filter + */ + if (state->Mode) { /* Digital Mode */ + if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) { + status += MXL_ControlWrite(fe, EN_AAF, 1); + status += MXL_ControlWrite(fe, EN_3P, 1); + status += MXL_ControlWrite(fe, EN_AUX_3P, 1); + status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); + } + if ((state->IF_OUT == 36125000UL) || (state->IF_OUT == 36150000UL)) { + status += MXL_ControlWrite(fe, EN_AAF, 1); + status += MXL_ControlWrite(fe, EN_3P, 1); + status += MXL_ControlWrite(fe, EN_AUX_3P, 1); + status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1); + } + if (state->IF_OUT > 36150000UL) { + status += MXL_ControlWrite(fe, EN_AAF, 0); + status += MXL_ControlWrite(fe, EN_3P, 1); + status += MXL_ControlWrite(fe, EN_AUX_3P, 1); + status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1); + } + } else { /* Analog Mode */ + if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) { - status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; - status += MXL_ControlWrite(Tuner, EN_3P, 1) ; - status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; - status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; + status += MXL_ControlWrite(fe, EN_AAF, 1); + status += MXL_ControlWrite(fe, EN_3P, 1); + status += MXL_ControlWrite(fe, EN_AUX_3P, 1); + status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); } - if (Tuner->IF_OUT > 5000000UL) + if (state->IF_OUT > 5000000UL) { - status += MXL_ControlWrite(Tuner, EN_AAF, 0) ; - status += MXL_ControlWrite(Tuner, EN_3P, 0) ; - status += MXL_ControlWrite(Tuner, EN_AUX_3P, 0) ; - status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; + status += MXL_ControlWrite(fe, EN_AAF, 0); + status += MXL_ControlWrite(fe, EN_3P, 0); + status += MXL_ControlWrite(fe, EN_AUX_3P, 0); + status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); } } - // - // Demod Clock Out - // - if (Tuner->CLOCK_OUT) - status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 1) ; + /* Demod Clock Out */ + if (state->CLOCK_OUT) + status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1); else - status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 0) ; + status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0); - if (Tuner->DIV_OUT == 1) - status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 1) ; - if (Tuner->DIV_OUT == 0) - status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 0) ; + if (state->DIV_OUT == 1) + status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1); + if (state->DIV_OUT == 0) + status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0); - // - // Crystal Control - // - if (Tuner->CAPSELECT) - status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 1) ; + /* Crystal Control */ + if (state->CAPSELECT) + status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1); else - status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 0) ; + status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0); - if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) - status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 1) ; - if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL) - status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 0) ; + if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL) + status += MXL_ControlWrite(fe, IF_SEL_DBL, 1); + if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) + status += MXL_ControlWrite(fe, IF_SEL_DBL, 0); - if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL) - status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 3) ; - if (Tuner->Fxtal > 22000000UL && Tuner->Fxtal <= 32000000UL) - status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 0) ; + if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL) + status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3); + if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL) + status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0); - // - // Misc Controls - // - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog LowIF mode - status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 0); + /* Misc Controls */ + if (state->Mode == 0 && Tuner->IF_Mode == 1) /* Analog LowIF mode */ + status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0); else - status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 1); + status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1); -// status += MXL_ControlRead(Tuner, IF_DIVVAL, &IF_DIVVAL_Val) ; + /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */ - // Set TG_R_DIV - status += MXL_ControlWrite(Tuner, TG_R_DIV, MXL_Ceiling(Tuner->Fxtal, 1000000)) ; + /* Set TG_R_DIV */ + status += MXL_ControlWrite(fe, TG_R_DIV, MXL_Ceiling(state->Fxtal, 1000000)); - // - // Apply Default value to BB_INITSTATE_DLPF_TUNE - // + /* Apply Default value to BB_INITSTATE_DLPF_TUNE */ - // - // RSSI Control - // - if(Tuner->EN_RSSI) + /* RSSI Control */ + if (state->EN_RSSI) { - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 3) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; - // TOP point - status += MXL_ControlWrite(Tuner, RFA_FLR, 0) ; - status += MXL_ControlWrite(Tuner, RFA_CEIL, 12) ; + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2); + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1); + + /* TOP point */ + status += MXL_ControlWrite(fe, RFA_FLR, 0); + status += MXL_ControlWrite(fe, RFA_CEIL, 12); } - // - // Modulation type bit settings - // Override the control values preset - // - if (Tuner->Mod_Type == MXL_DVBT) // DVB-T Mode + /* Modulation type bit settings + * Override the control values preset + */ + if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ { - Tuner->AGC_Mode = 1 ; // Single AGC Mode - - // Enable RSSI - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; - // TOP point - status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ; - status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ; - if (Tuner->IF_OUT <= 6280000UL) // Low IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; - else // High IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + state->AGC_Mode = 1; /* Single AGC Mode */ + + /* Enable RSSI */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1); + + /* TOP point */ + status += MXL_ControlWrite(fe, RFA_FLR, 2); + status += MXL_ControlWrite(fe, RFA_CEIL, 13); + if (state->IF_OUT <= 6280000UL) /* Low IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 0); + else /* High IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (Tuner->Mod_Type == MXL_ATSC) // ATSC Mode + if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ { - Tuner->AGC_Mode = 1 ; // Single AGC Mode - - // Enable RSSI - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 4) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; - // TOP point - status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ; - status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ; - - status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; // Low Zero - if (Tuner->IF_OUT <= 6280000UL) // Low IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; - else // High IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + Tuner->AGC_Mode = 1; /* Single AGC Mode */ + + /* Enable RSSI */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2); + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1); + + /* TOP point */ + status += MXL_ControlWrite(fe, RFA_FLR, 2); + status += MXL_ControlWrite(fe, RFA_CEIL, 13); + status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); /* Low Zero */ + if (state->IF_OUT <= 6280000UL) /* Low IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 0); + else /* High IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (Tuner->Mod_Type == MXL_QAM) // QAM Mode + if (state->Mod_Type == MXL_QAM) /* QAM Mode */ { - Tuner->Mode = MXL_DIGITAL_MODE; - - //Tuner->AGC_Mode = 1 ; // Single AGC Mode - - // Disable RSSI //change here for v2.6.5 - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - - // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; - - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; //change here for v2.6.5 - - if (Tuner->IF_OUT <= 6280000UL) // Low IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; - else // High IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + state->Mode = MXL_DIGITAL_MODE; + + /* state->AGC_Mode = 1; */ /* Single AGC Mode */ + + /* Disable RSSI */ /* change here for v2.6.5 */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); /* change here for v2.6.5 */ + + if (state->IF_OUT <= 6280000UL) /* Low IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 0); + else /* High IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (Tuner->Mod_Type == MXL_ANALOG_CABLE) // Analog Cable Mode - { - //Tuner->Mode = MXL_DIGITAL_MODE ; - Tuner->AGC_Mode = 1 ; // Single AGC Mode - - // Disable RSSI - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - - status += MXL_ControlWrite(Tuner, AGC_IF, 1) ; //change for 2.6.3 - status += MXL_ControlWrite(Tuner, AGC_RF, 15) ; - - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + if (state->Mod_Type == MXL_ANALOG_CABLE) { + /* Analog Cable Mode */ + /* Tuner->Mode = MXL_DIGITAL_MODE; */ + + state->AGC_Mode = 1; /* Single AGC Mode */ + + /* Disable RSSI */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + status += MXL_ControlWrite(fe, AGC_IF, 1); /* change for 2.6.3 */ + status += MXL_ControlWrite(fe, AGC_RF, 15); + status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (Tuner->Mod_Type == MXL_ANALOG_OTA) //Analog OTA Terrestrial mode add for 2.6.7 - { - //Tuner->Mode = MXL_ANALOG_MODE; - - // Enable RSSI - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - - // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; - - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; - - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + if (state->Mod_Type == MXL_ANALOG_OTA) { + /* Analog OTA Terrestrial mode add for 2.6.7 */ + /* state->Mode = MXL_ANALOG_MODE; */ + + /* Enable RSSI */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); + status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - // RSSI disable - if(Tuner->EN_RSSI==0) - { - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + /* RSSI disable */ + if(state->EN_RSSI==0) { + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); } - return status ; + return status; } /////////////////////////////////////////////////////////////////////////////// @@ -2456,9 +2278,9 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner) u32 fracModVal ; Kdbl = 2 ; - if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) + if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL) Kdbl = 2 ; - if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL) + if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) Kdbl = 1 ; // @@ -2467,43 +2289,43 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner) if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF mode { if (Tuner->IF_LO == 41000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 328000000UL ; } if (Tuner->IF_LO == 47000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 376000000UL ; } if (Tuner->IF_LO == 54000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 324000000UL ; } if (Tuner->IF_LO == 60000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 39250000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 314000000UL ; } if (Tuner->IF_LO == 39650000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 317200000UL ; } if (Tuner->IF_LO == 40150000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 321200000UL ; } if (Tuner->IF_LO == 40650000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 325200000UL ; } } @@ -2511,153 +2333,153 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner) if (Tuner->Mode || (Tuner->Mode == 0 && Tuner->IF_Mode == 0)) { if (Tuner->IF_LO == 57000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 342000000UL ; } if (Tuner->IF_LO == 44000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352000000UL ; } if (Tuner->IF_LO == 43750000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 350000000UL ; } if (Tuner->IF_LO == 36650000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 366500000UL ; } if (Tuner->IF_LO == 36150000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 361500000UL ; } if (Tuner->IF_LO == 36000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 35250000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352500000UL ; } if (Tuner->IF_LO == 34750000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 347500000UL ; } if (Tuner->IF_LO == 6280000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 376800000UL ; } if (Tuner->IF_LO == 5000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 4500000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 4570000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 365600000UL ; } if (Tuner->IF_LO == 4000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 57400000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 344400000UL ; } if (Tuner->IF_LO == 44400000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 355200000UL ; } if (Tuner->IF_LO == 44150000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 353200000UL ; } if (Tuner->IF_LO == 37050000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 370500000UL ; } if (Tuner->IF_LO == 36550000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 365500000UL ; } if (Tuner->IF_LO == 36125000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 361250000UL ; } if (Tuner->IF_LO == 6000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 5400000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 324000000UL ; } if (Tuner->IF_LO == 5380000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 322800000UL ; } if (Tuner->IF_LO == 5200000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 374400000UL ; } if (Tuner->IF_LO == 4900000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352800000UL ; } if (Tuner->IF_LO == 4400000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352000000UL ; } if (Tuner->IF_LO == 4063000UL) //add for 2.6.8 { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 365670000UL ; } } // CHCAL_INT_MOD_IF // CHCAL_FRAC_MOD_IF - intModVal = Fref / (Tuner->Fxtal * Kdbl/2) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_IF, intModVal ) ; + intModVal = Fref / (state->Fxtal * Kdbl/2) ; + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal ) ; - fracModVal = (2<<15)*(Fref/1000 - (Tuner->Fxtal/1000 * Kdbl/2) * intModVal); - fracModVal = fracModVal / ((Tuner->Fxtal * Kdbl/2)/1000) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_IF, fracModVal) ; + fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * intModVal); + fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000) ; + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal) ; return status ; } @@ -2706,7 +2528,7 @@ u32 MXL_GetXtalInt(u32 Xtal_Freq) // Functions used: // // MXL_SynthRFTGLO_Calc // // MXL5005_ControlWrite // -// MXL_GetXtalInt // +// MXL_GetXtalInt // // // // Inputs: // // Tuner : Tuner structure defined at higher level // @@ -2718,32 +2540,33 @@ u32 MXL_GetXtalInt(u32 Xtal_Freq) // 0 : Successful // // 1 : Unsuccessful // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) +u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) { + struct mxl5005s_state *state = fe->demodulator_priv; // Declare Local Variables - u16 status = 0 ; - u32 divider_val, E3, E4, E5, E5A ; - u32 Fmax, Fmin, FmaxBin, FminBin ; + u16 status = 0; + u32 divider_val, E3, E4, E5, E5A; + u32 Fmax, Fmin, FmaxBin, FminBin; u32 Kdbl_RF = 2; - u32 tg_divval ; - u32 tg_lo ; - u32 Xtal_Int ; + u32 tg_divval; + u32 tg_lo; + u32 Xtal_Int; u32 Fref_TG; u32 Fvco; // u32 temp; - Xtal_Int = MXL_GetXtalInt(Tuner->Fxtal ) ; + Xtal_Int = MXL_GetXtalInt(state->Fxtal); - Tuner->RF_IN = RF_Freq ; + state->RF_IN = RF_Freq; - MXL_SynthRFTGLO_Calc( Tuner ) ; + MXL_SynthRFTGLO_Calc(fe); - if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL) - Kdbl_RF = 2 ; - if (Tuner->Fxtal > 22000000 && Tuner->Fxtal <= 32000000) - Kdbl_RF = 1 ; + if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL) + Kdbl_RF = 2; + if (state->Fxtal > 22000000 && state->Fxtal <= 32000000) + Kdbl_RF = 1; // // Downconverter Controls @@ -2755,133 +2578,133 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // DN_EN_VHFUHFBAR // DN_GAIN_ADJUST // Change the boundary reference from RF_IN to RF_LO - if (Tuner->RF_LO < 40000000UL) { + if (state->RF_LO < 40000000UL) { return -1; } - if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) { + if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 2) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 423) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ; + status += MXL_ControlWrite(fe, DN_POLY, 2); + status += MXL_ControlWrite(fe, DN_RFGAIN, 3); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); } - if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) { + if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 222) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 3); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); } - if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) { + if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 147) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 3); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); } - if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) { + if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 9) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 3); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); } - if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) { + if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3) ; + status += MXL_ControlWrite(fe, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; } - if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 650000000UL) { + if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 1) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3) ; + status += MXL_ControlWrite(fe, DN_RFGAIN, 1) ; + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; } - if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 900000000UL) { + if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 2) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3) ; + status += MXL_ControlWrite(fe, DN_RFGAIN, 2) ; + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; } - if (Tuner->RF_LO > 900000000UL) { + if (state->RF_LO > 900000000UL) { return -1; } // DN_IQTNBUF_AMP // DN_IQTNGNBFBIAS_BST - if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 400000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 400000000UL && Tuner->RF_LO <= 450000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 450000000UL && Tuner->RF_LO <= 500000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 500000000UL && Tuner->RF_LO <= 550000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 550000000UL && Tuner->RF_LO <= 600000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 600000000UL && Tuner->RF_LO <= 650000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 700000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 700000000UL && Tuner->RF_LO <= 750000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 750000000UL && Tuner->RF_LO <= 800000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 800000000UL && Tuner->RF_LO <= 850000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ; + if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1); } - if (Tuner->RF_LO > 850000000UL && Tuner->RF_LO <= 900000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ; + if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1); } // @@ -2898,143 +2721,143 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // Set divider_val, Fmax, Fmix to use in Equations FminBin = 28000000UL ; FmaxBin = 42500000UL ; - if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); divider_val = 64 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 42500000UL ; FmaxBin = 56000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); divider_val = 64 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 56000000UL ; FmaxBin = 85000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; divider_val = 32 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 85000000UL ; FmaxBin = 112000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; divider_val = 32 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 112000000UL ; FmaxBin = 170000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; divider_val = 16 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 170000000UL ; FmaxBin = 225000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; divider_val = 16 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 225000000UL ; FmaxBin = 300000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 4) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4) ; divider_val = 8 ; Fmax = 340000000UL ; Fmin = FminBin ; } FminBin = 300000000UL ; FmaxBin = 340000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; divider_val = 8 ; Fmax = FmaxBin ; Fmin = 225000000UL ; } FminBin = 340000000UL ; FmaxBin = 450000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 2) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; divider_val = 8 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 450000000UL ; FmaxBin = 680000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 680000000UL ; FmaxBin = 900000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -3047,32 +2870,32 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // Equation E3 // RFSYN_VCO_BIAS - E3 = (((Fmax-Tuner->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, E3) ; + E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3) ; // Equation E4 // CHCAL_INT_MOD_RF - E4 = (Tuner->RF_LO*divider_val/1000)/(2*Tuner->Fxtal*Kdbl_RF/1000) ; - MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, E4) ; + E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000) ; + MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4) ; // Equation E5 // CHCAL_FRAC_MOD_RF // CHCAL_EN_INT_RF - E5 = ((2<<17)*(Tuner->RF_LO/10000*divider_val - (E4*(2*Tuner->Fxtal*Kdbl_RF)/10000)))/(2*Tuner->Fxtal*Kdbl_RF/10000) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ; + E5 = ((2<<17)*(state->RF_LO/10000*divider_val - (E4*(2*state->Fxtal*Kdbl_RF)/10000)))/(2*state->Fxtal*Kdbl_RF/10000) ; + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ; // Equation E5A // RFSYN_LPF_R - E5A = (((Fmax - Tuner->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; - status += MXL_ControlWrite(Tuner, RFSYN_LPF_R, E5A) ; + E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; + status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A) ; // Euqation E5B // CHCAL_EN_INIT_RF - status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); + status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); //if (E5 == 0) - // status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, 1); + // status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1); //else - // status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ; + // status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ; // // Set TG Synth @@ -3082,98 +2905,98 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // TG_LO_SELVAL // // Set divider_val, Fmax, Fmix to use in Equations - if (Tuner->TG_LO < 33000000UL) { + if (state->TG_LO < 33000000UL) { return -1; } FminBin = 33000000UL ; FmaxBin = 50000000UL ; - if (Tuner->TG_LO >= FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x6) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ; + if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; divider_val = 36 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 50000000UL ; FmaxBin = 67000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x1) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; divider_val = 24 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 67000000UL ; FmaxBin = 100000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0xC) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; divider_val = 18 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 100000000UL ; FmaxBin = 150000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; divider_val = 12 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 150000000UL ; FmaxBin = 200000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; divider_val = 8 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 200000000UL ; FmaxBin = 300000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; divider_val = 6 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 300000000UL ; FmaxBin = 400000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 400000000UL ; FmaxBin = 600000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; divider_val = 3 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 600000000UL ; FmaxBin = 900000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; divider_val = 2 ; Fmax = FmaxBin ; Fmin = FminBin ; } // TG_DIV_VAL - tg_divval = (Tuner->TG_LO*divider_val/100000) - *(MXL_Ceiling(Tuner->Fxtal,1000000) * 100) / (Tuner->Fxtal/1000) ; - status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval) ; + tg_divval = (state->TG_LO*divider_val/100000) + *(MXL_Ceiling(state->Fxtal,1000000) * 100) / (state->Fxtal/1000) ; + status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval) ; - if (Tuner->TG_LO > 600000000UL) - status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval + 1 ) ; + if (state->TG_LO > 600000000UL) + status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1 ) ; Fmax = 1800000000UL ; Fmin = 1200000000UL ; @@ -3181,28 +3004,28 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4 - Fref_TG = (Tuner->Fxtal/1000)/ MXL_Ceiling(Tuner->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000 + Fref_TG = (state->Fxtal/1000)/ MXL_Ceiling(state->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000 - Fvco = (Tuner->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10 + Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10 tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8; //below equation is same as above but much harder to debug. - //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((Tuner->TG_LO/10000)*divider_val*(Tuner->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ; + //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((state->TG_LO/10000)*divider_val*(state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ; - status += MXL_ControlWrite(Tuner, TG_VCO_BIAS , tg_lo) ; + status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo) ; //add for 2.6.5 //Special setting for QAM - if(Tuner ->Mod_Type == MXL_QAM) + if(state->Mod_Type == MXL_QAM) { - if(Tuner->RF_IN < 680000000) - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; + if(state->RF_IN < 680000000) + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; else - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 2) ; + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2) ; } @@ -3213,673 +3036,675 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // if (Tuner->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // turn off Bank 1 - status += MXL_SetGPIO(Tuner, 1, 1) ; // turn off Bank 2 - status += MXL_SetGPIO(Tuner, 4, 1) ; // turn off Bank 3 + status += MXL_SetGPIO(fe, 3, 1) ; // turn off Bank 1 + status += MXL_SetGPIO(fe, 1, 1) ; // turn off Bank 2 + status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3 } if (Tuner->TF_Type == MXL_TF_C) // Tracking Filter type C { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; - status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; + status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000) + if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000) + if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000) + if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000) + if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 29) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(fe, DAC_DIN_B, 29) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000) + if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000) + if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 16) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(fe, DAC_DIN_B, 16) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000) + if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 7) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(fe, DAC_DIN_B, 7) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only { - status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000) + if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000) + if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000) + if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000) + if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000) + if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000) + if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000) + if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_D) // Tracking Filter type D { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000) + if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000) + if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000) + if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 { - status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; // if UHF and terrestrial => Turn off Tracking Filter - if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) + if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) { // Turn off all the banks - status += MXL_SetGPIO(Tuner, 3, 1) ; - status += MXL_SetGPIO(Tuner, 1, 1) ; - status += MXL_SetGPIO(Tuner, 4, 1) ; - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; + status += MXL_SetGPIO(fe, 1, 1) ; + status += MXL_SetGPIO(fe, 4, 1) ; + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; - status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; + status += MXL_ControlWrite(fe, AGC_IF, 10) ; } else // if VHF or cable => Turn on Tracking Filter { - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 140000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 140000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off } - if (Tuner->RF_IN >= 140000000 && Tuner->RF_IN < 240000000) + if (state->RF_IN >= 140000000 && state->RF_IN < 240000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off } - if (Tuner->RF_IN >= 240000000 && Tuner->RF_IN < 340000000) + if (state->RF_IN >= 240000000 && state->RF_IN < 340000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off } - if (Tuner->RF_IN >= 340000000 && Tuner->RF_IN < 430000000) + if (state->RF_IN >= 340000000 && state->RF_IN < 430000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On } - if (Tuner->RF_IN >= 430000000 && Tuner->RF_IN < 470000000) + if (state->RF_IN >= 430000000 && state->RF_IN < 470000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On } - if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 570000000) + if (state->RF_IN >= 470000000 && state->RF_IN < 570000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On } - if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 620000000) + if (state->RF_IN >= 570000000 && state->RF_IN < 620000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Offq + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Offq } - if (Tuner->RF_IN >= 620000000 && Tuner->RF_IN < 760000000) + if (state->RF_IN >= 620000000 && state->RF_IN < 760000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } } if (Tuner->TF_Type == MXL_TF_E) // Tracking Filter type E { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000) + if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000) + if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000) + if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_F) // Tracking Filter type F { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 160000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 160000000 && Tuner->RF_IN < 210000000) + if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 210000000 && Tuner->RF_IN < 300000000) + if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 300000000 && Tuner->RF_IN < 390000000) + if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 390000000 && Tuner->RF_IN < 515000000) + if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 515000000 && Tuner->RF_IN < 650000000) + if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 650000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000) + if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000) + if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000) + if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 50000000 && Tuner->RF_IN < 190000000) + if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 190000000 && Tuner->RF_IN < 280000000) + if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 350000000) + if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 470000000) //modified for 2.6.11 + if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) //modified for 2.6.11 { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN < 820000000) + if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 820000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; // if UHF and terrestrial=> Turn off Tracking Filter - if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) + if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) { // Turn off all the banks - status += MXL_SetGPIO(Tuner, 3, 1) ; - status += MXL_SetGPIO(Tuner, 1, 1) ; - status += MXL_SetGPIO(Tuner, 4, 1) ; - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; + status += MXL_SetGPIO(fe, 1, 1) ; + status += MXL_SetGPIO(fe, 4, 1) ; + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; //2.6.12 //Turn on RSSI - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1) ; // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5) ; + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3) ; + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2) ; - //status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; //doesn't matter since RSSI is turn on + //status += MXL_ControlWrite(fe, AGC_IF, 10) ; //doesn't matter since RSSI is turn on //following parameter is from analog OTA mode, can be change to seek better performance - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; } else //if VHF or Cable => Turn on Tracking Filter { //2.6.12 //Turn off RSSI - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0) ; //change back from above condition - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000) + if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000) + if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000) + if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } } return status ; } -u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val) +// DONE +u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { - u16 status = 0 ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; if (GPIO_Num == 1) - status += MXL_ControlWrite(Tuner, GPIO_1B, GPIO_Val ? 0 : 1) ; - // GPIO2 is not available - if (GPIO_Num == 3) - { + status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1); + + /* GPIO2 is not available */ + + if (GPIO_Num == 3) { if (GPIO_Val == 1) { - status += MXL_ControlWrite(Tuner, GPIO_3, 0) ; - status += MXL_ControlWrite(Tuner, GPIO_3B, 0) ; + status += MXL_ControlWrite(fe, GPIO_3, 0); + status += MXL_ControlWrite(fe, GPIO_3B, 0); } if (GPIO_Val == 0) { - status += MXL_ControlWrite(Tuner, GPIO_3, 1) ; - status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ; + status += MXL_ControlWrite(fe, GPIO_3, 1); + status += MXL_ControlWrite(fe, GPIO_3B, 1); } - if (GPIO_Val == 3) { // tri-state - status += MXL_ControlWrite(Tuner, GPIO_3, 0) ; - status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ; + if (GPIO_Val == 3) { /* tri-state */ + status += MXL_ControlWrite(fe, GPIO_3, 0); + status += MXL_ControlWrite(fe, GPIO_3B, 1); } } - if (GPIO_Num == 4) - { + if (GPIO_Num == 4) { if (GPIO_Val == 1) { - status += MXL_ControlWrite(Tuner, GPIO_4, 0) ; - status += MXL_ControlWrite(Tuner, GPIO_4B, 0) ; + status += MXL_ControlWrite(fe, GPIO_4, 0); + status += MXL_ControlWrite(fe, GPIO_4B, 0); } if (GPIO_Val == 0) { - status += MXL_ControlWrite(Tuner, GPIO_4, 1) ; - status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ; + status += MXL_ControlWrite(fe, GPIO_4, 1); + status += MXL_ControlWrite(fe, GPIO_4B, 1); } - if (GPIO_Val == 3) { // tri-state - status += MXL_ControlWrite(Tuner, GPIO_4, 0) ; - status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ; + if (GPIO_Val == 3) { /* tri-state */ + status += MXL_ControlWrite(fe, GPIO_4, 0); + status += MXL_ControlWrite(fe, GPIO_4B, 1); } } - return status ; + return status; } /////////////////////////////////////////////////////////////////////////////// @@ -3907,17 +3732,19 @@ u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val) // >0 : Value exceed maximum allowed for control number // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value) +// DONE +u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { - u16 status = 0 ; - // Will write ALL Matching Control Name - status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 1 ) ; // Write Matching INIT Control - status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 2 ) ; // Write Matching CH Control + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; + + /* Will write ALL Matching Control Name */ + status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control * + status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control * #ifdef _MXL_INTERNAL - status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 3 ) ; // Write Matching MXL Control + status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control * #endif - - return status ; + return status; } /////////////////////////////////////////////////////////////////////////////// @@ -3947,105 +3774,86 @@ u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value) // 2 : Control name not found // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 controlNum, u32 value, u16 controlGroup) +// DONE +u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { - u16 i, j, k ; - u32 highLimit ; - u32 ctrlVal ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 i, j, k; + u32 highLimit; + u32 ctrlVal; - if( controlGroup == 1) // Initial Control - { - for (i=0; iInit_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) - { // find the control Name - highLimit = 1 << Tuner->Init_Ctrl[i].size ; - if ( value < highLimit) - { - for( j=0; jInit_Ctrl[i].size; j++) - { - Tuner->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; - // change the register map accordingly - MXL_RegWriteBit( Tuner, (u8)(Tuner->Init_Ctrl[i].addr[j]), - (u8)(Tuner->Init_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ) ; - } - ctrlVal = 0 ; - for(k=0; kInit_Ctrl[i].size; k++) - { - ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ; + if (controlGroup == 1) /* Initial Control */ { + + for (i = 0; i < state->Init_Ctrl_Num; i++) { + + if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { + + highLimit = 1 << state->Init_Ctrl[i].size; + if (value < highLimit) { + for (j = 0; j < state->Init_Ctrl[i].size; j++) { + state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); + MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]), + (u8)(state->Init_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ); } + ctrlVal = 0; + for (k = 0; k < state->Init_Ctrl[i].size; k++) + ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); } else - { - return -1 ; - } + return -1; } } } - if ( controlGroup == 2) // Chan change Control - { - for (i=0; iCH_Ctrl_Num; i++) - { - if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) - { // find the control Name - highLimit = 1 << Tuner->CH_Ctrl[i].size ; - if ( value < highLimit) - { - for( j=0; jCH_Ctrl[i].size; j++) - { - Tuner->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; - // change the register map accordingly - MXL_RegWriteBit( Tuner, (u8)(Tuner->CH_Ctrl[i].addr[j]), - (u8)(Tuner->CH_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ) ; - } - ctrlVal = 0 ; - for(k=0; kCH_Ctrl[i].size; k++) - { - ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ; + if (controlGroup == 2) /* Chan change Control */ { + + for (i = 0; i < state->CH_Ctrl_Num; i++) { + + if (controlNum == state->CH_Ctrl[i].Ctrl_Num ) { + + highLimit = 1 << state->CH_Ctrl[i].size; + if (value < highLimit) { + for (j = 0; j < state->CH_Ctrl[i].size; j++) { + state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); + MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]), + (u8)(state->CH_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ); } + ctrlVal = 0; + for (k = 0; k < state->CH_Ctrl[i].size; k++) + ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); } else - { - return -1 ; - } + return -1; } } } #ifdef _MXL_INTERNAL - if ( controlGroup == 3) // Maxlinear Control - { - for (i=0; iMXL_Ctrl_Num; i++) - { - if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) - { // find the control Name - highLimit = (1 << Tuner->MXL_Ctrl[i].size) ; - if ( value < highLimit) - { - for( j=0; jMXL_Ctrl[i].size; j++) - { - Tuner->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; - // change the register map accordingly - MXL_RegWriteBit( Tuner, (u8)(Tuner->MXL_Ctrl[i].addr[j]), - (u8)(Tuner->MXL_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ) ; - } - ctrlVal = 0 ; - for(k=0; kMXL_Ctrl[i].size; k++) - { - ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1 << k) ; + if (controlGroup == 3) /* Maxlinear Control */ { + + for (i = 0; i < state->MXL_Ctrl_Num; i++) { + + if (controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { + + highLimit = (1 << state->MXL_Ctrl[i].size) ; + if (value < highLimit) { + for (j = 0; j < state->MXL_Ctrl[i].size; j++) { + state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); + MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]), + (u8)(state->MXL_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ); } + ctrlVal = 0; + for(k = 0; k < state->MXL_Ctrl[i].size; k++) + ctrlVal += state->MXL_Ctrl[i].val[k] * (1 << k); } else - { - return -1 ; - } + return -1; } } } #endif - return 0 ; // successful return + return 0 ; /* successful return */ } /////////////////////////////////////////////////////////////////////////////// @@ -4073,20 +3881,20 @@ u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 controlNum, u32 value, u16 c // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal) +// DONE +u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { + struct mxl5005s_state *state = fe->demodulator_priv; int i ; - for (i=0; i<104; i++) - { - if (RegNum == Tuner->TunerRegs[i].Reg_Num ) - { - Tuner->TunerRegs[i].Reg_Val = RegVal ; - return 0 ; + for (i = 0; i < 104; i++) { + if (RegNum == state->TunerRegs[i].Reg_Num) { + state->TunerRegs[i].Reg_Val = RegVal; + return 0; } } - return 1 ; + return 1; } /////////////////////////////////////////////////////////////////////////////// @@ -4113,20 +3921,20 @@ u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal) // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal) +// DONE +u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { + struct mxl5005s_state *state = fe->demodulator_priv; int i ; - for (i=0; i<104; i++) - { - if (RegNum == Tuner->TunerRegs[i].Reg_Num ) - { - *RegVal = (u8)(Tuner->TunerRegs[i].Reg_Val) ; - return 0 ; + for (i = 0; i < 104; i++) { + if (RegNum == state->TunerRegs[i].Reg_Num ) { + *RegVal = (u8)(state->TunerRegs[i].Reg_Val); + return 0; } } - return 1 ; + return 1; } /////////////////////////////////////////////////////////////////////////////// @@ -4150,48 +3958,53 @@ u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_ControlRead(Tuner_struct *Tuner, u16 controlNum, u32 * value) +// DONE +u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 * value) { + struct mxl5005s_state *state = fe->demodulator_priv; u32 ctrlVal ; u16 i, k ; - for (i=0; iInit_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) - { - ctrlVal = 0 ; - for(k=0; kInit_Ctrl[i].size; k++) - ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ; - *value = ctrlVal ; - return 0 ; + for (i = 0; i < state->Init_Ctrl_Num ; i++) { + + if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { + + ctrlVal = 0; + for (k = 0; k < state->Init_Ctrl[i].size; k++) + ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); + *value = ctrlVal; + return 0; } } - for (i=0; iCH_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) - { - ctrlVal = 0 ; - for(k=0; kCH_Ctrl[i].size; k++) - ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ; - *value = ctrlVal ; - return 0 ; + + for (i = 0; i < state->CH_Ctrl_Num ; i++) { + + if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { + + ctrlVal = 0; + for (k = 0; k < state->CH_Ctrl[i].size; k++) + ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); + *value = ctrlVal; + return 0; + } } #ifdef _MXL_INTERNAL - for (i=0; iMXL_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) - { - ctrlVal = 0 ; - for(k=0; kMXL_Ctrl[i].size; k++) - ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1<MXL_Ctrl_Num ; i++) { + + if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { + + ctrlVal = 0; + for (k = 0; k < state->MXL_Ctrl[i].size; k++) + ctrlVal += state->MXL_Ctrl[i].val[k] * (1<demodulator_priv; u16 i, j, k ; u16 Count ; - for (i=0; iInit_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) - { - Count = 1 ; - RegNum[0] = (u8)(Tuner->Init_Ctrl[i].addr[0]) ; + for (i = 0; i < state->Init_Ctrl_Num ; i++) { + + if ( controlNum == state->Init_Ctrl[i].Ctrl_Num ) { + + Count = 1; + RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]); + + for (k = 1; k < state->Init_Ctrl[i].size; k++) { + + for (j = 0; j < Count; j++) { + + if (state->Init_Ctrl[i].addr[k] != RegNum[j]) { + + Count ++; + RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]); - for(k=1; kInit_Ctrl[i].size; k++) - { - for (j= 0; jInit_Ctrl[i].addr[k] != RegNum[j]) - { - Count ++ ; - RegNum[Count-1] = (u8)(Tuner->Init_Ctrl[i].addr[k]) ; } } } - *count = Count ; - return 0 ; + *count = Count; + return 0; } } - for (i=0; iCH_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) - { - Count = 1 ; - RegNum[0] = (u8)(Tuner->CH_Ctrl[i].addr[0]) ; + for (i = 0; i < state->CH_Ctrl_Num ; i++) { + + if ( controlNum == state->CH_Ctrl[i].Ctrl_Num ) { + + Count = 1; + RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]); + + for (k = 1; k < state->CH_Ctrl[i].size; k++) { + + for (j= 0; jCH_Ctrl[i].addr[k] != RegNum[j]) { + + Count ++; + RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]); - for(k=1; kCH_Ctrl[i].size; k++) - { - for (j= 0; jCH_Ctrl[i].addr[k] != RegNum[j]) - { - Count ++ ; - RegNum[Count-1] = (u8)(Tuner->CH_Ctrl[i].addr[k]) ; } } } - *count = Count ; - return 0 ; + *count = Count; + return 0; } } #ifdef _MXL_INTERNAL - for (i=0; iMXL_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) - { - Count = 1 ; - RegNum[0] = (u8)(Tuner->MXL_Ctrl[i].addr[0]) ; + for (i = 0; i < state->MXL_Ctrl_Num ; i++) { + + if ( controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { + + Count = 1; + RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]); + + for (k = 1; k < state->MXL_Ctrl[i].size; k++) { + + for (j = 0; jMXL_Ctrl[i].addr[k] != RegNum[j]) { + + Count ++; + RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k]; - for(k=1; kMXL_Ctrl[i].size; k++) - { - for (j= 0; jMXL_Ctrl[i].addr[k] != RegNum[j]) - { - Count ++ ; - RegNum[Count-1] = (u8)Tuner->MXL_Ctrl[i].addr[k] ; } } } - *count = Count ; - return 0 ; + *count = Count; + return 0; } } #endif - *count = 0 ; - return 1 ; + *count = 0; + return 1; } /////////////////////////////////////////////////////////////////////////////// @@ -4308,7 +4126,7 @@ u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 controlNum, u8 *RegNum, int * co // Inputs: // // Tuner_struct : structure defined at higher level // // address : register address // -// bit : register bit number // +// bit : register bit number // // bitVal : register bit value // // // // Outputs: // @@ -4318,12 +4136,12 @@ u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 controlNum, u8 *RegNum, int * co // NONE // // // /////////////////////////////////////////////////////////////////////////////// - -void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal) +// DONE +void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { + struct mxl5005s_state *state = fe->demodulator_priv; int i ; - // Declare Local Constants const u8 AND_MAP[8] = { 0xFE, 0xFD, 0xFB, 0xF7, 0xEF, 0xDF, 0xBF, 0x7F } ; @@ -4332,17 +4150,16 @@ void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal) 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 } ; - for(i=0; iTunerRegs_Num; i++) { - if ( Tuner->TunerRegs[i].Reg_Num == address ) { + for (i = 0; i < state->TunerRegs_Num; i++) { + if (state->TunerRegs[i].Reg_Num == address) { if (bitVal) - Tuner->TunerRegs[i].Reg_Val |= OR_MAP[bit] ; + state->TunerRegs[i].Reg_Val |= OR_MAP[bit]; else - Tuner->TunerRegs[i].Reg_Val &= AND_MAP[bit] ; + state->TunerRegs[i].Reg_Val &= AND_MAP[bit]; break ; } } -} ; - +} /////////////////////////////////////////////////////////////////////////////// // // @@ -4367,37 +4184,43 @@ void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal) // Computed value // // // /////////////////////////////////////////////////////////////////////////////// -u32 MXL_Ceiling( u32 value, u32 resolution ) +// DONE +u32 MXL_Ceiling(u32 value, u32 resolution) { - return (value/resolution + (value%resolution > 0 ? 1 : 0)) ; -}; + return (value/resolution + (value % resolution > 0 ? 1 : 0)); +} // // Retrieve the Initialzation Registers // -u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) +// DONE +u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { + struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i ; - u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, - 76, 77, 91, 134, 135, 137, 147, - 156, 166, 167, 168, 25 } ; - *count = sizeof(RegAddr) / sizeof(u8) ; + u8 RegAddr[] = { + 11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, + 76, 77, 91, 134, 135, 137, 147, + 156, 166, 167, 168, 25 }; - status += MXL_BlockInit(Tuner) ; + *count = sizeof(RegAddr) / sizeof(u8); - for (i=0 ; i< *count; i++) - { - RegNum[i] = RegAddr[i] ; - status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + status += MXL_BlockInit(fe); + + for (i = 0 ; i < *count; i++) { + RegNum[i] = RegAddr[i]; + status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); } - return status ; + return status; } -u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) +// DONE +u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { + struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i ; @@ -4413,203 +4236,207 @@ u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) // RegAddr[i] = i; #endif - *count = sizeof(RegAddr) / sizeof(u8) ; + *count = sizeof(RegAddr) / sizeof(u8); - for (i=0 ; i< *count; i++) - { - RegNum[i] = RegAddr[i] ; - status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + for (i = 0 ; i < *count; i++) { + RegNum[i] = RegAddr[i]; + status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); } - return status ; - + return status; } -u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) +// DONE +u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - u16 status = 0 ; - int i ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; + int i; - u8 RegAddr[] = {43, 136} ; + u8 RegAddr[] = {43, 136}; - *count = sizeof(RegAddr) / sizeof(u8) ; + *count = sizeof(RegAddr) / sizeof(u8); - for (i=0; i<*count; i++) - { - RegNum[i] = RegAddr[i] ; - status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + for (i = 0; i < *count; i++) { + RegNum[i] = RegAddr[i]; + status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); } - return status ; + return status; } -u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) +// DONE +u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - u16 status = 0 ; - int i ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; + int i; - u8 RegAddr[] = {138} ; + u8 RegAddr[] = { 138 }; - *count = sizeof(RegAddr) / sizeof(u8) ; + *count = sizeof(RegAddr) / sizeof(u8); - for (i=0; i<*count; i++) - { - RegNum[i] = RegAddr[i] ; - status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + for (i = 0; i < *count; i++) { + RegNum[i] = RegAddr[i]; + status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); } - return status ; + return status; } +// DONE u16 MXL_GetMasterControl(u8 *MasterReg, int state) { - if (state == 1) // Load_Start - *MasterReg = 0xF3 ; - if (state == 2) // Power_Down - *MasterReg = 0x41 ; - if (state == 3) // Synth_Reset - *MasterReg = 0xB1 ; - if (state == 4) // Seq_Off - *MasterReg = 0xF1 ; - - return 0 ; + if (state == 1) /* Load_Start */ + *MasterReg = 0xF3; + if (state == 2) /* Power_Down */ + *MasterReg = 0x41; + if (state == 3) /* Synth_Reset */ + *MasterReg = 0xB1; + if (state == 4) /* Seq_Off */ + *MasterReg = 0xF1; + + return 0; } #ifdef _MXL_PRODUCTION -u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) +u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) { + struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0 ; if (VCO_Range == 1) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224); - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ; - } - if (Tuner->Mode == 1) // Digital Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ; + status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 180224); + } + if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 222822); + } + if (state->Mode == 1) /* Digital Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 229376); } } if (VCO_Range == 2) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41); - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); - } - if (Tuner->Mode == 1) // Digital Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384); + status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + } + if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + } + if (state->Mode == 1) /* Digital Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 16384); } } if (VCO_Range == 3) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670); - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670); - } - if (Tuner->Mode == 1) // Digital Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760); + status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); + } + if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); + } + if (state->Mode == 1) /* Digital Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 245760); } } if (VCO_Range == 4) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); - } - if (Tuner->Mode == 1) // Digital Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992); + status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + } + if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + } + if (state->Mode == 1) /* Digital Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 212992); } } return status; } -u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) +// DONE +u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { + struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; if (Hystersis == 1) - status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1); + status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1); return status; } diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h index 1944d9e94427..df49826816bb 100644 --- a/drivers/media/common/tuners/mxl5005s.h +++ b/drivers/media/common/tuners/mxl5005s.h @@ -140,61 +140,6 @@ typedef struct _TunerReg_struct u16 Reg_Val; /* Current sofware programmed value waiting to be writen */ } TunerReg_struct; -/* MXL5005 Tuner Control Struct */ -typedef struct _TunerControl_struct { - u16 Ctrl_Num; /* Control Number */ - u16 size; /* Number of bits to represent Value */ - u16 addr[25]; /* Array of Tuner Register Address for each bit position */ - u16 bit[25]; /* Array of bit position in Register Address for each bit position */ - u16 val[25]; /* Binary representation of Value */ -} TunerControl_struct; - -/* MXL5005 Tuner Struct */ -typedef struct _Tuner_struct -{ - u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ - u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */ - u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */ - u32 IF_OUT; /* Desired IF Out Frequency */ - u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */ - u32 RF_IN; /* RF Input Frequency */ - u32 Fxtal; /* XTAL Frequency */ - u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */ - u16 TOP; /* Value: take over point */ - u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */ - u8 DIV_OUT; /* 4MHz or 16MHz */ - u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */ - u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */ - u8 Mod_Type; /* Modulation Type; */ - /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ - u8 TF_Type; /* Tracking Filter Type */ - /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ - - /* Calculated Settings */ - u32 RF_LO; /* Synth RF LO Frequency */ - u32 IF_LO; /* Synth IF LO Frequency */ - u32 TG_LO; /* Synth TG_LO Frequency */ - - /* Pointers to ControlName Arrays */ - u16 Init_Ctrl_Num; /* Number of INIT Control Names */ - TunerControl_struct - Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ - - u16 CH_Ctrl_Num; /* Number of CH Control Names */ - TunerControl_struct - CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ - - u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ - TunerControl_struct - MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ - - /* Pointer to Tuner Register Array */ - u16 TunerRegs_Num; /* Number of Tuner Registers */ - TunerReg_struct - TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ - -} Tuner_struct; - typedef enum { /* Initialization Control Names */ @@ -290,60 +235,6 @@ typedef enum * MaxLinear source code - Common_MXL.h (?) */ -void InitTunerControls(Tuner_struct *Tuner); -u16 MXL_BlockInit(Tuner_struct *Tuner); -u16 MXL5005_RegisterInit(Tuner_struct *Tuner); -u16 MXL5005_ControlInit(Tuner_struct *Tuner); -#ifdef _MXL_INTERNAL -u16 MXL5005_MXLControlInit(Tuner_struct *Tuner); -#endif - -u16 MXL5005_TunerConfig(Tuner_struct *Tuner, - u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ - u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ - u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ - u32 IF_out, /* Desired IF Out Frequency */ - u32 Fxtal, /* XTAL Frequency */ - u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ - u16 TOP, /* 0: Dual AGC; Value: take over point */ - u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ - u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */ - u8 DIV_OUT, /* 4MHz or 16MHz */ - u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ - u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ - u8 Mod_Type, /* Modulation Type; */ - /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ - u8 TF_Type /* Tracking Filter Type */ - /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ - ); - -void MXL_SynthIFLO_Calc(Tuner_struct *Tuner); -void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner); -u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal); -u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal); -u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value); -u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 ControlNum, u32 value, u16 controlGroup); -u16 MXL_ControlRead(Tuner_struct *Tuner, u16 ControlNum, u32 * value); -u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 ControlNum, u8 *RegNum, int *count); -void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal); -u16 MXL_IFSynthInit(Tuner_struct * Tuner ); -u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq); -u16 MXL_OverwriteICDefault(Tuner_struct *Tuner); -u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val); -u32 MXL_Ceiling(u32 value, u32 resolution); -u32 MXL_GetXtalInt(u32 Xtal_Freq); - -u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); -u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); -u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); -u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); -u16 MXL_GetMasterControl(u8 *MasterReg, int state); - -#ifdef _MXL_PRODUCTION -u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range); -u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis); -#endif - /* Constants */ #define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 #define MXL5005S_LATCH_BYTE 0xfe @@ -401,62 +292,6 @@ enum MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, }; -/* MxL5005S extra module alias */ -typedef struct MXL5005S_EXTRA_MODULE_TAG MXL5005S_EXTRA_MODULE; - -/* MxL5005S register setting function pointer */ -typedef int -(*MXL5005S_FP_SET_REGS_WITH_TABLE)( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned char *pAddrTable, - unsigned char *pByteTable, - int TableLen - ); - - -/* MxL5005S register mask bits setting function pointer */ -typedef int -(*MXL5005S_FP_SET_REG_MASK_BITS)( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned char RegAddr, - unsigned char Msb, - unsigned char Lsb, - const unsigned char WritingValue - ); - -/* MxL5005S spectrum mode setting function pointer */ -typedef int -(*MXL5005S_FP_SET_SPECTRUM_MODE)( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - int SpectrumMode - ); - -/* MxL5005S bandwidth setting function pointer */ -typedef int -(*MXL5005S_FP_SET_BANDWIDTH_HZ)( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long BandwidthHz - ); - -/* MxL5005S extra module */ -struct MXL5005S_EXTRA_MODULE_TAG -{ - /* MxL5005S function pointers */ - MXL5005S_FP_SET_REGS_WITH_TABLE SetRegsWithTable; - MXL5005S_FP_SET_REG_MASK_BITS SetRegMaskBits; - MXL5005S_FP_SET_SPECTRUM_MODE SetSpectrumMode; - MXL5005S_FP_SET_BANDWIDTH_HZ SetBandwidthHz; - - /* MxL5005S extra data */ - unsigned char AgcMasterByte; /* Variable name in MaxLinear source code: AGC_MASTER_BYTE */ - - /* MaxLinear defined struct */ - Tuner_struct MxlDefinedTunerStructure; -}; /* End of common_mxl.h (?) */ #endif /* __MXL5005S_H */ -- cgit v1.2.3 From 85d220d03b70180b9958b29d43e99c7135f00654 Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 05:48:14 -0300 Subject: V4L/DVB (7867): mxl5005s: Cleanup #4 Cleanup #4 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 926 +++++++++++++++++++++------------ drivers/media/common/tuners/mxl5005s.h | 291 ++--------- 2 files changed, 636 insertions(+), 581 deletions(-) diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index d8885484cfbd..7e687171301b 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -24,6 +24,270 @@ #include "mxl5005s.h" +static int debug; + +#define dprintk(level, arg...) do { \ + if (debug >= level) \ + printk(arg); \ + } while (0) + +#define TUNER_REGS_NUM 104 +#define INITCTRL_NUM 40 + +#ifdef _MXL_PRODUCTION +#define CHCTRL_NUM 39 +#else +#define CHCTRL_NUM 36 +#endif + +#define MXLCTRL_NUM 189 +#define MASTER_CONTROL_ADDR 9 + +/* Enumeration of AGC Mode */ +typedef enum +{ + MXL_DUAL_AGC = 0, + MXL_SINGLE_AGC +} AGC_Mode; + +/* Enumeration of Master Control Register State */ +typedef enum +{ + MC_LOAD_START = 1, + MC_POWER_DOWN, + MC_SYNTH_RESET, + MC_SEQ_OFF +} Master_Control_State; + +/* Enumeration of MXL5005 Tuner Mode */ +typedef enum +{ + MXL_ANALOG_MODE = 0, + MXL_DIGITAL_MODE +} Tuner_Mode; + +/* Enumeration of MXL5005 Tuner IF Mode */ +typedef enum +{ + MXL_ZERO_IF = 0, + MXL_LOW_IF +} Tuner_IF_Mode; + +/* Enumeration of MXL5005 Tuner Clock Out Mode */ +typedef enum +{ + MXL_CLOCK_OUT_DISABLE = 0, + MXL_CLOCK_OUT_ENABLE +} Tuner_Clock_Out; + +/* Enumeration of MXL5005 Tuner Div Out Mode */ +typedef enum +{ + MXL_DIV_OUT_1 = 0, + MXL_DIV_OUT_4 + +} Tuner_Div_Out; + +/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ +typedef enum +{ + MXL_CAP_SEL_DISABLE = 0, + MXL_CAP_SEL_ENABLE + +} Tuner_Cap_Select; + +/* Enumeration of MXL5005 Tuner RSSI Mode */ +typedef enum +{ + MXL_RSSI_DISABLE = 0, + MXL_RSSI_ENABLE + +} Tuner_RSSI; + +/* Enumeration of MXL5005 Tuner Modulation Type */ +typedef enum +{ + MXL_DEFAULT_MODULATION = 0, + MXL_DVBT, + MXL_ATSC, + MXL_QAM, + MXL_ANALOG_CABLE, + MXL_ANALOG_OTA +} Tuner_Modu_Type; + +/* Enumeration of MXL5005 Tuner Tracking Filter Type */ +typedef enum +{ + MXL_TF_DEFAULT = 0, + MXL_TF_OFF, + MXL_TF_C, + MXL_TF_C_H, + MXL_TF_D, + MXL_TF_D_L, + MXL_TF_E, + MXL_TF_F, + MXL_TF_E_2, + MXL_TF_E_NA, + MXL_TF_G +} Tuner_TF_Type; + +/* MXL5005 Tuner Register Struct */ +typedef struct _TunerReg_struct +{ + u16 Reg_Num; /* Tuner Register Address */ + u16 Reg_Val; /* Current sofware programmed value waiting to be writen */ +} TunerReg_struct; + +typedef enum +{ + /* Initialization Control Names */ + DN_IQTN_AMP_CUT = 1, /* 1 */ + BB_MODE, /* 2 */ + BB_BUF, /* 3 */ + BB_BUF_OA, /* 4 */ + BB_ALPF_BANDSELECT, /* 5 */ + BB_IQSWAP, /* 6 */ + BB_DLPF_BANDSEL, /* 7 */ + RFSYN_CHP_GAIN, /* 8 */ + RFSYN_EN_CHP_HIGAIN, /* 9 */ + AGC_IF, /* 10 */ + AGC_RF, /* 11 */ + IF_DIVVAL, /* 12 */ + IF_VCO_BIAS, /* 13 */ + CHCAL_INT_MOD_IF, /* 14 */ + CHCAL_FRAC_MOD_IF, /* 15 */ + DRV_RES_SEL, /* 16 */ + I_DRIVER, /* 17 */ + EN_AAF, /* 18 */ + EN_3P, /* 19 */ + EN_AUX_3P, /* 20 */ + SEL_AAF_BAND, /* 21 */ + SEQ_ENCLK16_CLK_OUT, /* 22 */ + SEQ_SEL4_16B, /* 23 */ + XTAL_CAPSELECT, /* 24 */ + IF_SEL_DBL, /* 25 */ + RFSYN_R_DIV, /* 26 */ + SEQ_EXTSYNTHCALIF, /* 27 */ + SEQ_EXTDCCAL, /* 28 */ + AGC_EN_RSSI, /* 29 */ + RFA_ENCLKRFAGC, /* 30 */ + RFA_RSSI_REFH, /* 31 */ + RFA_RSSI_REF, /* 32 */ + RFA_RSSI_REFL, /* 33 */ + RFA_FLR, /* 34 */ + RFA_CEIL, /* 35 */ + SEQ_EXTIQFSMPULSE, /* 36 */ + OVERRIDE_1, /* 37 */ + BB_INITSTATE_DLPF_TUNE, /* 38 */ + TG_R_DIV, /* 39 */ + EN_CHP_LIN_B, /* 40 */ + + /* Channel Change Control Names */ + DN_POLY = 51, /* 51 */ + DN_RFGAIN, /* 52 */ + DN_CAP_RFLPF, /* 53 */ + DN_EN_VHFUHFBAR, /* 54 */ + DN_GAIN_ADJUST, /* 55 */ + DN_IQTNBUF_AMP, /* 56 */ + DN_IQTNGNBFBIAS_BST, /* 57 */ + RFSYN_EN_OUTMUX, /* 58 */ + RFSYN_SEL_VCO_OUT, /* 59 */ + RFSYN_SEL_VCO_HI, /* 60 */ + RFSYN_SEL_DIVM, /* 61 */ + RFSYN_RF_DIV_BIAS, /* 62 */ + DN_SEL_FREQ, /* 63 */ + RFSYN_VCO_BIAS, /* 64 */ + CHCAL_INT_MOD_RF, /* 65 */ + CHCAL_FRAC_MOD_RF, /* 66 */ + RFSYN_LPF_R, /* 67 */ + CHCAL_EN_INT_RF, /* 68 */ + TG_LO_DIVVAL, /* 69 */ + TG_LO_SELVAL, /* 70 */ + TG_DIV_VAL, /* 71 */ + TG_VCO_BIAS, /* 72 */ + SEQ_EXTPOWERUP, /* 73 */ + OVERRIDE_2, /* 74 */ + OVERRIDE_3, /* 75 */ + OVERRIDE_4, /* 76 */ + SEQ_FSM_PULSE, /* 77 */ + GPIO_4B, /* 78 */ + GPIO_3B, /* 79 */ + GPIO_4, /* 80 */ + GPIO_3, /* 81 */ + GPIO_1B, /* 82 */ + DAC_A_ENABLE, /* 83 */ + DAC_B_ENABLE, /* 84 */ + DAC_DIN_A, /* 85 */ + DAC_DIN_B, /* 86 */ +#ifdef _MXL_PRODUCTION + RFSYN_EN_DIV, /* 87 */ + RFSYN_DIVM, /* 88 */ + DN_BYPASS_AGC_I2C /* 89 */ +#endif +} MXL5005_ControlName; + +/* + * The following context is source code provided by MaxLinear. + * MaxLinear source code - Common_MXL.h (?) + */ + +/* Constants */ +#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 +#define MXL5005S_LATCH_BYTE 0xfe + +/* Register address, MSB, and LSB */ +#define MXL5005S_BB_IQSWAP_ADDR 59 +#define MXL5005S_BB_IQSWAP_MSB 0 +#define MXL5005S_BB_IQSWAP_LSB 0 + +#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53 +#define MXL5005S_BB_DLPF_BANDSEL_MSB 4 +#define MXL5005S_BB_DLPF_BANDSEL_LSB 3 + +/* Standard modes */ +enum +{ + MXL5005S_STANDARD_DVBT, + MXL5005S_STANDARD_ATSC, +}; +#define MXL5005S_STANDARD_MODE_NUM 2 + +/* Bandwidth modes */ +enum +{ + MXL5005S_BANDWIDTH_6MHZ = 6000000, + MXL5005S_BANDWIDTH_7MHZ = 7000000, + MXL5005S_BANDWIDTH_8MHZ = 8000000, +}; +#define MXL5005S_BANDWIDTH_MODE_NUM 3 + +/* Top modes */ +enum +{ + MXL5005S_TOP_5P5 = 55, + MXL5005S_TOP_7P2 = 72, + MXL5005S_TOP_9P2 = 92, + MXL5005S_TOP_11P0 = 110, + MXL5005S_TOP_12P9 = 129, + MXL5005S_TOP_14P7 = 147, + MXL5005S_TOP_16P8 = 168, + MXL5005S_TOP_19P4 = 194, + MXL5005S_TOP_21P2 = 212, + MXL5005S_TOP_23P2 = 232, + MXL5005S_TOP_25P2 = 252, + MXL5005S_TOP_27P1 = 271, + MXL5005S_TOP_29P2 = 292, + MXL5005S_TOP_31P7 = 317, + MXL5005S_TOP_34P9 = 349, +}; + +/* IF output load */ +enum +{ + MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, + MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, +}; + /* MXL5005 Tuner Control Struct */ typedef struct _TunerControl_struct { u16 Ctrl_Num; /* Control Number */ @@ -77,241 +341,138 @@ struct mxl5005s_state TunerReg_struct TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ -}; - - -int mxl5005s_Initialize( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner - ) -{ - MXL5005S_EXTRA_MODULE *pExtra; - - unsigned char AgcMasterByte; - unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; - unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; - int TableLen; - - // Get tuner extra module. - pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - - // Get AGC master byte - AgcMasterByte = pExtra->AgcMasterByte; + /* Linux driver framework specific */ + const struct mxl5005s_config *config; - // Initialize MxL5005S tuner according to MxL5005S tuner example code. - - // Tuner initialization stage 0 - MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); - AddrTable[0] = MASTER_CONTROL_ADDR; - ByteTable[0] |= AgcMasterByte; - - if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - // Tuner initialization stage 1 - MXL_GetInitRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen); - - if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - return FUNCTION_SUCCESS; - -error_status_set_tuner_registers: - return FUNCTION_ERROR; -} + struct dvb_frontend *frontend; + struct i2c_adapter *i2c; +}; -int mxl5005s_SetRfFreqHz( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long RfFreqHz - ) +// funcs +u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); +u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); +u16 MXL_GetMasterControl(u8 *MasterReg, int state); +void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal); +u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); +u32 MXL_Ceiling(u32 value, u32 resolution); +u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); +u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); +u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup); +u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); +u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count); +u32 MXL_GetXtalInt(u32 Xtal_Freq); +u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); +void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); +void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); +u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); +int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); +u16 MXL_IFSynthInit(struct dvb_frontend *fe); + +int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { - MXL5005S_EXTRA_MODULE *pExtra; - BASE_INTERFACE_MODULE *pBaseInterface; - - unsigned char AgcMasterByte; + struct mxl5005s_state *state = fe->tuner_priv; + u8 AgcMasterByte = state->config->AgcMasterByte; unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - unsigned long IfDivval; + u32 IfDivval; unsigned char MasterControlByte; - // Get tuner extra module and base interface module. - pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - pBaseInterface = pTuner->pBaseInterface; - - - // Get AGC master byte - AgcMasterByte = pExtra->AgcMasterByte; - + dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz); // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code. // Tuner RF frequency setting stage 0 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ; AddrTable[0] = MASTER_CONTROL_ADDR; - ByteTable[0] |= AgcMasterByte; - - if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; + ByteTable[0] |= state->config->AgcMasterByte; + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); // Tuner RF frequency setting stage 1 - MXL_TuneRF(&pExtra->MxlDefinedTunerStructure, RfFreqHz); - - MXL_ControlRead(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, &IfDivval); + MXL_TuneRF(fe, RfFreqHz); - MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 0); - MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_EXTPOWERUP, 1); - MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, 8); + MXL_ControlRead(fe, IF_DIVVAL, &IfDivval); - MXL_GetCHRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ; + MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0); + MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1); + MXL_ControlWrite(fe, IF_DIVVAL, 8); + MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen) ; MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; ByteTable[TableLen] = MasterControlByte | AgcMasterByte; TableLen += 1; - if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); // Wait 30 ms. - pBaseInterface->WaitMs(pBaseInterface, 30); - + msleep(30); // Tuner RF frequency setting stage 2 - MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 1) ; - MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, IfDivval) ; - MXL_GetCHRegister_ZeroIF(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ; + MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; + MXL_ControlWrite(fe, IF_DIVVAL, IfDivval) ; + MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen) ; MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; TableLen += 1; - if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - - // Set tuner RF frequency parameter. - pTuner->RfFreqHz = RfFreqHz; - pTuner->IsRfFreqHzSet = YES; - - - return FUNCTION_SUCCESS; - + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); -error_status_set_tuner_registers: - return FUNCTION_ERROR; + return 0; } -// DONE -int mxl5005s_GetRfFreqHz(struct dvb_frontend *fe, unsigned long *pRfFreqHz) +/* Write a single byte to a single reg */ +static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val) { - struct mxl5005s_state *state = fe->demodulator_priv; - int ret = -1; - - /* Get tuner RF frequency in Hz from tuner module. */ - if(state->IsRfFreqHzSet == YES) { - *pRfFreqHz = state->RfFreqHz; - ret = 0; + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[2] = { reg, val }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 2 }; + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write failed\n"); + return -EREMOTEIO; } - - return -1; + return 0; } -int mxl5005s_SetRegsWithTable( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned char *pAddrTable, - unsigned char *pByteTable, - int TableLen - ) +/* Write a word to a single reg */ +static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) { - BASE_INTERFACE_MODULE *pBaseInterface; - I2C_BRIDGE_MODULE *pI2cBridge; - unsigned char WritingByteNumMax; - - int i; - unsigned char WritingBuffer[I2C_BUFFER_LEN]; - unsigned char WritingIndex; - - - - // Get base interface, I2C bridge, and maximum writing byte number. - pBaseInterface = pTuner->pBaseInterface; - pI2cBridge = pTuner->pI2cBridge; - WritingByteNumMax = pBaseInterface->I2cWritingByteNumMax; - - - // Set registers with table. - // Note: 1. The I2C format of MxL5005S is described as follows: - // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * n + stop_bit - // ... - // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * m + latch_byte + stop_bit - // 2. The latch_byte is 0xfe. - // 3. The following writing byte separating scheme takes latch_byte as two byte data. - for(i = 0, WritingIndex = 0; i < TableLen; i++) - { - // Put register address and register byte value into writing buffer. - WritingBuffer[WritingIndex] = pAddrTable[i]; - WritingBuffer[WritingIndex + 1] = pByteTable[i]; - WritingIndex += 2; - - // If writing buffer is full, send the I2C writing command with writing buffer. - if(WritingIndex > (WritingByteNumMax - 2)) - { - if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - WritingIndex = 0; - } + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[3] = { reg, val >> 8 , val & 0xff }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 3 }; + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write16 failed\n"); + return -EREMOTEIO; } - - - // Send the last I2C writing command with writing buffer and latch byte. - WritingBuffer[WritingIndex] = MXL5005S_LATCH_BYTE; - WritingIndex += 1; - - if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - - return FUNCTION_SUCCESS; - - -error_status_set_tuner_registers: - return FUNCTION_ERROR; + return 0; } -int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, - unsigned char *pAddrTable, - unsigned char *pByteTable, - int TableLen - ) +int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) { - struct mxl5005s_state *state = fe->demodulator_priv; - int i; + int i, ret; u8 end_two_bytes_buf[]={ 0 , 0 }; - u8 tuner_addr=0x00; - - pTuner->GetDeviceAddr(pTuner , &tuner_addr); for( i = 0 ; i < TableLen - 1 ; i++) { - if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , &pByteTable[i] , 1 ) ) - return FUNCTION_ERROR; + ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]); + if (!ret) + return ret; } end_two_bytes_buf[0] = pByteTable[i]; end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; - if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , end_two_bytes_buf , 2 ) ) - return FUNCTION_ERROR; + ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]); - return FUNCTION_SUCCESS; + return ret; } int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, @@ -321,7 +482,6 @@ int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, const unsigned char WritingValue ) { - struct mxl5005s_state *state = fe->demodulator_priv; int i; unsigned char Mask; @@ -335,82 +495,18 @@ int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, Shift = Lsb; - /* Get tuner register byte according to register adddress. */ - MXL_RegRead(&pExtra->MxlDefinedTunerStructure, RegAddr, &RegByte); + MXL_RegRead(fe, RegAddr, &RegByte); /* Reserve register byte unmask bit with mask and inlay writing value into it. */ RegByte &= ~Mask; RegByte |= (WritingValue << Shift) & Mask; /* Update tuner register byte table. */ - MXL_RegWrite(&pExtra->MxlDefinedTunerStructure, RegAddr, RegByte); + MXL_RegWrite(fe, RegAddr, RegByte); /* Write tuner register byte with writing byte. */ - if(pExtra->SetRegsWithTable( dib, pTuner, &RegAddr, &RegByte, LEN_1_BYTE) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - - return FUNCTION_SUCCESS; - - -error_status_set_tuner_registers: - return FUNCTION_ERROR; -} - -// DONE -int mxl5005s_SetSpectrumMode(struct dvb_frontend *fe, int SpectrumMode) -{ - struct mxl5005s_state *state = fe->demodulator_priv; - static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] = - { - /* BB_IQSWAP */ - 0, /* Normal spectrum */ - 1, /* Inverse spectrum */ - }; - - /* Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. */ - mxl5005s_SetRegMaskBits(fe, - MXL5005S_BB_IQSWAP_ADDR, - MXL5005S_BB_IQSWAP_MSB, - MXL5005S_BB_IQSWAP_LSB, - BbIqswapTable[SpectrumMode]); - - return FUNCTION_SUCCESS; -} - -// DONE -int mxl5005s_SetBandwidthHz(struct dvb_frontend *fe, unsigned long BandwidthHz) -{ - struct mxl5005s_state *state = fe->demodulator_priv; - - unsigned char BbDlpfBandsel; - - /* Set BB_DLPF_BANDSEL according to bandwidth. */ - switch(BandwidthHz) - { - default: - case MXL5005S_BANDWIDTH_6MHZ: - BbDlpfBandsel = 3; - break; - case MXL5005S_BANDWIDTH_7MHZ: - BbDlpfBandsel = 2; - break; - case MXL5005S_BANDWIDTH_8MHZ: - BbDlpfBandsel = 0; - break; - } - - if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB, - MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != 0) - goto error_status_set_tuner_registers; - - - return 0; - - -error_status_set_tuner_registers: - return -1; + return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); } // The following context is source code provided by MaxLinear. @@ -418,7 +514,7 @@ error_status_set_tuner_registers: // DONE u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; state->TunerRegs_Num = TUNER_REGS_NUM ; // state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; @@ -740,7 +836,7 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) // DONE u16 MXL5005_ControlInit(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; state->Init_Ctrl_Num = INITCTRL_NUM; state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; @@ -1684,7 +1780,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) // DONE void InitTunerControls(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; MXL5005_RegisterInit(fe); MXL5005_ControlInit(fe); #ifdef _MXL_INTERNAL @@ -1745,7 +1840,7 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ ) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; state->Mode = Mode; @@ -1798,8 +1893,8 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, // DONE void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; - if (Tuner->Mode == 1) /* Digital Mode */ + struct mxl5005s_state *state = fe->tuner_priv; + if (state->Mode == 1) /* Digital Mode */ state->IF_LO = state->IF_OUT; else /* Analog Mode */ { @@ -1837,7 +1932,7 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) // DONE void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; if (state->Mode == 1) /* Digital Mode */ { //remove 20.48MHz setting for 2.6.10 @@ -1876,7 +1971,6 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) // DONE u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; status += MXL_ControlWrite(fe, OVERRIDE_1, 1); @@ -1915,7 +2009,7 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) // DONE u16 MXL_BlockInit(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; status += MXL_OverwriteICDefault(fe); @@ -2096,7 +2190,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0); /* Misc Controls */ - if (state->Mode == 0 && Tuner->IF_Mode == 1) /* Analog LowIF mode */ + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */ status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0); else status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1); @@ -2155,7 +2249,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ { - Tuner->AGC_Mode = 1; /* Single AGC Mode */ + state->AGC_Mode = 1; /* Single AGC Mode */ /* Enable RSSI */ status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); @@ -2203,7 +2297,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } if (state->Mod_Type == MXL_ANALOG_CABLE) { /* Analog Cable Mode */ - /* Tuner->Mode = MXL_DIGITAL_MODE; */ + /* state->Mode = MXL_DIGITAL_MODE; */ state->AGC_Mode = 1; /* Single AGC Mode */ @@ -2269,8 +2363,9 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_IFSynthInit(Tuner_struct * Tuner) +u16 MXL_IFSynthInit(struct dvb_frontend *fe) { + struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; // Declare Local Variables u32 Fref = 0 ; @@ -2286,186 +2381,186 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner) // // IF Synthesizer Control // - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF mode + if (state->Mode == 0 && state->IF_Mode == 1) // Analog Low IF mode { - if (Tuner->IF_LO == 41000000UL) { + if (state->IF_LO == 41000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 328000000UL ; } - if (Tuner->IF_LO == 47000000UL) { + if (state->IF_LO == 47000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 376000000UL ; } - if (Tuner->IF_LO == 54000000UL) { + if (state->IF_LO == 54000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 324000000UL ; } - if (Tuner->IF_LO == 60000000UL) { + if (state->IF_LO == 60000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 39250000UL) { + if (state->IF_LO == 39250000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 314000000UL ; } - if (Tuner->IF_LO == 39650000UL) { + if (state->IF_LO == 39650000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 317200000UL ; } - if (Tuner->IF_LO == 40150000UL) { + if (state->IF_LO == 40150000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 321200000UL ; } - if (Tuner->IF_LO == 40650000UL) { + if (state->IF_LO == 40650000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 325200000UL ; } } - if (Tuner->Mode || (Tuner->Mode == 0 && Tuner->IF_Mode == 0)) + if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) { - if (Tuner->IF_LO == 57000000UL) { + if (state->IF_LO == 57000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 342000000UL ; } - if (Tuner->IF_LO == 44000000UL) { + if (state->IF_LO == 44000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352000000UL ; } - if (Tuner->IF_LO == 43750000UL) { + if (state->IF_LO == 43750000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 350000000UL ; } - if (Tuner->IF_LO == 36650000UL) { + if (state->IF_LO == 36650000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 366500000UL ; } - if (Tuner->IF_LO == 36150000UL) { + if (state->IF_LO == 36150000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 361500000UL ; } - if (Tuner->IF_LO == 36000000UL) { + if (state->IF_LO == 36000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 35250000UL) { + if (state->IF_LO == 35250000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352500000UL ; } - if (Tuner->IF_LO == 34750000UL) { + if (state->IF_LO == 34750000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 347500000UL ; } - if (Tuner->IF_LO == 6280000UL) { + if (state->IF_LO == 6280000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 376800000UL ; } - if (Tuner->IF_LO == 5000000UL) { + if (state->IF_LO == 5000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 4500000UL) { + if (state->IF_LO == 4500000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 4570000UL) { + if (state->IF_LO == 4570000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 365600000UL ; } - if (Tuner->IF_LO == 4000000UL) { + if (state->IF_LO == 4000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 57400000UL) + if (state->IF_LO == 57400000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 344400000UL ; } - if (Tuner->IF_LO == 44400000UL) + if (state->IF_LO == 44400000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 355200000UL ; } - if (Tuner->IF_LO == 44150000UL) + if (state->IF_LO == 44150000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 353200000UL ; } - if (Tuner->IF_LO == 37050000UL) + if (state->IF_LO == 37050000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 370500000UL ; } - if (Tuner->IF_LO == 36550000UL) + if (state->IF_LO == 36550000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 365500000UL ; } - if (Tuner->IF_LO == 36125000UL) { + if (state->IF_LO == 36125000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 361250000UL ; } - if (Tuner->IF_LO == 6000000UL) { + if (state->IF_LO == 6000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 5400000UL) + if (state->IF_LO == 5400000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 324000000UL ; } - if (Tuner->IF_LO == 5380000UL) { + if (state->IF_LO == 5380000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 322800000UL ; } - if (Tuner->IF_LO == 5200000UL) { + if (state->IF_LO == 5200000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 374400000UL ; } - if (Tuner->IF_LO == 4900000UL) + if (state->IF_LO == 4900000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352800000UL ; } - if (Tuner->IF_LO == 4400000UL) + if (state->IF_LO == 4400000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352000000UL ; } - if (Tuner->IF_LO == 4063000UL) //add for 2.6.8 + if (state->IF_LO == 4063000UL) //add for 2.6.8 { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; @@ -2542,7 +2637,7 @@ u32 MXL_GetXtalInt(u32 Xtal_Freq) /////////////////////////////////////////////////////////////////////////////// u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; // Declare Local Variables u16 status = 0; u32 divider_val, E3, E4, E5, E5A; @@ -3034,7 +3129,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) // // Off Chip Tracking Filter Control // - if (Tuner->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks + if (state->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks { status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; @@ -3044,7 +3139,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3 } - if (Tuner->TF_Type == MXL_TF_C) // Tracking Filter type C + if (state->TF_Type == MXL_TF_C) // Tracking Filter type C { status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; @@ -3124,7 +3219,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only + if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only { status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; @@ -3194,7 +3289,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_D) // Tracking Filter type D + if (state->TF_Type == MXL_TF_D) // Tracking Filter type D { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3251,7 +3346,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } - if (Tuner->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 + if (state->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 { status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; @@ -3336,7 +3431,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_E) // Tracking Filter type E + if (state->TF_Type == MXL_TF_E) // Tracking Filter type E { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3392,7 +3487,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_F) // Tracking Filter type F + if (state->TF_Type == MXL_TF_F) // Tracking Filter type F { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3448,7 +3543,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 + if (state->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3504,7 +3599,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 + if (state->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3567,7 +3662,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 + if (state->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3667,7 +3762,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) // DONE u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; if (GPIO_Num == 1) @@ -3735,14 +3829,13 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) // DONE u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; /* Will write ALL Matching Control Name */ - status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control * - status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control * + status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control */ + status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control */ #ifdef _MXL_INTERNAL - status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control * + status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control */ #endif return status; } @@ -3777,7 +3870,7 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) // DONE u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 i, j, k; u32 highLimit; u32 ctrlVal; @@ -3884,7 +3977,7 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u // DONE u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; int i ; for (i = 0; i < 104; i++) { @@ -3924,7 +4017,7 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) // DONE u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; int i ; for (i = 0; i < 104; i++) { @@ -3959,9 +4052,9 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) // // /////////////////////////////////////////////////////////////////////////////// // DONE -u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 * value) +u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u32 ctrlVal ; u16 i, k ; @@ -4033,7 +4126,7 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 * value) // DONE u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 i, j, k ; u16 Count ; @@ -4139,7 +4232,7 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int // DONE void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; int i ; const u8 AND_MAP[8] = { @@ -4196,7 +4289,6 @@ u32 MXL_Ceiling(u32 value, u32 resolution) // DONE u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i ; @@ -4220,7 +4312,6 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c // DONE u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i ; @@ -4249,7 +4340,6 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou // DONE u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i; @@ -4268,7 +4358,6 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i // DONE u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i; @@ -4302,7 +4391,7 @@ u16 MXL_GetMasterControl(u8 *MasterReg, int state) #ifdef _MXL_PRODUCTION u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; if (VCO_Range == 1) { @@ -4432,7 +4521,7 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) // DONE u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; if (Hystersis == 1) @@ -4443,3 +4532,194 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) #endif +/* Linux driver related functions */ + + +int mxl5005s_init2(struct dvb_frontend *fe) +{ + int MxlModMode; + int MxlIfMode; + unsigned long MxlBandwitdh; + unsigned long MxlIfFreqHz; + unsigned long MxlCrystalFreqHz; + int MxlAgcMode; + unsigned short MxlTop; + unsigned short MxlIfOutputLoad; + int MxlClockOut; + int MxlDivOut; + int MxlCapSel; + int MxlRssiOnOff; + unsigned char MxlStandard; + unsigned char MxlTfType; + + /* Set MxL5005S parameters. */ + MxlModMode = MXL_DIGITAL_MODE; + MxlIfMode = MXL_ZERO_IF; +// steve + //MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; + //MxlIfFreqHz = IF_FREQ_4570000HZ; + MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config + MxlIfFreqHz = IF_FREQ_5380000HZ; // config + MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config + MxlAgcMode = MXL_SINGLE_AGC; + MxlTop = MXL5005S_TOP_25P2; + MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; + MxlClockOut = MXL_CLOCK_OUT_DISABLE; + MxlDivOut = MXL_DIV_OUT_4; + MxlCapSel = MXL_CAP_SEL_ENABLE; + MxlRssiOnOff = MXL_RSSI_ENABLE; // config + MxlTfType = MXL_TF_C_H; // config + + MxlStandard = MXL_ATSC; // config + + // TODO: this is bad, it trashes other configs + // Set MxL5005S extra module. + //pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; + + MXL5005_TunerConfig( + fe, + (unsigned char)MxlModMode, + (unsigned char)MxlIfMode, + MxlBandwitdh, + MxlIfFreqHz, + MxlCrystalFreqHz, + (unsigned char)MxlAgcMode, + MxlTop, + MxlIfOutputLoad, + (unsigned char)MxlClockOut, + (unsigned char)MxlDivOut, + (unsigned char)MxlCapSel, + (unsigned char)MxlRssiOnOff, + MxlStandard, MxlTfType); + + return 0; +} + +static int mxl5005s_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + u32 freq; + u32 bw; + + if (fe->ops.info.type == FE_OFDM) + bw = params->u.ofdm.bandwidth; + else + bw = MXL5005S_BANDWIDTH_6MHZ; + + freq = params->frequency; /* Hz */ + dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); + + return mxl5005s_SetRfFreqHz(fe, freq); +} + +static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + + *frequency = state->RF_IN; + + return 0; +} + +static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + + *bandwidth = state->Chan_Bandwidth; + + return 0; +} + +static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status) +{ + dprintk(1, "%s()\n", __func__); + + *status = 0; + // *status = TUNER_STATUS_LOCKED; + + return 0; +} + +static int mxl5005s_init(struct dvb_frontend *fe) +{ + struct mxl5005s_state *state = fe->tuner_priv; + u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + int TableLen; + + dprintk(1, "%s()\n", __func__); + + /* Initialize MxL5005S tuner according to MxL5005S tuner example code. */ + + /* Tuner initialization stage 0 */ + MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); + AddrTable[0] = MASTER_CONTROL_ADDR; + ByteTable[0] |= state->config->AgcMasterByte; + + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + + /* Tuner initialization stage 1 */ + MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); + + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + + return mxl5005s_init2(fe); +} + +static int mxl5005s_release(struct dvb_frontend *fe) +{ + dprintk(1, "%s()\n", __func__); + kfree(fe->tuner_priv); + fe->tuner_priv = NULL; + return 0; +} + +static const struct dvb_tuner_ops mxl5005s_tuner_ops = { + .info = { + .name = "MaxLinear MXL5005S", + .frequency_min = 48000000, + .frequency_max = 860000000, + .frequency_step = 50000, + }, + + .release = mxl5005s_release, + .init = mxl5005s_init, + + .set_params = mxl5005s_set_params, + .get_frequency = mxl5005s_get_frequency, + .get_bandwidth = mxl5005s_get_bandwidth, + .get_status = mxl5005s_get_status +}; + +struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct mxl5005s_config *config) +{ + struct mxl5005s_state *state = NULL; + dprintk(1, "%s()\n", __func__); + + state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL); + if (state == NULL) + return NULL; + + state->frontend = fe; + state->config = config; + state->i2c = i2c; + + printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); + + memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, sizeof(struct dvb_tuner_ops)); + + fe->tuner_priv = state; + return fe; +} +EXPORT_SYMBOL(mxl5005s_attach); + +MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); +MODULE_AUTHOR("Jan Hoogenraad"); +MODULE_AUTHOR("Barnaby Shearer"); +MODULE_AUTHOR("Andy Hasper"); +MODULE_AUTHOR("Steven Toth"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h index df49826816bb..1c4d9da8e1fe 100644 --- a/drivers/media/common/tuners/mxl5005s.h +++ b/drivers/media/common/tuners/mxl5005s.h @@ -26,273 +26,48 @@ #ifndef __MXL5005S_H #define __MXL5005S_H -/* - * The following context is source code provided by MaxLinear. - * MaxLinear source code - Common.h - */ - -typedef void *HANDLE; /* Pointer to memory location */ - -#define TUNER_REGS_NUM 104 -#define INITCTRL_NUM 40 - -#ifdef _MXL_PRODUCTION -#define CHCTRL_NUM 39 -#else -#define CHCTRL_NUM 36 -#endif - -#define MXLCTRL_NUM 189 -#define MASTER_CONTROL_ADDR 9 - -/* Enumeration of AGC Mode */ -typedef enum -{ - MXL_DUAL_AGC = 0, - MXL_SINGLE_AGC -} AGC_Mode; - -/* Enumeration of Master Control Register State */ -typedef enum -{ - MC_LOAD_START = 1, - MC_POWER_DOWN, - MC_SYNTH_RESET, - MC_SEQ_OFF -} Master_Control_State; - -/* Enumeration of MXL5005 Tuner Mode */ -typedef enum -{ - MXL_ANALOG_MODE = 0, - MXL_DIGITAL_MODE -} Tuner_Mode; - -/* Enumeration of MXL5005 Tuner IF Mode */ -typedef enum -{ - MXL_ZERO_IF = 0, - MXL_LOW_IF -} Tuner_IF_Mode; - -/* Enumeration of MXL5005 Tuner Clock Out Mode */ -typedef enum -{ - MXL_CLOCK_OUT_DISABLE = 0, - MXL_CLOCK_OUT_ENABLE -} Tuner_Clock_Out; - -/* Enumeration of MXL5005 Tuner Div Out Mode */ -typedef enum -{ - MXL_DIV_OUT_1 = 0, - MXL_DIV_OUT_4 - -} Tuner_Div_Out; - -/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ -typedef enum -{ - MXL_CAP_SEL_DISABLE = 0, - MXL_CAP_SEL_ENABLE - -} Tuner_Cap_Select; - -/* Enumeration of MXL5005 Tuner RSSI Mode */ -typedef enum -{ - MXL_RSSI_DISABLE = 0, - MXL_RSSI_ENABLE - -} Tuner_RSSI; - -/* Enumeration of MXL5005 Tuner Modulation Type */ -typedef enum -{ - MXL_DEFAULT_MODULATION = 0, - MXL_DVBT, - MXL_ATSC, - MXL_QAM, - MXL_ANALOG_CABLE, - MXL_ANALOG_OTA -} Tuner_Modu_Type; - -/* Enumeration of MXL5005 Tuner Tracking Filter Type */ -typedef enum -{ - MXL_TF_DEFAULT = 0, - MXL_TF_OFF, - MXL_TF_C, - MXL_TF_C_H, - MXL_TF_D, - MXL_TF_D_L, - MXL_TF_E, - MXL_TF_F, - MXL_TF_E_2, - MXL_TF_E_NA, - MXL_TF_G -} Tuner_TF_Type; - -/* MXL5005 Tuner Register Struct */ -typedef struct _TunerReg_struct -{ - u16 Reg_Num; /* Tuner Register Address */ - u16 Reg_Val; /* Current sofware programmed value waiting to be writen */ -} TunerReg_struct; - -typedef enum -{ - /* Initialization Control Names */ - DN_IQTN_AMP_CUT = 1, /* 1 */ - BB_MODE, /* 2 */ - BB_BUF, /* 3 */ - BB_BUF_OA, /* 4 */ - BB_ALPF_BANDSELECT, /* 5 */ - BB_IQSWAP, /* 6 */ - BB_DLPF_BANDSEL, /* 7 */ - RFSYN_CHP_GAIN, /* 8 */ - RFSYN_EN_CHP_HIGAIN, /* 9 */ - AGC_IF, /* 10 */ - AGC_RF, /* 11 */ - IF_DIVVAL, /* 12 */ - IF_VCO_BIAS, /* 13 */ - CHCAL_INT_MOD_IF, /* 14 */ - CHCAL_FRAC_MOD_IF, /* 15 */ - DRV_RES_SEL, /* 16 */ - I_DRIVER, /* 17 */ - EN_AAF, /* 18 */ - EN_3P, /* 19 */ - EN_AUX_3P, /* 20 */ - SEL_AAF_BAND, /* 21 */ - SEQ_ENCLK16_CLK_OUT, /* 22 */ - SEQ_SEL4_16B, /* 23 */ - XTAL_CAPSELECT, /* 24 */ - IF_SEL_DBL, /* 25 */ - RFSYN_R_DIV, /* 26 */ - SEQ_EXTSYNTHCALIF, /* 27 */ - SEQ_EXTDCCAL, /* 28 */ - AGC_EN_RSSI, /* 29 */ - RFA_ENCLKRFAGC, /* 30 */ - RFA_RSSI_REFH, /* 31 */ - RFA_RSSI_REF, /* 32 */ - RFA_RSSI_REFL, /* 33 */ - RFA_FLR, /* 34 */ - RFA_CEIL, /* 35 */ - SEQ_EXTIQFSMPULSE, /* 36 */ - OVERRIDE_1, /* 37 */ - BB_INITSTATE_DLPF_TUNE, /* 38 */ - TG_R_DIV, /* 39 */ - EN_CHP_LIN_B, /* 40 */ - - /* Channel Change Control Names */ - DN_POLY = 51, /* 51 */ - DN_RFGAIN, /* 52 */ - DN_CAP_RFLPF, /* 53 */ - DN_EN_VHFUHFBAR, /* 54 */ - DN_GAIN_ADJUST, /* 55 */ - DN_IQTNBUF_AMP, /* 56 */ - DN_IQTNGNBFBIAS_BST, /* 57 */ - RFSYN_EN_OUTMUX, /* 58 */ - RFSYN_SEL_VCO_OUT, /* 59 */ - RFSYN_SEL_VCO_HI, /* 60 */ - RFSYN_SEL_DIVM, /* 61 */ - RFSYN_RF_DIV_BIAS, /* 62 */ - DN_SEL_FREQ, /* 63 */ - RFSYN_VCO_BIAS, /* 64 */ - CHCAL_INT_MOD_RF, /* 65 */ - CHCAL_FRAC_MOD_RF, /* 66 */ - RFSYN_LPF_R, /* 67 */ - CHCAL_EN_INT_RF, /* 68 */ - TG_LO_DIVVAL, /* 69 */ - TG_LO_SELVAL, /* 70 */ - TG_DIV_VAL, /* 71 */ - TG_VCO_BIAS, /* 72 */ - SEQ_EXTPOWERUP, /* 73 */ - OVERRIDE_2, /* 74 */ - OVERRIDE_3, /* 75 */ - OVERRIDE_4, /* 76 */ - SEQ_FSM_PULSE, /* 77 */ - GPIO_4B, /* 78 */ - GPIO_3B, /* 79 */ - GPIO_4, /* 80 */ - GPIO_3, /* 81 */ - GPIO_1B, /* 82 */ - DAC_A_ENABLE, /* 83 */ - DAC_B_ENABLE, /* 84 */ - DAC_DIN_A, /* 85 */ - DAC_DIN_B, /* 86 */ -#ifdef _MXL_PRODUCTION - RFSYN_EN_DIV, /* 87 */ - RFSYN_DIVM, /* 88 */ - DN_BYPASS_AGC_I2C /* 89 */ -#endif -} MXL5005_ControlName; - -/* End of common.h */ - -/* - * The following context is source code provided by MaxLinear. - * MaxLinear source code - Common_MXL.h (?) - */ - -/* Constants */ -#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 -#define MXL5005S_LATCH_BYTE 0xfe - -/* Register address, MSB, and LSB */ -#define MXL5005S_BB_IQSWAP_ADDR 59 -#define MXL5005S_BB_IQSWAP_MSB 0 -#define MXL5005S_BB_IQSWAP_LSB 0 - -#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53 -#define MXL5005S_BB_DLPF_BANDSEL_MSB 4 -#define MXL5005S_BB_DLPF_BANDSEL_LSB 3 - -/* Standard modes */ -enum -{ - MXL5005S_STANDARD_DVBT, - MXL5005S_STANDARD_ATSC, +/* IF frequency */ +enum IF_FREQ_HZ +{ + IF_FREQ_4570000HZ = 4570000, ///< IF frequency = 4.57 MHz + IF_FREQ_4571429HZ = 4571429, ///< IF frequency = 4.571 MHz + IF_FREQ_5380000HZ = 5380000, ///< IF frequency = 5.38 MHz + IF_FREQ_36000000HZ = 36000000, ///< IF frequency = 36.000 MHz + IF_FREQ_36125000HZ = 36125000, ///< IF frequency = 36.125 MHz + IF_FREQ_36166667HZ = 36166667, ///< IF frequency = 36.167 MHz + IF_FREQ_44000000HZ = 44000000, ///< IF frequency = 44.000 MHz }; -#define MXL5005S_STANDARD_MODE_NUM 2 -/* Bandwidth modes */ -enum +/* Crystal frequency */ +enum CRYSTAL_FREQ_HZ { - MXL5005S_BANDWIDTH_6MHZ = 6000000, - MXL5005S_BANDWIDTH_7MHZ = 7000000, - MXL5005S_BANDWIDTH_8MHZ = 8000000, + CRYSTAL_FREQ_4000000HZ = 4000000, ///< Crystal frequency = 4.0 MHz + CRYSTAL_FREQ_16000000HZ = 16000000, ///< Crystal frequency = 16.0 MHz + CRYSTAL_FREQ_25000000HZ = 25000000, ///< Crystal frequency = 25.0 MHz + CRYSTAL_FREQ_28800000HZ = 28800000, ///< Crystal frequency = 28.8 MHz }; -#define MXL5005S_BANDWIDTH_MODE_NUM 3 -/* Top modes */ -enum +struct mxl5005s_config { - MXL5005S_TOP_5P5 = 55, - MXL5005S_TOP_7P2 = 72, - MXL5005S_TOP_9P2 = 92, - MXL5005S_TOP_11P0 = 110, - MXL5005S_TOP_12P9 = 129, - MXL5005S_TOP_14P7 = 147, - MXL5005S_TOP_16P8 = 168, - MXL5005S_TOP_19P4 = 194, - MXL5005S_TOP_21P2 = 212, - MXL5005S_TOP_23P2 = 232, - MXL5005S_TOP_25P2 = 252, - MXL5005S_TOP_27P1 = 271, - MXL5005S_TOP_29P2 = 292, - MXL5005S_TOP_31P7 = 317, - MXL5005S_TOP_34P9 = 349, -}; + u8 i2c_address; -/* IF output load */ -enum -{ - MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, - MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, + /* Stuff I don't know what to do with */ + u8 AgcMasterByte; }; -/* End of common_mxl.h (?) */ +#if defined(CONFIG_DVB_TUNER_MXL5005S) || (defined(CONFIG_DVB_TUNER_MXL5005S_MODULE) && defined(MODULE)) +extern struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct mxl5005s_config *config); +#else +static inline struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct mxl5005s_config *config); +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif /* CONFIG_DVB_TUNER_MXL5005S */ #endif /* __MXL5005S_H */ -- cgit v1.2.3 From 8c66a19d45fb5b88abf10678db353f35179a2cde Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 06:35:48 -0300 Subject: V4L/DVB (7868): mxl5005s: Cleanup #5 Cleanup #5 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 304 +++++++++++---------------------- drivers/media/common/tuners/mxl5005s.h | 99 ++++++++--- 2 files changed, 181 insertions(+), 222 deletions(-) diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 7e687171301b..aad88d5c0dc2 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -24,10 +24,10 @@ #include "mxl5005s.h" -static int debug; +static int debug = 2; #define dprintk(level, arg...) do { \ - if (debug >= level) \ + if (level <= debug) \ printk(arg); \ } while (0) @@ -43,13 +43,6 @@ static int debug; #define MXLCTRL_NUM 189 #define MASTER_CONTROL_ADDR 9 -/* Enumeration of AGC Mode */ -typedef enum -{ - MXL_DUAL_AGC = 0, - MXL_SINGLE_AGC -} AGC_Mode; - /* Enumeration of Master Control Register State */ typedef enum { @@ -59,51 +52,6 @@ typedef enum MC_SEQ_OFF } Master_Control_State; -/* Enumeration of MXL5005 Tuner Mode */ -typedef enum -{ - MXL_ANALOG_MODE = 0, - MXL_DIGITAL_MODE -} Tuner_Mode; - -/* Enumeration of MXL5005 Tuner IF Mode */ -typedef enum -{ - MXL_ZERO_IF = 0, - MXL_LOW_IF -} Tuner_IF_Mode; - -/* Enumeration of MXL5005 Tuner Clock Out Mode */ -typedef enum -{ - MXL_CLOCK_OUT_DISABLE = 0, - MXL_CLOCK_OUT_ENABLE -} Tuner_Clock_Out; - -/* Enumeration of MXL5005 Tuner Div Out Mode */ -typedef enum -{ - MXL_DIV_OUT_1 = 0, - MXL_DIV_OUT_4 - -} Tuner_Div_Out; - -/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ -typedef enum -{ - MXL_CAP_SEL_DISABLE = 0, - MXL_CAP_SEL_ENABLE - -} Tuner_Cap_Select; - -/* Enumeration of MXL5005 Tuner RSSI Mode */ -typedef enum -{ - MXL_RSSI_DISABLE = 0, - MXL_RSSI_ENABLE - -} Tuner_RSSI; - /* Enumeration of MXL5005 Tuner Modulation Type */ typedef enum { @@ -115,22 +63,6 @@ typedef enum MXL_ANALOG_OTA } Tuner_Modu_Type; -/* Enumeration of MXL5005 Tuner Tracking Filter Type */ -typedef enum -{ - MXL_TF_DEFAULT = 0, - MXL_TF_OFF, - MXL_TF_C, - MXL_TF_C_H, - MXL_TF_D, - MXL_TF_D_L, - MXL_TF_E, - MXL_TF_F, - MXL_TF_E_2, - MXL_TF_E_NA, - MXL_TF_G -} Tuner_TF_Type; - /* MXL5005 Tuner Register Struct */ typedef struct _TunerReg_struct { @@ -261,33 +193,6 @@ enum }; #define MXL5005S_BANDWIDTH_MODE_NUM 3 -/* Top modes */ -enum -{ - MXL5005S_TOP_5P5 = 55, - MXL5005S_TOP_7P2 = 72, - MXL5005S_TOP_9P2 = 92, - MXL5005S_TOP_11P0 = 110, - MXL5005S_TOP_12P9 = 129, - MXL5005S_TOP_14P7 = 147, - MXL5005S_TOP_16P8 = 168, - MXL5005S_TOP_19P4 = 194, - MXL5005S_TOP_21P2 = 212, - MXL5005S_TOP_23P2 = 232, - MXL5005S_TOP_25P2 = 252, - MXL5005S_TOP_27P1 = 271, - MXL5005S_TOP_29P2 = 292, - MXL5005S_TOP_31P7 = 317, - MXL5005S_TOP_34P9 = 349, -}; - -/* IF output load */ -enum -{ - MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, - MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, -}; - /* MXL5005 Tuner Control Struct */ typedef struct _TunerControl_struct { u16 Ctrl_Num; /* Control Number */ @@ -342,8 +247,7 @@ struct mxl5005s_state TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ /* Linux driver framework specific */ - const struct mxl5005s_config *config; - + struct mxl5005s_config *config; struct dvb_frontend *frontend; struct i2c_adapter *i2c; }; @@ -367,11 +271,11 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); u16 MXL_IFSynthInit(struct dvb_frontend *fe); +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe); int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { struct mxl5005s_state *state = fe->tuner_priv; - u8 AgcMasterByte = state->config->AgcMasterByte; unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; @@ -402,13 +306,13 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | AgcMasterByte; + ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; TableLen += 1; mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); // Wait 30 ms. - msleep(30); + msleep(150); // Tuner RF frequency setting stage 2 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; @@ -417,39 +321,56 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; + ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; TableLen += 1; mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + msleep(100); + return 0; } -/* Write a single byte to a single reg */ -static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val) +static int mxl5005s_reset(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[2] = { reg, val }; + int ret = 0; + + u8 buf[2] = { 0xff, 0x00 }; struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, .buf = buf, .len = 2 }; + dprintk(2, "%s()\n", __func__); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write failed\n"); - return -EREMOTEIO; + printk(KERN_WARNING "mxl5005s I2C reset failed\n"); + ret = -EREMOTEIO; } - return 0; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return ret; } -/* Write a word to a single reg */ -static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) +/* Write a single byte to a single reg */ +static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) { struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[3] = { reg, val >> 8 , val & 0xff }; + u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, .buf = buf, .len = 3 }; + if(latch == 0) + msg.len = 2; + + dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); + if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write16 failed\n"); + printk(KERN_WARNING "mxl5005s I2C write failed\n"); return -EREMOTEIO; } return 0; @@ -457,20 +378,22 @@ static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) { - int i, ret; - u8 end_two_bytes_buf[]={ 0 , 0 }; + int i, ret = 0; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); for( i = 0 ; i < TableLen - 1 ; i++) { - ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]); - if (!ret) - return ret; + ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 0); + if (ret < 0) + break; } - end_two_bytes_buf[0] = pByteTable[i]; - end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; + ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 1); - ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); return ret; } @@ -509,6 +432,7 @@ int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); } + // The following context is source code provided by MaxLinear. // MaxLinear source code - MXL5005_Initialize.cpp // DONE @@ -2034,6 +1958,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); break; case 6000000: + printk("%s() doing 6MHz digital\n", __func__); status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); break; } @@ -2064,7 +1989,6 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) else /* Single AGC Mode Dig Ana */ status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); - if (state->TOP == 55) /* TOP == 5.5 */ status += MXL_ControlWrite(fe, AGC_IF, 0x0); @@ -2294,6 +2218,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_IQSWAP, 0); else /* High IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 1); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2); + } if (state->Mod_Type == MXL_ANALOG_CABLE) { /* Analog Cable Mode */ @@ -2330,7 +2256,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } /* RSSI disable */ - if(state->EN_RSSI==0) { + if(state->EN_RSSI == 0) { status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); @@ -2539,6 +2465,7 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe) Fref = 324000000UL ; } if (state->IF_LO == 5380000UL) { + printk("%s() doing 5.38\n", __func__); status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 322800000UL ; @@ -3221,6 +3148,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only { + printk("%s() CH filter\n", __func__); status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) @@ -4534,63 +4462,59 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) /* Linux driver related functions */ +int mxl5005s_init(struct dvb_frontend *fe) +{ + struct mxl5005s_state *state = fe->tuner_priv; + + u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + int TableLen; + + dprintk(1, "%s()\n", __func__); + + mxl5005s_reset(fe); + + /* Tuner initialization stage 0 */ + MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); + AddrTable[0] = MASTER_CONTROL_ADDR; + ByteTable[0] |= state->config->AgcMasterByte; -int mxl5005s_init2(struct dvb_frontend *fe) + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + + mxl5005s_AssignTunerMode(fe); // tunre_config + + /* Tuner initialization stage 1 */ + MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); + + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + + return 0; +} + +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe) { - int MxlModMode; - int MxlIfMode; - unsigned long MxlBandwitdh; - unsigned long MxlIfFreqHz; - unsigned long MxlCrystalFreqHz; - int MxlAgcMode; - unsigned short MxlTop; - unsigned short MxlIfOutputLoad; - int MxlClockOut; - int MxlDivOut; - int MxlCapSel; - int MxlRssiOnOff; - unsigned char MxlStandard; - unsigned char MxlTfType; + struct mxl5005s_state *state = fe->tuner_priv; + struct mxl5005s_config *c = state->config; - /* Set MxL5005S parameters. */ - MxlModMode = MXL_DIGITAL_MODE; - MxlIfMode = MXL_ZERO_IF; -// steve - //MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; - //MxlIfFreqHz = IF_FREQ_4570000HZ; - MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config - MxlIfFreqHz = IF_FREQ_5380000HZ; // config - MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config - MxlAgcMode = MXL_SINGLE_AGC; - MxlTop = MXL5005S_TOP_25P2; - MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; - MxlClockOut = MXL_CLOCK_OUT_DISABLE; - MxlDivOut = MXL_DIV_OUT_4; - MxlCapSel = MXL_CAP_SEL_ENABLE; - MxlRssiOnOff = MXL_RSSI_ENABLE; // config - MxlTfType = MXL_TF_C_H; // config - - MxlStandard = MXL_ATSC; // config - - // TODO: this is bad, it trashes other configs - // Set MxL5005S extra module. - //pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; + InitTunerControls(fe); + /* Set MxL5005S parameters. */ MXL5005_TunerConfig( fe, - (unsigned char)MxlModMode, - (unsigned char)MxlIfMode, - MxlBandwitdh, - MxlIfFreqHz, - MxlCrystalFreqHz, - (unsigned char)MxlAgcMode, - MxlTop, - MxlIfOutputLoad, - (unsigned char)MxlClockOut, - (unsigned char)MxlDivOut, - (unsigned char)MxlCapSel, - (unsigned char)MxlRssiOnOff, - MxlStandard, MxlTfType); + c->mod_mode, + c->if_mode, + MXL5005S_BANDWIDTH_6MHZ, + c->if_freq, + c->xtal_freq, + c->agc_mode, + c->top, + c->output_load, + c->clock_out, + c->div_out, + c->cap_select, + c->rssi_enable, + MXL_QAM, + c->tracking_filter); return 0; } @@ -4609,7 +4533,11 @@ static int mxl5005s_set_params(struct dvb_frontend *fe, freq = params->frequency; /* Hz */ dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); - return mxl5005s_SetRfFreqHz(fe, freq); + mxl5005s_SetRfFreqHz(fe, freq); + + msleep(350); + + return 0; } static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) @@ -4642,32 +4570,6 @@ static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status) return 0; } -static int mxl5005s_init(struct dvb_frontend *fe) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; - u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; - int TableLen; - - dprintk(1, "%s()\n", __func__); - - /* Initialize MxL5005S tuner according to MxL5005S tuner example code. */ - - /* Tuner initialization stage 0 */ - MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); - AddrTable[0] = MASTER_CONTROL_ADDR; - ByteTable[0] |= state->config->AgcMasterByte; - - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); - - /* Tuner initialization stage 1 */ - MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); - - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); - - return mxl5005s_init2(fe); -} - static int mxl5005s_release(struct dvb_frontend *fe) { dprintk(1, "%s()\n", __func__); diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h index 1c4d9da8e1fe..2777ecc20d19 100644 --- a/drivers/media/common/tuners/mxl5005s.h +++ b/drivers/media/common/tuners/mxl5005s.h @@ -26,31 +26,88 @@ #ifndef __MXL5005S_H #define __MXL5005S_H -/* IF frequency */ -enum IF_FREQ_HZ -{ - IF_FREQ_4570000HZ = 4570000, ///< IF frequency = 4.57 MHz - IF_FREQ_4571429HZ = 4571429, ///< IF frequency = 4.571 MHz - IF_FREQ_5380000HZ = 5380000, ///< IF frequency = 5.38 MHz - IF_FREQ_36000000HZ = 36000000, ///< IF frequency = 36.000 MHz - IF_FREQ_36125000HZ = 36125000, ///< IF frequency = 36.125 MHz - IF_FREQ_36166667HZ = 36166667, ///< IF frequency = 36.167 MHz - IF_FREQ_44000000HZ = 44000000, ///< IF frequency = 44.000 MHz -}; - -/* Crystal frequency */ -enum CRYSTAL_FREQ_HZ -{ - CRYSTAL_FREQ_4000000HZ = 4000000, ///< Crystal frequency = 4.0 MHz - CRYSTAL_FREQ_16000000HZ = 16000000, ///< Crystal frequency = 16.0 MHz - CRYSTAL_FREQ_25000000HZ = 25000000, ///< Crystal frequency = 25.0 MHz - CRYSTAL_FREQ_28800000HZ = 28800000, ///< Crystal frequency = 28.8 MHz -}; - struct mxl5005s_config { + /* 7 bit i2c address */ u8 i2c_address; +#define IF_FREQ_4570000HZ 4570000 +#define IF_FREQ_4571429HZ 4571429 +#define IF_FREQ_5380000HZ 5380000 +#define IF_FREQ_36000000HZ 36000000 +#define IF_FREQ_36125000HZ 36125000 +#define IF_FREQ_36166667HZ 36166667 +#define IF_FREQ_44000000HZ 44000000 + u32 if_freq; + +#define CRYSTAL_FREQ_4000000HZ 4000000 +#define CRYSTAL_FREQ_16000000HZ 16000000 +#define CRYSTAL_FREQ_25000000HZ 25000000 +#define CRYSTAL_FREQ_28800000HZ 28800000 + u32 xtal_freq; + +#define MXL_DUAL_AGC 0 +#define MXL_SINGLE_AGC 1 + u8 agc_mode; + +#define MXL_TF_DEFAULT 0 +#define MXL_TF_OFF 1 +#define MXL_TF_C 2 +#define MXL_TF_C_H 3 +#define MXL_TF_D 4 +#define MXL_TF_D_L 5 +#define MXL_TF_E 6 +#define MXL_TF_F 7 +#define MXL_TF_E_2 8 +#define MXL_TF_E_NA 9 +#define MXL_TF_G 10 + u8 tracking_filter; + +#define MXL_RSSI_DISABLE 0 +#define MXL_RSSI_ENABLE 1 + u8 rssi_enable; + +#define MXL_CAP_SEL_DISABLE 0 +#define MXL_CAP_SEL_ENABLE 1 + u8 cap_select; + +#define MXL_DIV_OUT_1 0 +#define MXL_DIV_OUT_4 1 + u8 div_out; + +#define MXL_CLOCK_OUT_DISABLE 0 +#define MXL_CLOCK_OUT_ENABLE 1 + u8 clock_out; + +#define MXL5005S_IF_OUTPUT_LOAD_200_OHM 200 +#define MXL5005S_IF_OUTPUT_LOAD_300_OHM 300 + u32 output_load; + +#define MXL5005S_TOP_5P5 55 +#define MXL5005S_TOP_7P2 72 +#define MXL5005S_TOP_9P2 92 +#define MXL5005S_TOP_11P0 110 +#define MXL5005S_TOP_12P9 129 +#define MXL5005S_TOP_14P7 147 +#define MXL5005S_TOP_16P8 168 +#define MXL5005S_TOP_19P4 194 +#define MXL5005S_TOP_21P2 212 +#define MXL5005S_TOP_23P2 232 +#define MXL5005S_TOP_25P2 252 +#define MXL5005S_TOP_27P1 271 +#define MXL5005S_TOP_29P2 292 +#define MXL5005S_TOP_31P7 317 +#define MXL5005S_TOP_34P9 349 + u32 top; + +#define MXL_ANALOG_MODE 0 +#define MXL_DIGITAL_MODE 1 + u8 mod_mode; + +#define MXL_ZERO_IF 0 +#define MXL_LOW_IF 1 + u8 if_mode; + /* Stuff I don't know what to do with */ u8 AgcMasterByte; }; -- cgit v1.2.3 From 7f5c3affef2883f49e820db62413e1dff1d4cebb Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 06:51:36 -0300 Subject: V4L/DVB(7869): mxl5005s: Cleanup #6 Cleanup #6 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 414 ++++++++++++++++++--------------- drivers/media/common/tuners/mxl5005s.h | 48 ++-- 2 files changed, 248 insertions(+), 214 deletions(-) diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index aad88d5c0dc2..f7ed9a72db4a 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -1,26 +1,62 @@ /* - * For the Realtek RTL chip RTL2831U - * Realtek Release Date: 2008-03-14, ver 080314 - * Realtek version RTL2831 Linux driver version 080314 - * ver 080314 - * - * for linux kernel version 2.6.21.4 - 2.6.22-14 - * support MXL5005s and MT2060 tuners (support tuner auto-detecting) - * support two IR types -- RC5 and NEC - * - * Known boards with Realtek RTL chip RTL2821U - * Freecom USB stick 14aa:0160 (version 4) - * Conceptronic CTVDIGRCU - * - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - * This code is placed under the terms of the GNU General Public License - * - * Released by Realtek under GPLv2. - * Thanks to Realtek for a lot of support we received ! - * - * Revision: 080314 - original version - */ + MaxLinear MXL5005S VSB/QAM/DVBT tuner driver + + Copyright (C) 2008 MaxLinear + Copyright (C) 2006 Steven Toth + Functions: + mxl5005s_reset() + mxl5005s_writereg() + mxl5005s_writeregs() + mxl5005s_init() + mxl5005s_reconfigure() + mxl5005s_AssignTunerMode() + mxl5005s_set_params() + mxl5005s_get_frequency() + mxl5005s_get_bandwidth() + mxl5005s_release() + mxl5005s_attach() + + Copyright (c) 2008 Realtek + Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + Functions: + mxl5005s_SetRfFreqHz() + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + +*/ + +/* + History of this driver (Steven Toth): + I was given a public release of a linux driver that included + support for the MaxLinear MXL5005S silicon tuner. Analysis of + the tuner driver showed clearly three things. + + 1. The tuner driver didn't support the LinuxTV tuner API + so the code Realtek added had to be removed. + + 2. A significant amount of the driver is reference driver code + from MaxLinear, I felt it was important to identify and + preserve this. + + 3. New code has to be added to interface correctly with the + LinuxTV API, as a regular kernel module. + + Other than the reference driver enum's, I've clearly marked + sections of the code and retained the copyright of the + respective owners. +*/ #include "mxl5005s.h" @@ -250,9 +286,12 @@ struct mxl5005s_state struct mxl5005s_config *config; struct dvb_frontend *frontend; struct i2c_adapter *i2c; + + /* Cache values */ + u32 current_mode; + }; -// funcs u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); u16 MXL_GetMasterControl(u8 *MasterReg, int state); @@ -269,9 +308,22 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); u16 MXL_IFSynthInit(struct dvb_frontend *fe); -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe); +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); +int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); + +/* ---------------------------------------------------------------- + * Begin: Custom code salvaged from the Realtek driver. + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { @@ -292,7 +344,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); // Tuner RF frequency setting stage 1 MXL_TuneRF(fe, RfFreqHz); @@ -309,7 +361,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; TableLen += 1; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); // Wait 30 ms. msleep(150); @@ -324,118 +376,18 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; TableLen += 1; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); msleep(100); return 0; } +/* End: Custom code taken from the Realtek driver */ -static int mxl5005s_reset(struct dvb_frontend *fe) -{ - struct mxl5005s_state *state = fe->tuner_priv; - int ret = 0; - - u8 buf[2] = { 0xff, 0x00 }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 2 }; - - dprintk(2, "%s()\n", __func__); - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C reset failed\n"); - ret = -EREMOTEIO; - } - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return ret; -} - -/* Write a single byte to a single reg */ -static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 3 }; - - if(latch == 0) - msg.len = 2; - - dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); - - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write failed\n"); - return -EREMOTEIO; - } - return 0; -} - -int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) -{ - int i, ret = 0; - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - - for( i = 0 ; i < TableLen - 1 ; i++) - { - ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 0); - if (ret < 0) - break; - } - - ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 1); - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return ret; -} - -int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, - unsigned char RegAddr, - unsigned char Msb, - unsigned char Lsb, - const unsigned char WritingValue - ) -{ - int i; - - unsigned char Mask; - unsigned char Shift; - unsigned char RegByte; - - /* Generate mask and shift according to MSB and LSB. */ - Mask = 0; - for(i = Lsb; i < (unsigned char)(Msb + 1); i++) - Mask |= 0x1 << i; - - Shift = Lsb; - - /* Get tuner register byte according to register adddress. */ - MXL_RegRead(fe, RegAddr, &RegByte); - - /* Reserve register byte unmask bit with mask and inlay writing value into it. */ - RegByte &= ~Mask; - RegByte |= (WritingValue << Shift) & Mask; - - /* Update tuner register byte table. */ - MXL_RegWrite(fe, RegAddr, RegByte); - - /* Write tuner register byte with writing byte. */ - return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); -} - - -// The following context is source code provided by MaxLinear. -// MaxLinear source code - MXL5005_Initialize.cpp -// DONE +/* ---------------------------------------------------------------- + * Begin: Reference driver code found in the Realtek driver. + * Copyright (c) 2008 MaxLinear + */ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -757,7 +709,6 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) return 0 ; } -// DONE u16 MXL5005_ControlInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1701,7 +1652,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) // MaxLinear source code - MXL5005_c.cpp // MXL5005.cpp : Defines the initialization routines for the DLL. // 2.6.12 -// DONE void InitTunerControls(struct dvb_frontend *fe) { MXL5005_RegisterInit(fe); @@ -1744,7 +1694,6 @@ void InitTunerControls(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL5005_TunerConfig(struct dvb_frontend *fe, u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ @@ -1814,7 +1763,6 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1853,7 +1801,6 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1892,7 +1839,6 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { u16 status = 0; @@ -1930,7 +1876,6 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_BlockInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3687,7 +3632,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) return status ; } -// DONE u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { u16 status = 0; @@ -3754,7 +3698,6 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) // >0 : Value exceed maximum allowed for control number // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { u16 status = 0; @@ -3795,7 +3738,6 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) // 2 : Control name not found // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3902,7 +3844,6 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3942,7 +3883,6 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3979,7 +3919,6 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4051,7 +3990,6 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4157,7 +4095,6 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int // NONE // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4205,7 +4142,6 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) // Computed value // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u32 MXL_Ceiling(u32 value, u32 resolution) { return (value/resolution + (value % resolution > 0 ? 1 : 0)); @@ -4214,7 +4150,6 @@ u32 MXL_Ceiling(u32 value, u32 resolution) // // Retrieve the Initialzation Registers // -// DONE u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4237,7 +4172,6 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c return status; } -// DONE u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4265,7 +4199,6 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou return status; } -// DONE u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4283,7 +4216,6 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i return status; } -// DONE u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4301,7 +4233,6 @@ u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, in return status; } -// DONE u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) /* Load_Start */ @@ -4446,7 +4377,6 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) return status; } -// DONE u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4457,12 +4387,91 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) return status; } - #endif +/* End: Reference driver code found in the Realtek driver that + * is copyright MaxLinear */ + +/* ---------------------------------------------------------------- + * Begin: Everything after here is new code to adapt the + * proprietary Realtek driver into a Linux API tuner. + * Copyright (C) 2008 Steven Toth + */ +static int mxl5005s_reset(struct dvb_frontend *fe) +{ + struct mxl5005s_state *state = fe->tuner_priv; + int ret = 0; + + u8 buf[2] = { 0xff, 0x00 }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 2 }; + + dprintk(2, "%s()\n", __func__); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C reset failed\n"); + ret = -EREMOTEIO; + } + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return ret; +} + +/* Write a single byte to a single reg, latch the value if required by + * following the transaction with the latch byte. + */ +static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) +{ + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 3 }; + + if (latch == 0) + msg.len = 2; + + dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write failed\n"); + return -EREMOTEIO; + } + return 0; +} + +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len) +{ + int ret = 0, i; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + for (i = 0 ; i < len-1; i++) { + ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0); + if (ret < 0) + break; + } + + ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return ret; +} -/* Linux driver related functions */ int mxl5005s_init(struct dvb_frontend *fe) +{ + dprintk(1, "%s()\n", __func__); + return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ); +} + +int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4470,7 +4479,7 @@ int mxl5005s_init(struct dvb_frontend *fe) u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - dprintk(1, "%s()\n", __func__); + dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth); mxl5005s_reset(fe); @@ -4479,19 +4488,19 @@ int mxl5005s_init(struct dvb_frontend *fe) AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); - mxl5005s_AssignTunerMode(fe); // tunre_config + mxl5005s_AssignTunerMode(fe, mod_type, bandwidth); /* Tuner initialization stage 1 */ MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); return 0; } -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe) +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; struct mxl5005s_config *c = state->config; @@ -4503,7 +4512,7 @@ int mxl5005s_AssignTunerMode(struct dvb_frontend *fe) fe, c->mod_mode, c->if_mode, - MXL5005S_BANDWIDTH_6MHZ, + bandwidth, c->if_freq, c->xtal_freq, c->agc_mode, @@ -4513,7 +4522,7 @@ int mxl5005s_AssignTunerMode(struct dvb_frontend *fe) c->div_out, c->cap_select, c->rssi_enable, - MXL_QAM, + mod_type, c->tracking_filter); return 0; @@ -4522,22 +4531,62 @@ int mxl5005s_AssignTunerMode(struct dvb_frontend *fe) static int mxl5005s_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) { - u32 freq; - u32 bw; + struct mxl5005s_state *state = fe->tuner_priv; + u32 req_mode, req_bw = 0; + int ret; - if (fe->ops.info.type == FE_OFDM) - bw = params->u.ofdm.bandwidth; - else - bw = MXL5005S_BANDWIDTH_6MHZ; + dprintk(1, "%s()\n", __func__); + + if (fe->ops.info.type == FE_ATSC) { + switch (params->u.vsb.modulation) { + case VSB_8: + req_mode = MXL_ATSC; break; + default: + case QAM_64: + case QAM_256: + case QAM_AUTO: + req_mode = MXL_QAM; break; + } + } + else req_mode = MXL_DVBT; + + /* Change tuner for new modulation type if reqd */ + if (req_mode != state->current_mode) { + switch (req_mode) { + case VSB_8: + case QAM_64: + case QAM_256: + case QAM_AUTO: + req_bw = MXL5005S_BANDWIDTH_6MHZ; + break; + default: + /* Assume DVB-T */ + switch (params->u.ofdm.bandwidth) { + case BANDWIDTH_6_MHZ: + req_bw = MXL5005S_BANDWIDTH_6MHZ; + break; + case BANDWIDTH_7_MHZ: + req_bw = MXL5005S_BANDWIDTH_7MHZ; + break; + case BANDWIDTH_AUTO: + case BANDWIDTH_8_MHZ: + req_bw = MXL5005S_BANDWIDTH_8MHZ; + break; + } + } - freq = params->frequency; /* Hz */ - dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); + state->current_mode = req_mode; + ret = mxl5005s_reconfigure(fe, req_mode, req_bw); - mxl5005s_SetRfFreqHz(fe, freq); + } else + ret = 0; - msleep(350); + if (ret == 0) { + dprintk(1, "%s() freq=%d\n", __func__, params->frequency); + ret = mxl5005s_SetRfFreqHz(fe, params->frequency); + } - return 0; + return ret; } static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) @@ -4560,16 +4609,6 @@ static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) return 0; } -static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status) -{ - dprintk(1, "%s()\n", __func__); - - *status = 0; - // *status = TUNER_STATUS_LOCKED; - - return 0; -} - static int mxl5005s_release(struct dvb_frontend *fe) { dprintk(1, "%s()\n", __func__); @@ -4592,7 +4631,6 @@ static const struct dvb_tuner_ops mxl5005s_tuner_ops = { .set_params = mxl5005s_set_params, .get_frequency = mxl5005s_get_frequency, .get_bandwidth = mxl5005s_get_bandwidth, - .get_status = mxl5005s_get_status }; struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, @@ -4609,6 +4647,7 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, state->frontend = fe; state->config = config; state->i2c = i2c; + state->current_mode = MXL_QAM; printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); @@ -4620,8 +4659,5 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, EXPORT_SYMBOL(mxl5005s_attach); MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); -MODULE_AUTHOR("Jan Hoogenraad"); -MODULE_AUTHOR("Barnaby Shearer"); -MODULE_AUTHOR("Andy Hasper"); MODULE_AUTHOR("Steven Toth"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h index 2777ecc20d19..7658401f3cdd 100644 --- a/drivers/media/common/tuners/mxl5005s.h +++ b/drivers/media/common/tuners/mxl5005s.h @@ -1,27 +1,24 @@ /* - * For the Realtek RTL chip RTL2831U - * Realtek Release Date: 2008-03-14, ver 080314 - * Realtek version RTL2831 Linux driver version 080314 - * ver 080314 - * - * for linux kernel version 2.6.21.4 - 2.6.22-14 - * support MXL5005s and MT2060 tuners (support tuner auto-detecting) - * support two IR types -- RC5 and NEC - * - * Known boards with Realtek RTL chip RTL2821U - * Freecom USB stick 14aa:0160 (version 4) - * Conceptronic CTVDIGRCU - * - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - * This code is placed under the terms of the GNU General Public License - * - * Released by Realtek under GPLv2. - * Thanks to Realtek for a lot of support we received ! - * - * Revision: 080314 - original version - */ + MaxLinear MXL5005S VSB/QAM/DVBT tuner driver + Copyright (C) 2008 MaxLinear + Copyright (C) 2008 Steven Toth + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + +*/ #ifndef __MXL5005S_H #define __MXL5005S_H @@ -112,14 +109,15 @@ struct mxl5005s_config u8 AgcMasterByte; }; -#if defined(CONFIG_DVB_TUNER_MXL5005S) || (defined(CONFIG_DVB_TUNER_MXL5005S_MODULE) && defined(MODULE)) +#if defined(CONFIG_DVB_TUNER_MXL5005S) || \ + (defined(CONFIG_DVB_TUNER_MXL5005S_MODULE) && defined(MODULE)) extern struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, - struct mxl5005s_config *config); + struct mxl5005s_config *config) #else static inline struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, - struct mxl5005s_config *config); + struct mxl5005s_config *config) { printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); return NULL; -- cgit v1.2.3 From 5c1b20514f592af19974166f130b85346c1fbf3a Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 07:04:09 -0300 Subject: V4L/DVB (7870): mxl5005s: Basic digital support. ATSC and QAM should be working but basic testing is required. Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 616 ++++++++++++++++++--------------- drivers/media/common/tuners/mxl5005s.h | 145 +++----- 2 files changed, 389 insertions(+), 372 deletions(-) diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index f7ed9a72db4a..64aa864c5dbf 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -1,69 +1,40 @@ /* - MaxLinear MXL5005S VSB/QAM/DVBT tuner driver - - Copyright (C) 2008 MaxLinear - Copyright (C) 2006 Steven Toth - Functions: - mxl5005s_reset() - mxl5005s_writereg() - mxl5005s_writeregs() - mxl5005s_init() - mxl5005s_reconfigure() - mxl5005s_AssignTunerMode() - mxl5005s_set_params() - mxl5005s_get_frequency() - mxl5005s_get_bandwidth() - mxl5005s_release() - mxl5005s_attach() - - Copyright (c) 2008 Realtek - Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - Functions: - mxl5005s_SetRfFreqHz() - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - -*/ - -/* - History of this driver (Steven Toth): - I was given a public release of a linux driver that included - support for the MaxLinear MXL5005S silicon tuner. Analysis of - the tuner driver showed clearly three things. - - 1. The tuner driver didn't support the LinuxTV tuner API - so the code Realtek added had to be removed. - - 2. A significant amount of the driver is reference driver code - from MaxLinear, I felt it was important to identify and - preserve this. - - 3. New code has to be added to interface correctly with the - LinuxTV API, as a regular kernel module. - - Other than the reference driver enum's, I've clearly marked - sections of the code and retained the copyright of the - respective owners. -*/ + * For the Realtek RTL chip RTL2831U + * Realtek Release Date: 2008-03-14, ver 080314 + * Realtek version RTL2831 Linux driver version 080314 + * ver 080314 + * + * for linux kernel version 2.6.21.4 - 2.6.22-14 + * support MXL5005s and MT2060 tuners (support tuner auto-detecting) + * support two IR types -- RC5 and NEC + * + * Known boards with Realtek RTL chip RTL2821U + * Freecom USB stick 14aa:0160 (version 4) + * Conceptronic CTVDIGRCU + * + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ +#include +#include +#include +#include +#include +#include +#include "dvb_frontend.h" #include "mxl5005s.h" -static int debug = 2; +static int debug; #define dprintk(level, arg...) do { \ - if (level <= debug) \ + if (debug >= level) \ printk(arg); \ } while (0) @@ -79,6 +50,13 @@ static int debug = 2; #define MXLCTRL_NUM 189 #define MASTER_CONTROL_ADDR 9 +/* Enumeration of AGC Mode */ +typedef enum +{ + MXL_DUAL_AGC = 0, + MXL_SINGLE_AGC +} AGC_Mode; + /* Enumeration of Master Control Register State */ typedef enum { @@ -88,6 +66,51 @@ typedef enum MC_SEQ_OFF } Master_Control_State; +/* Enumeration of MXL5005 Tuner Mode */ +typedef enum +{ + MXL_ANALOG_MODE = 0, + MXL_DIGITAL_MODE +} Tuner_Mode; + +/* Enumeration of MXL5005 Tuner IF Mode */ +typedef enum +{ + MXL_ZERO_IF = 0, + MXL_LOW_IF +} Tuner_IF_Mode; + +/* Enumeration of MXL5005 Tuner Clock Out Mode */ +typedef enum +{ + MXL_CLOCK_OUT_DISABLE = 0, + MXL_CLOCK_OUT_ENABLE +} Tuner_Clock_Out; + +/* Enumeration of MXL5005 Tuner Div Out Mode */ +typedef enum +{ + MXL_DIV_OUT_1 = 0, + MXL_DIV_OUT_4 + +} Tuner_Div_Out; + +/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ +typedef enum +{ + MXL_CAP_SEL_DISABLE = 0, + MXL_CAP_SEL_ENABLE + +} Tuner_Cap_Select; + +/* Enumeration of MXL5005 Tuner RSSI Mode */ +typedef enum +{ + MXL_RSSI_DISABLE = 0, + MXL_RSSI_ENABLE + +} Tuner_RSSI; + /* Enumeration of MXL5005 Tuner Modulation Type */ typedef enum { @@ -99,6 +122,22 @@ typedef enum MXL_ANALOG_OTA } Tuner_Modu_Type; +/* Enumeration of MXL5005 Tuner Tracking Filter Type */ +typedef enum +{ + MXL_TF_DEFAULT = 0, + MXL_TF_OFF, + MXL_TF_C, + MXL_TF_C_H, + MXL_TF_D, + MXL_TF_D_L, + MXL_TF_E, + MXL_TF_F, + MXL_TF_E_2, + MXL_TF_E_NA, + MXL_TF_G +} Tuner_TF_Type; + /* MXL5005 Tuner Register Struct */ typedef struct _TunerReg_struct { @@ -229,6 +268,33 @@ enum }; #define MXL5005S_BANDWIDTH_MODE_NUM 3 +/* Top modes */ +enum +{ + MXL5005S_TOP_5P5 = 55, + MXL5005S_TOP_7P2 = 72, + MXL5005S_TOP_9P2 = 92, + MXL5005S_TOP_11P0 = 110, + MXL5005S_TOP_12P9 = 129, + MXL5005S_TOP_14P7 = 147, + MXL5005S_TOP_16P8 = 168, + MXL5005S_TOP_19P4 = 194, + MXL5005S_TOP_21P2 = 212, + MXL5005S_TOP_23P2 = 232, + MXL5005S_TOP_25P2 = 252, + MXL5005S_TOP_27P1 = 271, + MXL5005S_TOP_29P2 = 292, + MXL5005S_TOP_31P7 = 317, + MXL5005S_TOP_34P9 = 349, +}; + +/* IF output load */ +enum +{ + MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, + MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, +}; + /* MXL5005 Tuner Control Struct */ typedef struct _TunerControl_struct { u16 Ctrl_Num; /* Control Number */ @@ -283,15 +349,13 @@ struct mxl5005s_state TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ /* Linux driver framework specific */ - struct mxl5005s_config *config; + const struct mxl5005s_config *config; + struct dvb_frontend *frontend; struct i2c_adapter *i2c; - - /* Cache values */ - u32 current_mode; - }; +// funcs u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); u16 MXL_GetMasterControl(u8 *MasterReg, int state); @@ -308,26 +372,14 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); +int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); u16 MXL_IFSynthInit(struct dvb_frontend *fe); -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); -int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); - -/* ---------------------------------------------------------------- - * Begin: Custom code salvaged from the Realtek driver. - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - * This code is placed under the terms of the GNU General Public License - * - * Released by Realtek under GPLv2. - * Thanks to Realtek for a lot of support we received ! - * - * Revision: 080314 - original version - */ +static int mxl5005s_init2(struct dvb_frontend *fe); int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { struct mxl5005s_state *state = fe->tuner_priv; + u8 AgcMasterByte = state->config->AgcMasterByte; unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; @@ -344,7 +396,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); // Tuner RF frequency setting stage 1 MXL_TuneRF(fe, RfFreqHz); @@ -358,13 +410,13 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; + ByteTable[TableLen] = MasterControlByte | AgcMasterByte; TableLen += 1; - mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); // Wait 30 ms. - msleep(150); + msleep(30); // Tuner RF frequency setting stage 2 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; @@ -373,21 +425,101 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; + ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; TableLen += 1; - mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); - msleep(100); + return 0; +} +/* Write a single byte to a single reg */ +static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val) +{ + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[2] = { reg, val }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 2 }; + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write failed\n"); + return -EREMOTEIO; + } return 0; } -/* End: Custom code taken from the Realtek driver */ -/* ---------------------------------------------------------------- - * Begin: Reference driver code found in the Realtek driver. - * Copyright (c) 2008 MaxLinear - */ +/* Write a word to a single reg */ +static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) +{ + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[3] = { reg, val >> 8 , val & 0xff }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 3 }; + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write16 failed\n"); + return -EREMOTEIO; + } + return 0; +} + +int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) +{ + int i, ret; + u8 end_two_bytes_buf[]={ 0 , 0 }; + + for( i = 0 ; i < TableLen - 1 ; i++) + { + ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]); + if (!ret) + return ret; + } + + end_two_bytes_buf[0] = pByteTable[i]; + end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; + + ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]); + + return ret; +} + +int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, + unsigned char RegAddr, + unsigned char Msb, + unsigned char Lsb, + const unsigned char WritingValue + ) +{ + int i; + + unsigned char Mask; + unsigned char Shift; + unsigned char RegByte; + + /* Generate mask and shift according to MSB and LSB. */ + Mask = 0; + for(i = Lsb; i < (unsigned char)(Msb + 1); i++) + Mask |= 0x1 << i; + + Shift = Lsb; + + /* Get tuner register byte according to register adddress. */ + MXL_RegRead(fe, RegAddr, &RegByte); + + /* Reserve register byte unmask bit with mask and inlay writing value into it. */ + RegByte &= ~Mask; + RegByte |= (WritingValue << Shift) & Mask; + + /* Update tuner register byte table. */ + MXL_RegWrite(fe, RegAddr, RegByte); + + /* Write tuner register byte with writing byte. */ + return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); +} + +// The following context is source code provided by MaxLinear. +// MaxLinear source code - MXL5005_Initialize.cpp +// DONE u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -709,6 +841,7 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) return 0 ; } +// DONE u16 MXL5005_ControlInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1652,6 +1785,7 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) // MaxLinear source code - MXL5005_c.cpp // MXL5005.cpp : Defines the initialization routines for the DLL. // 2.6.12 +// DONE void InitTunerControls(struct dvb_frontend *fe) { MXL5005_RegisterInit(fe); @@ -1694,6 +1828,7 @@ void InitTunerControls(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL5005_TunerConfig(struct dvb_frontend *fe, u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ @@ -1763,6 +1898,7 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// +// DONE void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1801,6 +1937,7 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// +// DONE void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1839,6 +1976,7 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { u16 status = 0; @@ -1876,6 +2014,7 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_BlockInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1903,7 +2042,6 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); break; case 6000000: - printk("%s() doing 6MHz digital\n", __func__); status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); break; } @@ -1934,6 +2072,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) else /* Single AGC Mode Dig Ana */ status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); + if (state->TOP == 55) /* TOP == 5.5 */ status += MXL_ControlWrite(fe, AGC_IF, 0x0); @@ -2163,8 +2302,6 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_IQSWAP, 0); else /* High IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 1); - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2); - } if (state->Mod_Type == MXL_ANALOG_CABLE) { /* Analog Cable Mode */ @@ -2201,7 +2338,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } /* RSSI disable */ - if(state->EN_RSSI == 0) { + if(state->EN_RSSI==0) { status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); @@ -2410,7 +2547,6 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe) Fref = 324000000UL ; } if (state->IF_LO == 5380000UL) { - printk("%s() doing 5.38\n", __func__); status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 322800000UL ; @@ -3093,7 +3229,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only { - printk("%s() CH filter\n", __func__); status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) @@ -3632,6 +3767,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) return status ; } +// DONE u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { u16 status = 0; @@ -3698,6 +3834,7 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) // >0 : Value exceed maximum allowed for control number // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { u16 status = 0; @@ -3738,6 +3875,7 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) // 2 : Control name not found // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3844,6 +3982,7 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3883,6 +4022,7 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3919,6 +4059,7 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3990,6 +4131,7 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4095,6 +4237,7 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int // NONE // // // /////////////////////////////////////////////////////////////////////////////// +// DONE void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4142,6 +4285,7 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) // Computed value // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u32 MXL_Ceiling(u32 value, u32 resolution) { return (value/resolution + (value % resolution > 0 ? 1 : 0)); @@ -4150,6 +4294,7 @@ u32 MXL_Ceiling(u32 value, u32 resolution) // // Retrieve the Initialzation Registers // +// DONE u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4172,6 +4317,7 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c return status; } +// DONE u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4199,6 +4345,7 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou return status; } +// DONE u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4216,6 +4363,7 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i return status; } +// DONE u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4233,6 +4381,7 @@ u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, in return status; } +// DONE u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) /* Load_Start */ @@ -4377,6 +4526,7 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) return status; } +// DONE u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4387,224 +4537,141 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) return status; } + #endif -/* End: Reference driver code found in the Realtek driver that - * is copyright MaxLinear */ -/* ---------------------------------------------------------------- - * Begin: Everything after here is new code to adapt the - * proprietary Realtek driver into a Linux API tuner. - * Copyright (C) 2008 Steven Toth - */ -static int mxl5005s_reset(struct dvb_frontend *fe) +/* Linux driver related functions */ + + +int mxl5005s_init(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->tuner_priv; - int ret = 0; + int MxlModMode; + int MxlIfMode; + unsigned long MxlBandwitdh; + unsigned long MxlIfFreqHz; + unsigned long MxlCrystalFreqHz; + int MxlAgcMode; + unsigned short MxlTop; + unsigned short MxlIfOutputLoad; + int MxlClockOut; + int MxlDivOut; + int MxlCapSel; + int MxlRssiOnOff; + unsigned char MxlStandard; + unsigned char MxlTfType; - u8 buf[2] = { 0xff, 0x00 }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 2 }; + /* Set MxL5005S parameters. */ + MxlModMode = MXL_DIGITAL_MODE; + MxlIfMode = MXL_ZERO_IF; +// steve + //MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; + //MxlIfFreqHz = IF_FREQ_4570000HZ; + MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config + MxlIfFreqHz = IF_FREQ_5380000HZ; // config + MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config + MxlAgcMode = MXL_SINGLE_AGC; + MxlTop = MXL5005S_TOP_25P2; + MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; + MxlClockOut = MXL_CLOCK_OUT_DISABLE; + MxlDivOut = MXL_DIV_OUT_4; + MxlCapSel = MXL_CAP_SEL_ENABLE; + MxlRssiOnOff = MXL_RSSI_ENABLE; // config + MxlTfType = MXL_TF_C_H; // config + + MxlStandard = MXL_ATSC; // config + + // TODO: this is bad, it trashes other configs + // Set MxL5005S extra module. + //pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; - dprintk(2, "%s()\n", __func__); + MXL5005_TunerConfig( + fe, + (unsigned char)MxlModMode, + (unsigned char)MxlIfMode, + MxlBandwitdh, + MxlIfFreqHz, + MxlCrystalFreqHz, + (unsigned char)MxlAgcMode, + MxlTop, + MxlIfOutputLoad, + (unsigned char)MxlClockOut, + (unsigned char)MxlDivOut, + (unsigned char)MxlCapSel, + (unsigned char)MxlRssiOnOff, + MxlStandard, MxlTfType); + + return mxl5005s_init2(fe); +} - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); +static int mxl5005s_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + u32 freq; + u32 bw; - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C reset failed\n"); - ret = -EREMOTEIO; - } + if (fe->ops.info.type == FE_OFDM) + bw = params->u.ofdm.bandwidth; + else + bw = MXL5005S_BANDWIDTH_6MHZ; - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + freq = params->frequency; /* Hz */ + dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); - return ret; + return mxl5005s_SetRfFreqHz(fe, freq); } -/* Write a single byte to a single reg, latch the value if required by - * following the transaction with the latch byte. - */ -static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) +static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) { struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 3 }; - - if (latch == 0) - msg.len = 2; + dprintk(1, "%s()\n", __func__); - dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); + *frequency = state->RF_IN; - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write failed\n"); - return -EREMOTEIO; - } return 0; } -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len) +static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) { - int ret = 0, i; - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - - for (i = 0 ; i < len-1; i++) { - ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0); - if (ret < 0) - break; - } - - ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1); + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + *bandwidth = state->Chan_Bandwidth; - return ret; + return 0; } - -int mxl5005s_init(struct dvb_frontend *fe) +static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status) { dprintk(1, "%s()\n", __func__); - return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ); + + *status = 0; + // *status = TUNER_STATUS_LOCKED; + + return 0; } -int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) +static int mxl5005s_init2(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; - u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth); + dprintk(1, "%s()\n", __func__); - mxl5005s_reset(fe); + /* Initialize MxL5005S tuner according to MxL5005S tuner example code. */ /* Tuner initialization stage 0 */ MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); - - mxl5005s_AssignTunerMode(fe, mod_type, bandwidth); + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); /* Tuner initialization stage 1 */ MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); - mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); - - return 0; -} - -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) -{ - struct mxl5005s_state *state = fe->tuner_priv; - struct mxl5005s_config *c = state->config; - - InitTunerControls(fe); - - /* Set MxL5005S parameters. */ - MXL5005_TunerConfig( - fe, - c->mod_mode, - c->if_mode, - bandwidth, - c->if_freq, - c->xtal_freq, - c->agc_mode, - c->top, - c->output_load, - c->clock_out, - c->div_out, - c->cap_select, - c->rssi_enable, - mod_type, - c->tracking_filter); - - return 0; -} - -static int mxl5005s_set_params(struct dvb_frontend *fe, - struct dvb_frontend_parameters *params) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u32 req_mode, req_bw = 0; - int ret; - - dprintk(1, "%s()\n", __func__); - - if (fe->ops.info.type == FE_ATSC) { - switch (params->u.vsb.modulation) { - case VSB_8: - req_mode = MXL_ATSC; break; - default: - case QAM_64: - case QAM_256: - case QAM_AUTO: - req_mode = MXL_QAM; break; - } - } - else req_mode = MXL_DVBT; - - /* Change tuner for new modulation type if reqd */ - if (req_mode != state->current_mode) { - switch (req_mode) { - case VSB_8: - case QAM_64: - case QAM_256: - case QAM_AUTO: - req_bw = MXL5005S_BANDWIDTH_6MHZ; - break; - default: - /* Assume DVB-T */ - switch (params->u.ofdm.bandwidth) { - case BANDWIDTH_6_MHZ: - req_bw = MXL5005S_BANDWIDTH_6MHZ; - break; - case BANDWIDTH_7_MHZ: - req_bw = MXL5005S_BANDWIDTH_7MHZ; - break; - case BANDWIDTH_AUTO: - case BANDWIDTH_8_MHZ: - req_bw = MXL5005S_BANDWIDTH_8MHZ; - break; - } - } - - state->current_mode = req_mode; - ret = mxl5005s_reconfigure(fe, req_mode, req_bw); - - } else - ret = 0; - - if (ret == 0) { - dprintk(1, "%s() freq=%d\n", __func__, params->frequency); - ret = mxl5005s_SetRfFreqHz(fe, params->frequency); - } - - return ret; -} - -static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) -{ - struct mxl5005s_state *state = fe->tuner_priv; - dprintk(1, "%s()\n", __func__); - - *frequency = state->RF_IN; - - return 0; -} - -static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) -{ - struct mxl5005s_state *state = fe->tuner_priv; - dprintk(1, "%s()\n", __func__); - - *bandwidth = state->Chan_Bandwidth; + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); return 0; } @@ -4631,6 +4698,7 @@ static const struct dvb_tuner_ops mxl5005s_tuner_ops = { .set_params = mxl5005s_set_params, .get_frequency = mxl5005s_get_frequency, .get_bandwidth = mxl5005s_get_bandwidth, + .get_status = mxl5005s_get_status }; struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, @@ -4647,7 +4715,6 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, state->frontend = fe; state->config = config; state->i2c = i2c; - state->current_mode = MXL_QAM; printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); @@ -4659,5 +4726,8 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, EXPORT_SYMBOL(mxl5005s_attach); MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); +MODULE_AUTHOR("Jan Hoogenraad"); +MODULE_AUTHOR("Barnaby Shearer"); +MODULE_AUTHOR("Andy Hasper"); MODULE_AUTHOR("Steven Toth"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h index 7658401f3cdd..7d0727d44536 100644 --- a/drivers/media/common/tuners/mxl5005s.h +++ b/drivers/media/common/tuners/mxl5005s.h @@ -1,119 +1,66 @@ /* - MaxLinear MXL5005S VSB/QAM/DVBT tuner driver + * For the Realtek RTL chip RTL2831U + * Realtek Release Date: 2008-03-14, ver 080314 + * Realtek version RTL2831 Linux driver version 080314 + * ver 080314 + * + * for linux kernel version 2.6.21.4 - 2.6.22-14 + * support MXL5005s and MT2060 tuners (support tuner auto-detecting) + * support two IR types -- RC5 and NEC + * + * Known boards with Realtek RTL chip RTL2821U + * Freecom USB stick 14aa:0160 (version 4) + * Conceptronic CTVDIGRCU + * + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ - Copyright (C) 2008 MaxLinear - Copyright (C) 2008 Steven Toth - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. +#ifndef __MXL5005S_H +#define __MXL5005S_H - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +#include -*/ +/* IF frequency */ +enum IF_FREQ_HZ +{ + IF_FREQ_4570000HZ = 4570000, ///< IF frequency = 4.57 MHz + IF_FREQ_4571429HZ = 4571429, ///< IF frequency = 4.571 MHz + IF_FREQ_5380000HZ = 5380000, ///< IF frequency = 5.38 MHz + IF_FREQ_36000000HZ = 36000000, ///< IF frequency = 36.000 MHz + IF_FREQ_36125000HZ = 36125000, ///< IF frequency = 36.125 MHz + IF_FREQ_36166667HZ = 36166667, ///< IF frequency = 36.167 MHz + IF_FREQ_44000000HZ = 44000000, ///< IF frequency = 44.000 MHz +}; -#ifndef __MXL5005S_H -#define __MXL5005S_H +/* Crystal frequency */ +enum CRYSTAL_FREQ_HZ +{ + CRYSTAL_FREQ_4000000HZ = 4000000, ///< Crystal frequency = 4.0 MHz + CRYSTAL_FREQ_16000000HZ = 16000000, ///< Crystal frequency = 16.0 MHz + CRYSTAL_FREQ_25000000HZ = 25000000, ///< Crystal frequency = 25.0 MHz + CRYSTAL_FREQ_28800000HZ = 28800000, ///< Crystal frequency = 28.8 MHz +}; struct mxl5005s_config { - /* 7 bit i2c address */ u8 i2c_address; -#define IF_FREQ_4570000HZ 4570000 -#define IF_FREQ_4571429HZ 4571429 -#define IF_FREQ_5380000HZ 5380000 -#define IF_FREQ_36000000HZ 36000000 -#define IF_FREQ_36125000HZ 36125000 -#define IF_FREQ_36166667HZ 36166667 -#define IF_FREQ_44000000HZ 44000000 - u32 if_freq; - -#define CRYSTAL_FREQ_4000000HZ 4000000 -#define CRYSTAL_FREQ_16000000HZ 16000000 -#define CRYSTAL_FREQ_25000000HZ 25000000 -#define CRYSTAL_FREQ_28800000HZ 28800000 - u32 xtal_freq; - -#define MXL_DUAL_AGC 0 -#define MXL_SINGLE_AGC 1 - u8 agc_mode; - -#define MXL_TF_DEFAULT 0 -#define MXL_TF_OFF 1 -#define MXL_TF_C 2 -#define MXL_TF_C_H 3 -#define MXL_TF_D 4 -#define MXL_TF_D_L 5 -#define MXL_TF_E 6 -#define MXL_TF_F 7 -#define MXL_TF_E_2 8 -#define MXL_TF_E_NA 9 -#define MXL_TF_G 10 - u8 tracking_filter; - -#define MXL_RSSI_DISABLE 0 -#define MXL_RSSI_ENABLE 1 - u8 rssi_enable; - -#define MXL_CAP_SEL_DISABLE 0 -#define MXL_CAP_SEL_ENABLE 1 - u8 cap_select; - -#define MXL_DIV_OUT_1 0 -#define MXL_DIV_OUT_4 1 - u8 div_out; - -#define MXL_CLOCK_OUT_DISABLE 0 -#define MXL_CLOCK_OUT_ENABLE 1 - u8 clock_out; - -#define MXL5005S_IF_OUTPUT_LOAD_200_OHM 200 -#define MXL5005S_IF_OUTPUT_LOAD_300_OHM 300 - u32 output_load; - -#define MXL5005S_TOP_5P5 55 -#define MXL5005S_TOP_7P2 72 -#define MXL5005S_TOP_9P2 92 -#define MXL5005S_TOP_11P0 110 -#define MXL5005S_TOP_12P9 129 -#define MXL5005S_TOP_14P7 147 -#define MXL5005S_TOP_16P8 168 -#define MXL5005S_TOP_19P4 194 -#define MXL5005S_TOP_21P2 212 -#define MXL5005S_TOP_23P2 232 -#define MXL5005S_TOP_25P2 252 -#define MXL5005S_TOP_27P1 271 -#define MXL5005S_TOP_29P2 292 -#define MXL5005S_TOP_31P7 317 -#define MXL5005S_TOP_34P9 349 - u32 top; - -#define MXL_ANALOG_MODE 0 -#define MXL_DIGITAL_MODE 1 - u8 mod_mode; - -#define MXL_ZERO_IF 0 -#define MXL_LOW_IF 1 - u8 if_mode; - /* Stuff I don't know what to do with */ u8 AgcMasterByte; }; -#if defined(CONFIG_DVB_TUNER_MXL5005S) || \ - (defined(CONFIG_DVB_TUNER_MXL5005S_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_MXL5005S) || (defined(CONFIG_MEDIA_TUNER_MXL5005S_MODULE) && defined(MODULE)) extern struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, - struct mxl5005s_config *config) + struct mxl5005s_config *config); #else static inline struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, -- cgit v1.2.3 From 48937295a63b4e81db907605afcbd81e0464b00f Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 07:15:38 -0300 Subject: V4L/DVB(7871): mxl5005s: Re-org code and update copyrights Re-org code and update copyrights Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 608 +++++++++++++++------------------ drivers/media/common/tuners/mxl5005s.h | 143 +++++--- 2 files changed, 371 insertions(+), 380 deletions(-) diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 64aa864c5dbf..45ac6a9e71a3 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -1,27 +1,62 @@ /* - * For the Realtek RTL chip RTL2831U - * Realtek Release Date: 2008-03-14, ver 080314 - * Realtek version RTL2831 Linux driver version 080314 - * ver 080314 - * - * for linux kernel version 2.6.21.4 - 2.6.22-14 - * support MXL5005s and MT2060 tuners (support tuner auto-detecting) - * support two IR types -- RC5 and NEC - * - * Known boards with Realtek RTL chip RTL2821U - * Freecom USB stick 14aa:0160 (version 4) - * Conceptronic CTVDIGRCU - * - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - * This code is placed under the terms of the GNU General Public License - * - * Released by Realtek under GPLv2. - * Thanks to Realtek for a lot of support we received ! - * - * Revision: 080314 - original version - */ + MaxLinear MXL5005S VSB/QAM/DVBT tuner driver + + Copyright (C) 2008 MaxLinear + Copyright (C) 2006 Steven Toth + Functions: + mxl5005s_reset() + mxl5005s_writereg() + mxl5005s_writeregs() + mxl5005s_init() + mxl5005s_reconfigure() + mxl5005s_AssignTunerMode() + mxl5005s_set_params() + mxl5005s_get_frequency() + mxl5005s_get_bandwidth() + mxl5005s_release() + mxl5005s_attach() + + Copyright (c) 2008 Realtek + Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + Functions: + mxl5005s_SetRfFreqHz() + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + +*/ + +/* + History of this driver (Steven Toth): + I was given a public release of a linux driver that included + support for the MaxLinear MXL5005S silicon tuner. Analysis of + the tuner driver showed clearly three things. + 1. The tuner driver didn't support the LinuxTV tuner API + so the code Realtek added had to be removed. + + 2. A significant amount of the driver is reference driver code + from MaxLinear, I felt it was important to identify and + preserve this. + + 3. New code has to be added to interface correctly with the + LinuxTV API, as a regular kernel module. + + Other than the reference driver enum's, I've clearly marked + sections of the code and retained the copyright of the + respective owners. +*/ #include #include #include @@ -31,10 +66,10 @@ #include "dvb_frontend.h" #include "mxl5005s.h" -static int debug; +static int debug = 2; #define dprintk(level, arg...) do { \ - if (debug >= level) \ + if (level <= debug) \ printk(arg); \ } while (0) @@ -50,13 +85,6 @@ static int debug; #define MXLCTRL_NUM 189 #define MASTER_CONTROL_ADDR 9 -/* Enumeration of AGC Mode */ -typedef enum -{ - MXL_DUAL_AGC = 0, - MXL_SINGLE_AGC -} AGC_Mode; - /* Enumeration of Master Control Register State */ typedef enum { @@ -66,51 +94,6 @@ typedef enum MC_SEQ_OFF } Master_Control_State; -/* Enumeration of MXL5005 Tuner Mode */ -typedef enum -{ - MXL_ANALOG_MODE = 0, - MXL_DIGITAL_MODE -} Tuner_Mode; - -/* Enumeration of MXL5005 Tuner IF Mode */ -typedef enum -{ - MXL_ZERO_IF = 0, - MXL_LOW_IF -} Tuner_IF_Mode; - -/* Enumeration of MXL5005 Tuner Clock Out Mode */ -typedef enum -{ - MXL_CLOCK_OUT_DISABLE = 0, - MXL_CLOCK_OUT_ENABLE -} Tuner_Clock_Out; - -/* Enumeration of MXL5005 Tuner Div Out Mode */ -typedef enum -{ - MXL_DIV_OUT_1 = 0, - MXL_DIV_OUT_4 - -} Tuner_Div_Out; - -/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ -typedef enum -{ - MXL_CAP_SEL_DISABLE = 0, - MXL_CAP_SEL_ENABLE - -} Tuner_Cap_Select; - -/* Enumeration of MXL5005 Tuner RSSI Mode */ -typedef enum -{ - MXL_RSSI_DISABLE = 0, - MXL_RSSI_ENABLE - -} Tuner_RSSI; - /* Enumeration of MXL5005 Tuner Modulation Type */ typedef enum { @@ -122,22 +105,6 @@ typedef enum MXL_ANALOG_OTA } Tuner_Modu_Type; -/* Enumeration of MXL5005 Tuner Tracking Filter Type */ -typedef enum -{ - MXL_TF_DEFAULT = 0, - MXL_TF_OFF, - MXL_TF_C, - MXL_TF_C_H, - MXL_TF_D, - MXL_TF_D_L, - MXL_TF_E, - MXL_TF_F, - MXL_TF_E_2, - MXL_TF_E_NA, - MXL_TF_G -} Tuner_TF_Type; - /* MXL5005 Tuner Register Struct */ typedef struct _TunerReg_struct { @@ -268,33 +235,6 @@ enum }; #define MXL5005S_BANDWIDTH_MODE_NUM 3 -/* Top modes */ -enum -{ - MXL5005S_TOP_5P5 = 55, - MXL5005S_TOP_7P2 = 72, - MXL5005S_TOP_9P2 = 92, - MXL5005S_TOP_11P0 = 110, - MXL5005S_TOP_12P9 = 129, - MXL5005S_TOP_14P7 = 147, - MXL5005S_TOP_16P8 = 168, - MXL5005S_TOP_19P4 = 194, - MXL5005S_TOP_21P2 = 212, - MXL5005S_TOP_23P2 = 232, - MXL5005S_TOP_25P2 = 252, - MXL5005S_TOP_27P1 = 271, - MXL5005S_TOP_29P2 = 292, - MXL5005S_TOP_31P7 = 317, - MXL5005S_TOP_34P9 = 349, -}; - -/* IF output load */ -enum -{ - MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, - MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, -}; - /* MXL5005 Tuner Control Struct */ typedef struct _TunerControl_struct { u16 Ctrl_Num; /* Control Number */ @@ -349,13 +289,15 @@ struct mxl5005s_state TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ /* Linux driver framework specific */ - const struct mxl5005s_config *config; - + struct mxl5005s_config *config; struct dvb_frontend *frontend; struct i2c_adapter *i2c; + + /* Cache values */ + u32 current_mode; + }; -// funcs u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); u16 MXL_GetMasterControl(u8 *MasterReg, int state); @@ -372,14 +314,26 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); u16 MXL_IFSynthInit(struct dvb_frontend *fe); -static int mxl5005s_init2(struct dvb_frontend *fe); +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); +int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); + +/* ---------------------------------------------------------------- + * Begin: Custom code salvaged from the Realtek driver. + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { struct mxl5005s_state *state = fe->tuner_priv; - u8 AgcMasterByte = state->config->AgcMasterByte; unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; @@ -396,7 +350,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); // Tuner RF frequency setting stage 1 MXL_TuneRF(fe, RfFreqHz); @@ -410,13 +364,13 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | AgcMasterByte; + ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; TableLen += 1; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); // Wait 30 ms. - msleep(30); + msleep(150); // Tuner RF frequency setting stage 2 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; @@ -425,101 +379,21 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; + ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; TableLen += 1; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); - return 0; -} + msleep(100); -/* Write a single byte to a single reg */ -static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[2] = { reg, val }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 2 }; - - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write failed\n"); - return -EREMOTEIO; - } return 0; } +/* End: Custom code taken from the Realtek driver */ -/* Write a word to a single reg */ -static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[3] = { reg, val >> 8 , val & 0xff }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 3 }; - - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write16 failed\n"); - return -EREMOTEIO; - } - return 0; -} - -int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) -{ - int i, ret; - u8 end_two_bytes_buf[]={ 0 , 0 }; - - for( i = 0 ; i < TableLen - 1 ; i++) - { - ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]); - if (!ret) - return ret; - } - - end_two_bytes_buf[0] = pByteTable[i]; - end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; - - ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]); - - return ret; -} - -int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, - unsigned char RegAddr, - unsigned char Msb, - unsigned char Lsb, - const unsigned char WritingValue - ) -{ - int i; - - unsigned char Mask; - unsigned char Shift; - unsigned char RegByte; - - /* Generate mask and shift according to MSB and LSB. */ - Mask = 0; - for(i = Lsb; i < (unsigned char)(Msb + 1); i++) - Mask |= 0x1 << i; - - Shift = Lsb; - - /* Get tuner register byte according to register adddress. */ - MXL_RegRead(fe, RegAddr, &RegByte); - - /* Reserve register byte unmask bit with mask and inlay writing value into it. */ - RegByte &= ~Mask; - RegByte |= (WritingValue << Shift) & Mask; - - /* Update tuner register byte table. */ - MXL_RegWrite(fe, RegAddr, RegByte); - - /* Write tuner register byte with writing byte. */ - return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); -} - -// The following context is source code provided by MaxLinear. -// MaxLinear source code - MXL5005_Initialize.cpp -// DONE +/* ---------------------------------------------------------------- + * Begin: Reference driver code found in the Realtek driver. + * Copyright (c) 2008 MaxLinear + */ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -841,7 +715,6 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) return 0 ; } -// DONE u16 MXL5005_ControlInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1785,7 +1658,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) // MaxLinear source code - MXL5005_c.cpp // MXL5005.cpp : Defines the initialization routines for the DLL. // 2.6.12 -// DONE void InitTunerControls(struct dvb_frontend *fe) { MXL5005_RegisterInit(fe); @@ -1828,7 +1700,6 @@ void InitTunerControls(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL5005_TunerConfig(struct dvb_frontend *fe, u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ @@ -1898,7 +1769,6 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1937,7 +1807,6 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1976,7 +1845,6 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { u16 status = 0; @@ -2014,7 +1882,6 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_BlockInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -2042,6 +1909,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); break; case 6000000: + printk("%s() doing 6MHz digital\n", __func__); status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); break; } @@ -2072,7 +1940,6 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) else /* Single AGC Mode Dig Ana */ status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); - if (state->TOP == 55) /* TOP == 5.5 */ status += MXL_ControlWrite(fe, AGC_IF, 0x0); @@ -2302,6 +2169,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_IQSWAP, 0); else /* High IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 1); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2); + } if (state->Mod_Type == MXL_ANALOG_CABLE) { /* Analog Cable Mode */ @@ -2338,7 +2207,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } /* RSSI disable */ - if(state->EN_RSSI==0) { + if(state->EN_RSSI == 0) { status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); @@ -2547,6 +2416,7 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe) Fref = 324000000UL ; } if (state->IF_LO == 5380000UL) { + printk("%s() doing 5.38\n", __func__); status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 322800000UL ; @@ -3229,6 +3099,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only { + printk("%s() CH filter\n", __func__); status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) @@ -3767,7 +3638,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) return status ; } -// DONE u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { u16 status = 0; @@ -3834,7 +3704,6 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) // >0 : Value exceed maximum allowed for control number // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { u16 status = 0; @@ -3875,7 +3744,6 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) // 2 : Control name not found // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3982,7 +3850,6 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4022,7 +3889,6 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4059,7 +3925,6 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4131,7 +3996,6 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4237,7 +4101,6 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int // NONE // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4285,7 +4148,6 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) // Computed value // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u32 MXL_Ceiling(u32 value, u32 resolution) { return (value/resolution + (value % resolution > 0 ? 1 : 0)); @@ -4294,7 +4156,6 @@ u32 MXL_Ceiling(u32 value, u32 resolution) // // Retrieve the Initialzation Registers // -// DONE u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4317,7 +4178,6 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c return status; } -// DONE u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4345,7 +4205,6 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou return status; } -// DONE u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4363,7 +4222,6 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i return status; } -// DONE u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4381,7 +4239,6 @@ u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, in return status; } -// DONE u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) /* Load_Start */ @@ -4526,7 +4383,6 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) return status; } -// DONE u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4537,141 +4393,224 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) return status; } - #endif +/* End: Reference driver code found in the Realtek driver that + * is copyright MaxLinear */ -/* Linux driver related functions */ - - -int mxl5005s_init(struct dvb_frontend *fe) +/* ---------------------------------------------------------------- + * Begin: Everything after here is new code to adapt the + * proprietary Realtek driver into a Linux API tuner. + * Copyright (C) 2008 Steven Toth + */ +static int mxl5005s_reset(struct dvb_frontend *fe) { - int MxlModMode; - int MxlIfMode; - unsigned long MxlBandwitdh; - unsigned long MxlIfFreqHz; - unsigned long MxlCrystalFreqHz; - int MxlAgcMode; - unsigned short MxlTop; - unsigned short MxlIfOutputLoad; - int MxlClockOut; - int MxlDivOut; - int MxlCapSel; - int MxlRssiOnOff; - unsigned char MxlStandard; - unsigned char MxlTfType; + struct mxl5005s_state *state = fe->tuner_priv; + int ret = 0; - /* Set MxL5005S parameters. */ - MxlModMode = MXL_DIGITAL_MODE; - MxlIfMode = MXL_ZERO_IF; -// steve - //MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; - //MxlIfFreqHz = IF_FREQ_4570000HZ; - MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config - MxlIfFreqHz = IF_FREQ_5380000HZ; // config - MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config - MxlAgcMode = MXL_SINGLE_AGC; - MxlTop = MXL5005S_TOP_25P2; - MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; - MxlClockOut = MXL_CLOCK_OUT_DISABLE; - MxlDivOut = MXL_DIV_OUT_4; - MxlCapSel = MXL_CAP_SEL_ENABLE; - MxlRssiOnOff = MXL_RSSI_ENABLE; // config - MxlTfType = MXL_TF_C_H; // config - - MxlStandard = MXL_ATSC; // config - - // TODO: this is bad, it trashes other configs - // Set MxL5005S extra module. - //pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; + u8 buf[2] = { 0xff, 0x00 }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 2 }; - MXL5005_TunerConfig( - fe, - (unsigned char)MxlModMode, - (unsigned char)MxlIfMode, - MxlBandwitdh, - MxlIfFreqHz, - MxlCrystalFreqHz, - (unsigned char)MxlAgcMode, - MxlTop, - MxlIfOutputLoad, - (unsigned char)MxlClockOut, - (unsigned char)MxlDivOut, - (unsigned char)MxlCapSel, - (unsigned char)MxlRssiOnOff, - MxlStandard, MxlTfType); - - return mxl5005s_init2(fe); -} + dprintk(2, "%s()\n", __func__); -static int mxl5005s_set_params(struct dvb_frontend *fe, - struct dvb_frontend_parameters *params) -{ - u32 freq; - u32 bw; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); - if (fe->ops.info.type == FE_OFDM) - bw = params->u.ofdm.bandwidth; - else - bw = MXL5005S_BANDWIDTH_6MHZ; + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C reset failed\n"); + ret = -EREMOTEIO; + } - freq = params->frequency; /* Hz */ - dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); - return mxl5005s_SetRfFreqHz(fe, freq); + return ret; } -static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) +/* Write a single byte to a single reg, latch the value if required by + * following the transaction with the latch byte. + */ +static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) { struct mxl5005s_state *state = fe->tuner_priv; - dprintk(1, "%s()\n", __func__); + u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 3 }; - *frequency = state->RF_IN; + if (latch == 0) + msg.len = 2; + dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write failed\n"); + return -EREMOTEIO; + } return 0; } -static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len) { - struct mxl5005s_state *state = fe->tuner_priv; - dprintk(1, "%s()\n", __func__); + int ret = 0, i; - *bandwidth = state->Chan_Bandwidth; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); - return 0; + for (i = 0 ; i < len-1; i++) { + ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0); + if (ret < 0) + break; + } + + ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return ret; } -static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status) + +int mxl5005s_init(struct dvb_frontend *fe) { dprintk(1, "%s()\n", __func__); - - *status = 0; - // *status = TUNER_STATUS_LOCKED; - - return 0; + return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ); } -static int mxl5005s_init2(struct dvb_frontend *fe) +int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; + u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - dprintk(1, "%s()\n", __func__); + dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth); - /* Initialize MxL5005S tuner according to MxL5005S tuner example code. */ + mxl5005s_reset(fe); /* Tuner initialization stage 0 */ MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); + + mxl5005s_AssignTunerMode(fe, mod_type, bandwidth); /* Tuner initialization stage 1 */ MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); + + return 0; +} + +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) +{ + struct mxl5005s_state *state = fe->tuner_priv; + struct mxl5005s_config *c = state->config; + + InitTunerControls(fe); + + /* Set MxL5005S parameters. */ + MXL5005_TunerConfig( + fe, + c->mod_mode, + c->if_mode, + bandwidth, + c->if_freq, + c->xtal_freq, + c->agc_mode, + c->top, + c->output_load, + c->clock_out, + c->div_out, + c->cap_select, + c->rssi_enable, + mod_type, + c->tracking_filter); + + return 0; +} + +static int mxl5005s_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct mxl5005s_state *state = fe->tuner_priv; + u32 req_mode, req_bw = 0; + int ret; + + dprintk(1, "%s()\n", __func__); + + if (fe->ops.info.type == FE_ATSC) { + switch (params->u.vsb.modulation) { + case VSB_8: + req_mode = MXL_ATSC; break; + default: + case QAM_64: + case QAM_256: + case QAM_AUTO: + req_mode = MXL_QAM; break; + } + } + else req_mode = MXL_DVBT; + + /* Change tuner for new modulation type if reqd */ + if (req_mode != state->current_mode) { + switch (req_mode) { + case VSB_8: + case QAM_64: + case QAM_256: + case QAM_AUTO: + req_bw = MXL5005S_BANDWIDTH_6MHZ; + break; + default: + /* Assume DVB-T */ + switch (params->u.ofdm.bandwidth) { + case BANDWIDTH_6_MHZ: + req_bw = MXL5005S_BANDWIDTH_6MHZ; + break; + case BANDWIDTH_7_MHZ: + req_bw = MXL5005S_BANDWIDTH_7MHZ; + break; + case BANDWIDTH_AUTO: + case BANDWIDTH_8_MHZ: + req_bw = MXL5005S_BANDWIDTH_8MHZ; + break; + } + } + + state->current_mode = req_mode; + ret = mxl5005s_reconfigure(fe, req_mode, req_bw); + + } else + ret = 0; + + if (ret == 0) { + dprintk(1, "%s() freq=%d\n", __func__, params->frequency); + ret = mxl5005s_SetRfFreqHz(fe, params->frequency); + } + + return ret; +} + +static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + + *frequency = state->RF_IN; + + return 0; +} + +static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + + *bandwidth = state->Chan_Bandwidth; return 0; } @@ -4698,7 +4637,6 @@ static const struct dvb_tuner_ops mxl5005s_tuner_ops = { .set_params = mxl5005s_set_params, .get_frequency = mxl5005s_get_frequency, .get_bandwidth = mxl5005s_get_bandwidth, - .get_status = mxl5005s_get_status }; struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, @@ -4715,6 +4653,7 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, state->frontend = fe; state->config = config; state->i2c = i2c; + state->current_mode = MXL_QAM; printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); @@ -4726,8 +4665,5 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, EXPORT_SYMBOL(mxl5005s_attach); MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); -MODULE_AUTHOR("Jan Hoogenraad"); -MODULE_AUTHOR("Barnaby Shearer"); -MODULE_AUTHOR("Andy Hasper"); MODULE_AUTHOR("Steven Toth"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h index 7d0727d44536..687cf146c2a0 100644 --- a/drivers/media/common/tuners/mxl5005s.h +++ b/drivers/media/common/tuners/mxl5005s.h @@ -1,63 +1,118 @@ /* - * For the Realtek RTL chip RTL2831U - * Realtek Release Date: 2008-03-14, ver 080314 - * Realtek version RTL2831 Linux driver version 080314 - * ver 080314 - * - * for linux kernel version 2.6.21.4 - 2.6.22-14 - * support MXL5005s and MT2060 tuners (support tuner auto-detecting) - * support two IR types -- RC5 and NEC - * - * Known boards with Realtek RTL chip RTL2821U - * Freecom USB stick 14aa:0160 (version 4) - * Conceptronic CTVDIGRCU - * - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - * This code is placed under the terms of the GNU General Public License - * - * Released by Realtek under GPLv2. - * Thanks to Realtek for a lot of support we received ! - * - * Revision: 080314 - original version - */ + MaxLinear MXL5005S VSB/QAM/DVBT tuner driver + Copyright (C) 2008 MaxLinear + Copyright (C) 2008 Steven Toth + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + +*/ #ifndef __MXL5005S_H #define __MXL5005S_H #include -/* IF frequency */ -enum IF_FREQ_HZ -{ - IF_FREQ_4570000HZ = 4570000, ///< IF frequency = 4.57 MHz - IF_FREQ_4571429HZ = 4571429, ///< IF frequency = 4.571 MHz - IF_FREQ_5380000HZ = 5380000, ///< IF frequency = 5.38 MHz - IF_FREQ_36000000HZ = 36000000, ///< IF frequency = 36.000 MHz - IF_FREQ_36125000HZ = 36125000, ///< IF frequency = 36.125 MHz - IF_FREQ_36166667HZ = 36166667, ///< IF frequency = 36.167 MHz - IF_FREQ_44000000HZ = 44000000, ///< IF frequency = 44.000 MHz -}; - -/* Crystal frequency */ -enum CRYSTAL_FREQ_HZ -{ - CRYSTAL_FREQ_4000000HZ = 4000000, ///< Crystal frequency = 4.0 MHz - CRYSTAL_FREQ_16000000HZ = 16000000, ///< Crystal frequency = 16.0 MHz - CRYSTAL_FREQ_25000000HZ = 25000000, ///< Crystal frequency = 25.0 MHz - CRYSTAL_FREQ_28800000HZ = 28800000, ///< Crystal frequency = 28.8 MHz -}; - struct mxl5005s_config { + /* 7 bit i2c address */ u8 i2c_address; +#define IF_FREQ_4570000HZ 4570000 +#define IF_FREQ_4571429HZ 4571429 +#define IF_FREQ_5380000HZ 5380000 +#define IF_FREQ_36000000HZ 36000000 +#define IF_FREQ_36125000HZ 36125000 +#define IF_FREQ_36166667HZ 36166667 +#define IF_FREQ_44000000HZ 44000000 + u32 if_freq; + +#define CRYSTAL_FREQ_4000000HZ 4000000 +#define CRYSTAL_FREQ_16000000HZ 16000000 +#define CRYSTAL_FREQ_25000000HZ 25000000 +#define CRYSTAL_FREQ_28800000HZ 28800000 + u32 xtal_freq; + +#define MXL_DUAL_AGC 0 +#define MXL_SINGLE_AGC 1 + u8 agc_mode; + +#define MXL_TF_DEFAULT 0 +#define MXL_TF_OFF 1 +#define MXL_TF_C 2 +#define MXL_TF_C_H 3 +#define MXL_TF_D 4 +#define MXL_TF_D_L 5 +#define MXL_TF_E 6 +#define MXL_TF_F 7 +#define MXL_TF_E_2 8 +#define MXL_TF_E_NA 9 +#define MXL_TF_G 10 + u8 tracking_filter; + +#define MXL_RSSI_DISABLE 0 +#define MXL_RSSI_ENABLE 1 + u8 rssi_enable; + +#define MXL_CAP_SEL_DISABLE 0 +#define MXL_CAP_SEL_ENABLE 1 + u8 cap_select; + +#define MXL_DIV_OUT_1 0 +#define MXL_DIV_OUT_4 1 + u8 div_out; + +#define MXL_CLOCK_OUT_DISABLE 0 +#define MXL_CLOCK_OUT_ENABLE 1 + u8 clock_out; + +#define MXL5005S_IF_OUTPUT_LOAD_200_OHM 200 +#define MXL5005S_IF_OUTPUT_LOAD_300_OHM 300 + u32 output_load; + +#define MXL5005S_TOP_5P5 55 +#define MXL5005S_TOP_7P2 72 +#define MXL5005S_TOP_9P2 92 +#define MXL5005S_TOP_11P0 110 +#define MXL5005S_TOP_12P9 129 +#define MXL5005S_TOP_14P7 147 +#define MXL5005S_TOP_16P8 168 +#define MXL5005S_TOP_19P4 194 +#define MXL5005S_TOP_21P2 212 +#define MXL5005S_TOP_23P2 232 +#define MXL5005S_TOP_25P2 252 +#define MXL5005S_TOP_27P1 271 +#define MXL5005S_TOP_29P2 292 +#define MXL5005S_TOP_31P7 317 +#define MXL5005S_TOP_34P9 349 + u32 top; + +#define MXL_ANALOG_MODE 0 +#define MXL_DIGITAL_MODE 1 + u8 mod_mode; + +#define MXL_ZERO_IF 0 +#define MXL_LOW_IF 1 + u8 if_mode; + /* Stuff I don't know what to do with */ u8 AgcMasterByte; }; -#if defined(CONFIG_MEDIA_TUNER_MXL5005S) || (defined(CONFIG_MEDIA_TUNER_MXL5005S_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_MXL5005S) || \ + (defined(CONFIG_MEDIA_TUNER_MXL5005S_MODULE) && defined(MODULE)) extern struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mxl5005s_config *config); -- cgit v1.2.3 From d211017b954436bfc516e93d839e8746ec2bbbfe Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 19:35:54 -0300 Subject: V4L/DVB(7872): mxl5005s: checkpatch.pl compliance 4 exceptions where the code would read very ugly otherwise. Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 2496 +++++++++++++------------------- drivers/media/common/tuners/mxl5005s.h | 4 +- 2 files changed, 1029 insertions(+), 1471 deletions(-) diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 45ac6a9e71a3..21dca5bdca77 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -86,34 +86,30 @@ static int debug = 2; #define MASTER_CONTROL_ADDR 9 /* Enumeration of Master Control Register State */ -typedef enum -{ +enum master_control_state { MC_LOAD_START = 1, MC_POWER_DOWN, MC_SYNTH_RESET, MC_SEQ_OFF -} Master_Control_State; +}; /* Enumeration of MXL5005 Tuner Modulation Type */ -typedef enum -{ +enum { MXL_DEFAULT_MODULATION = 0, MXL_DVBT, MXL_ATSC, MXL_QAM, MXL_ANALOG_CABLE, MXL_ANALOG_OTA -} Tuner_Modu_Type; +} tuner_modu_type; /* MXL5005 Tuner Register Struct */ -typedef struct _TunerReg_struct -{ +struct TunerReg { u16 Reg_Num; /* Tuner Register Address */ - u16 Reg_Val; /* Current sofware programmed value waiting to be writen */ -} TunerReg_struct; + u16 Reg_Val; /* Current sw programmed value waiting to be writen */ +}; -typedef enum -{ +enum { /* Initialization Control Names */ DN_IQTN_AMP_CUT = 1, /* 1 */ BB_MODE, /* 2 */ @@ -219,16 +215,14 @@ typedef enum #define MXL5005S_BB_DLPF_BANDSEL_LSB 3 /* Standard modes */ -enum -{ +enum { MXL5005S_STANDARD_DVBT, MXL5005S_STANDARD_ATSC, }; #define MXL5005S_STANDARD_MODE_NUM 2 /* Bandwidth modes */ -enum -{ +enum { MXL5005S_BANDWIDTH_6MHZ = 6000000, MXL5005S_BANDWIDTH_7MHZ = 7000000, MXL5005S_BANDWIDTH_8MHZ = 8000000, @@ -236,17 +230,16 @@ enum #define MXL5005S_BANDWIDTH_MODE_NUM 3 /* MXL5005 Tuner Control Struct */ -typedef struct _TunerControl_struct { +struct TunerControl { u16 Ctrl_Num; /* Control Number */ u16 size; /* Number of bits to represent Value */ - u16 addr[25]; /* Array of Tuner Register Address for each bit position */ - u16 bit[25]; /* Array of bit position in Register Address for each bit position */ + u16 addr[25]; /* Array of Tuner Register Address for each bit pos */ + u16 bit[25]; /* Array of bit pos in Reg Addr for each bit pos */ u16 val[25]; /* Binary representation of Value */ -} TunerControl_struct; +}; /* MXL5005 Tuner Struct */ -struct mxl5005s_state -{ +struct mxl5005s_state { u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */ u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */ @@ -256,14 +249,18 @@ struct mxl5005s_state u32 Fxtal; /* XTAL Frequency */ u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */ u16 TOP; /* Value: take over point */ - u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */ + u8 CLOCK_OUT; /* 0: turn off clk out; 1: turn on clock out */ u8 DIV_OUT; /* 4MHz or 16MHz */ u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */ u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */ - u8 Mod_Type; /* Modulation Type; */ - /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ - u8 TF_Type; /* Tracking Filter Type */ - /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + + /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 Mod_Type; + + /* Tracking Filter Type */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + u8 TF_Type; /* Calculated Settings */ u32 RF_LO; /* Synth RF LO Frequency */ @@ -271,22 +268,22 @@ struct mxl5005s_state u32 TG_LO; /* Synth TG_LO Frequency */ /* Pointers to ControlName Arrays */ - u16 Init_Ctrl_Num; /* Number of INIT Control Names */ - TunerControl_struct - Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ + u16 Init_Ctrl_Num; /* Number of INIT Control Names */ + struct TunerControl + Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ - u16 CH_Ctrl_Num; /* Number of CH Control Names */ - TunerControl_struct - CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ + u16 CH_Ctrl_Num; /* Number of CH Control Names */ + struct TunerControl + CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ - u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ - TunerControl_struct - MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ + u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ + struct TunerControl + MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ /* Pointer to Tuner Register Array */ - u16 TunerRegs_Num; /* Number of Tuner Registers */ - TunerReg_struct - TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ + u16 TunerRegs_Num; /* Number of Tuner Registers */ + struct TunerReg + TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ /* Linux driver framework specific */ struct mxl5005s_config *config; @@ -302,21 +299,27 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); u16 MXL_GetMasterControl(u8 *MasterReg, int state); void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal); -u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); +u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count); u32 MXL_Ceiling(u32 value, u32 resolution); u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); -u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup); +u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, + u32 value, u16 controlGroup); u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); -u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count); +u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count); u32 MXL_GetXtalInt(u32 Xtal_Freq); u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); -u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); +u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count); +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, + u8 *datatable, u8 len); u16 MXL_IFSynthInit(struct dvb_frontend *fe); -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, + u32 bandwidth); int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); /* ---------------------------------------------------------------- @@ -343,16 +346,16 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz); - // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code. + /* Set MxL5005S tuner RF frequency according to example code. */ - // Tuner RF frequency setting stage 0 - MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ; + /* Tuner RF frequency setting stage 0 */ + MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); - // Tuner RF frequency setting stage 1 + /* Tuner RF frequency setting stage 1 */ MXL_TuneRF(fe, RfFreqHz); MXL_ControlRead(fe, IF_DIVVAL, &IfDivval); @@ -360,26 +363,28 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0); MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1); MXL_ControlWrite(fe, IF_DIVVAL, 8); - MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen) ; + MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen); - MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; + MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START); AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; + ByteTable[TableLen] = MasterControlByte | + state->config->AgcMasterByte; TableLen += 1; mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); - // Wait 30 ms. + /* Wait 30 ms. */ msleep(150); - // Tuner RF frequency setting stage 2 - MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; - MXL_ControlWrite(fe, IF_DIVVAL, IfDivval) ; - MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen) ; + /* Tuner RF frequency setting stage 2 */ + MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1); + MXL_ControlWrite(fe, IF_DIVVAL, IfDivval); + MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen); - MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; + MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START); AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; + ByteTable[TableLen] = MasterControlByte | + state->config->AgcMasterByte ; TableLen += 1; mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); @@ -398,7 +403,6 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; state->TunerRegs_Num = TUNER_REGS_NUM ; -// state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; state->TunerRegs[0].Reg_Num = 9 ; state->TunerRegs[0].Reg_Val = 0x40 ; @@ -1655,9 +1659,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) return 0 ; } -// MaxLinear source code - MXL5005_c.cpp -// MXL5005.cpp : Defines the initialization routines for the DLL. -// 2.6.12 void InitTunerControls(struct dvb_frontend *fe) { MXL5005_RegisterInit(fe); @@ -1667,57 +1668,28 @@ void InitTunerControls(struct dvb_frontend *fe) #endif } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_ConfigTuner // -// // -// Description: Configure MXL5005Tuner structure for desired // -// Channel Bandwidth/Channel Frequency // -// // -// // -// Functions used: // -// MXL_SynthIFLO_Calc // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// Mode: Tuner Mode (Analog/Digital) // -// IF_Mode: IF Mode ( Zero/Low ) // -// Bandwidth: Filter Channel Bandwidth (in Hz) // -// IF_out: Desired IF out Frequency (in Hz) // -// Fxtal: Crystal Frerquency (in Hz) // -// TOP: 0: Dual AGC; Value: take over point // -// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // -// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // -// DIV_OUT: 0: Div-1; 1: Div-4 // -// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // -// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL5005_TunerConfig(struct dvb_frontend *fe, - u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ - u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ - u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ - u32 IF_out, /* Desired IF Out Frequency */ - u32 Fxtal, /* XTAL Frequency */ - u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ - u16 TOP, /* 0: Dual AGC; Value: take over point */ - u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ - u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */ - u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */ - u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ - u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ - u8 Mod_Type, /* Modulation Type; */ - /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ - u8 TF_Type /* Tracking Filter */ - /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ - ) + u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ + u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ + u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ + u32 IF_out, /* Desired IF Out Frequency */ + u32 Fxtal, /* XTAL Frequency */ + u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ + u16 TOP, /* 0: Dual AGC; Value: take over point */ + u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ + u8 CLOCK_OUT, /* 0: turn off clk out; 1: turn on clock out */ + u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */ + u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ + u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ + + /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 Mod_Type, + + /* Tracking Filter */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + u8 TF_Type + ) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; @@ -1746,105 +1718,40 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, return status; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_SynthIFLO_Calc // -// // -// Description: Calculate Internal IF-LO Frequency // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; if (state->Mode == 1) /* Digital Mode */ state->IF_LO = state->IF_OUT; - else /* Analog Mode */ - { - if(state->IF_Mode == 0) /* Analog Zero IF mode */ + else /* Analog Mode */ { + if (state->IF_Mode == 0) /* Analog Zero IF mode */ state->IF_LO = state->IF_OUT + 400000; else /* Analog Low IF mode */ state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2; } } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_SynthRFTGLO_Calc // -// // -// Description: Calculate Internal RF-LO frequency and // -// internal Tone-Gen(TG)-LO frequency // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; if (state->Mode == 1) /* Digital Mode */ { - //remove 20.48MHz setting for 2.6.10 + /* remove 20.48MHz setting for 2.6.10 */ state->RF_LO = state->RF_IN; - state->TG_LO = state->RF_IN - 750000; //change for 2.6.6 + /* change for 2.6.6 */ + state->TG_LO = state->RF_IN - 750000; } else /* Analog Mode */ { - if(state->IF_Mode == 0) /* Analog Zero IF mode */ { + if (state->IF_Mode == 0) /* Analog Zero IF mode */ { state->RF_LO = state->RF_IN - 400000; state->TG_LO = state->RF_IN - 1750000; } else /* Analog Low IF mode */ { state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2; - state->TG_LO = state->RF_IN - state->Chan_Bandwidth + 500000; + state->TG_LO = state->RF_IN - + state->Chan_Bandwidth + 500000; } } } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_OverwriteICDefault // -// // -// Description: Overwrite the Default Register Setting // -// // -// // -// Functions used: // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { u16 status = 0; @@ -1857,31 +1764,6 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) return status; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_BlockInit // -// // -// Description: Tuner Initialization as a function of 'User Settings' // -// * User settings in Tuner strcuture must be assigned // -// first // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// Tuner_struct: structure defined at higher level // -// // -// Inputs: // -// Tuner : Tuner structure defined at higher level // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_BlockInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1902,42 +1784,45 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) /* Initialize Low-Pass Filter */ if (state->Mode) { /* Digital Mode */ switch (state->Chan_Bandwidth) { - case 8000000: - status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0); - break; - case 7000000: - status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); - break; - case 6000000: - printk("%s() doing 6MHz digital\n", __func__); - status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); - break; + case 8000000: + status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0); + break; + case 7000000: + status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); + break; + case 6000000: + status += MXL_ControlWrite(fe, + BB_DLPF_BANDSEL, 3); + break; } } else { /* Analog Mode */ switch (state->Chan_Bandwidth) { - case 8000000: /* Low Zero */ - status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 0 : 3)); - break; - case 7000000: - status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 1 : 4)); - break; - case 6000000: - status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 2 : 5)); - break; + case 8000000: /* Low Zero */ + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, + (state->IF_Mode ? 0 : 3)); + break; + case 7000000: + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, + (state->IF_Mode ? 1 : 4)); + break; + case 6000000: + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, + (state->IF_Mode ? 2 : 5)); + break; } } /* Charge Pump Control Dig Ana */ - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8); - status += MXL_ControlWrite(fe, RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8); + status += MXL_ControlWrite(fe, + RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1); status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0); /* AGC TOP Control */ if (state->AGC_Mode == 0) /* Dual AGC */ { status += MXL_ControlWrite(fe, AGC_IF, 15); status += MXL_ControlWrite(fe, AGC_RF, 15); - } - else /* Single AGC Mode Dig Ana */ + } else /* Single AGC Mode Dig Ana */ status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); if (state->TOP == 55) /* TOP == 5.5 */ @@ -2008,7 +1893,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, EN_AUX_3P, 1); status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); } - if ((state->IF_OUT == 36125000UL) || (state->IF_OUT == 36150000UL)) { + if ((state->IF_OUT == 36125000UL) || + (state->IF_OUT == 36150000UL)) { status += MXL_ControlWrite(fe, EN_AAF, 1); status += MXL_ControlWrite(fe, EN_3P, 1); status += MXL_ControlWrite(fe, EN_AUX_3P, 1); @@ -2021,15 +1907,13 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1); } } else { /* Analog Mode */ - if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) - { + if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) { status += MXL_ControlWrite(fe, EN_AAF, 1); status += MXL_ControlWrite(fe, EN_3P, 1); status += MXL_ControlWrite(fe, EN_AUX_3P, 1); status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); } - if (state->IF_OUT > 5000000UL) - { + if (state->IF_OUT > 5000000UL) { status += MXL_ControlWrite(fe, EN_AAF, 0); status += MXL_ControlWrite(fe, EN_3P, 0); status += MXL_ControlWrite(fe, EN_AUX_3P, 0); @@ -2073,13 +1957,13 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */ /* Set TG_R_DIV */ - status += MXL_ControlWrite(fe, TG_R_DIV, MXL_Ceiling(state->Fxtal, 1000000)); + status += MXL_ControlWrite(fe, TG_R_DIV, + MXL_Ceiling(state->Fxtal, 1000000)); /* Apply Default value to BB_INITSTATE_DLPF_TUNE */ /* RSSI Control */ - if (state->EN_RSSI) - { + if (state->EN_RSSI) { status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); @@ -2098,8 +1982,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) /* Modulation type bit settings * Override the control values preset */ - if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ - { + if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ { state->AGC_Mode = 1; /* Single AGC Mode */ /* Enable RSSI */ @@ -2122,8 +2005,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ - { + if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ { state->AGC_Mode = 1; /* Single AGC Mode */ /* Enable RSSI */ @@ -2141,14 +2023,15 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, RFA_FLR, 2); status += MXL_ControlWrite(fe, RFA_CEIL, 13); status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1); - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); /* Low Zero */ + /* Low Zero */ + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); + if (state->IF_OUT <= 6280000UL) /* Low IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 0); else /* High IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (state->Mod_Type == MXL_QAM) /* QAM Mode */ - { + if (state->Mod_Type == MXL_QAM) /* QAM Mode */ { state->Mode = MXL_DIGITAL_MODE; /* state->AGC_Mode = 1; */ /* Single AGC Mode */ @@ -2163,7 +2046,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); /* change here for v2.6.5 */ + /* change here for v2.6.5 */ + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); if (state->IF_OUT <= 6280000UL) /* Low IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 0); @@ -2183,7 +2067,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); - status += MXL_ControlWrite(fe, AGC_IF, 1); /* change for 2.6.3 */ + /* change for 2.6.3 */ + status += MXL_ControlWrite(fe, AGC_IF, 1); status += MXL_ControlWrite(fe, AGC_RF, 15); status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } @@ -2207,7 +2092,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } /* RSSI disable */ - if(state->EN_RSSI == 0) { + if (state->EN_RSSI == 0) { status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); @@ -2217,34 +2102,10 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) return status; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_IFSynthInit // -// // -// Description: Tuner IF Synthesizer related register initialization // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// Tuner_struct: structure defined at higher level // -// // -// Inputs: // -// Tuner : Tuner structure defined at higher level // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_IFSynthInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; - // Declare Local Variables u32 Fref = 0 ; u32 Kdbl, intModVal ; u32 fracModVal ; @@ -2255,268 +2116,207 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe) if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) Kdbl = 1 ; - // - // IF Synthesizer Control - // - if (state->Mode == 0 && state->IF_Mode == 1) // Analog Low IF mode - { + /* IF Synthesizer Control */ + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ { if (state->IF_LO == 41000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 328000000UL ; } if (state->IF_LO == 47000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 376000000UL ; } if (state->IF_LO == 54000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 324000000UL ; } if (state->IF_LO == 60000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } if (state->IF_LO == 39250000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 314000000UL ; } if (state->IF_LO == 39650000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 317200000UL ; } if (state->IF_LO == 40150000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 321200000UL ; } if (state->IF_LO == 40650000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 325200000UL ; } } - if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) - { + if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) { if (state->IF_LO == 57000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 342000000UL ; } if (state->IF_LO == 44000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 352000000UL ; } if (state->IF_LO == 43750000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 350000000UL ; } if (state->IF_LO == 36650000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 366500000UL ; } if (state->IF_LO == 36150000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 361500000UL ; } if (state->IF_LO == 36000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } if (state->IF_LO == 35250000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 352500000UL ; } if (state->IF_LO == 34750000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 347500000UL ; } if (state->IF_LO == 6280000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 376800000UL ; } if (state->IF_LO == 5000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } if (state->IF_LO == 4500000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } if (state->IF_LO == 4570000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 365600000UL ; } if (state->IF_LO == 4000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } - if (state->IF_LO == 57400000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 57400000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 344400000UL ; } - if (state->IF_LO == 44400000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 44400000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 355200000UL ; } - if (state->IF_LO == 44150000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 44150000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 353200000UL ; } - if (state->IF_LO == 37050000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 37050000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 370500000UL ; } - if (state->IF_LO == 36550000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 36550000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 365500000UL ; } if (state->IF_LO == 36125000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 361250000UL ; } if (state->IF_LO == 6000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } - if (state->IF_LO == 5400000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + if (state->IF_LO == 5400000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 324000000UL ; } if (state->IF_LO == 5380000UL) { - printk("%s() doing 5.38\n", __func__); - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 322800000UL ; } if (state->IF_LO == 5200000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 374400000UL ; } - if (state->IF_LO == 4900000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 4900000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 352800000UL ; } - if (state->IF_LO == 4400000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 4400000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 352000000UL ; } - if (state->IF_LO == 4063000UL) //add for 2.6.8 - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 4063000UL) /* add for 2.6.8 */ { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 365670000UL ; } } - // CHCAL_INT_MOD_IF - // CHCAL_FRAC_MOD_IF - intModVal = Fref / (state->Fxtal * Kdbl/2) ; - status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal ) ; + /* CHCAL_INT_MOD_IF */ + /* CHCAL_FRAC_MOD_IF */ + intModVal = Fref / (state->Fxtal * Kdbl/2); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal); + + fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * + intModVal); - fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * intModVal); - fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000) ; - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal) ; + fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal); return status ; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_GetXtalInt // -// // -// Description: return the Crystal Integration Value for // -// TG_VCO_BIAS calculation // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// Crystal Frequency Value in Hz // -// // -// Outputs: // -// Calculated Crystal Frequency Integration Value // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// u32 MXL_GetXtalInt(u32 Xtal_Freq) { if ((Xtal_Freq % 1000000) == 0) - return (Xtal_Freq / 10000) ; + return (Xtal_Freq / 10000); else - return (((Xtal_Freq / 1000000) + 1)*100) ; + return (((Xtal_Freq / 1000000) + 1)*100); } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL5005_TuneRF // -// // -// Description: Set control names to tune to requested RF_IN frequency // -// // -// Globals: // -// None // -// // -// Functions used: // -// MXL_SynthRFTGLO_Calc // -// MXL5005_ControlWrite // -// MXL_GetXtalInt // -// // -// Inputs: // -// Tuner : Tuner structure defined at higher level // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// 1 : Unsuccessful // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) { struct mxl5005s_state *state = fe->tuner_priv; - // Declare Local Variables u16 status = 0; u32 divider_val, E3, E4, E5, E5A; u32 Fmax, Fmin, FmaxBin, FminBin; @@ -2527,8 +2327,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) u32 Fref_TG; u32 Fvco; -// u32 temp; - Xtal_Int = MXL_GetXtalInt(state->Fxtal); @@ -2541,21 +2339,19 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) if (state->Fxtal > 22000000 && state->Fxtal <= 32000000) Kdbl_RF = 1; - // - // Downconverter Controls - // - // Look-Up Table Implementation for: - // DN_POLY - // DN_RFGAIN - // DN_CAP_RFLPF - // DN_EN_VHFUHFBAR - // DN_GAIN_ADJUST - // Change the boundary reference from RF_IN to RF_LO - if (state->RF_LO < 40000000UL) { + /* Downconverter Controls + * Look-Up Table Implementation for: + * DN_POLY + * DN_RFGAIN + * DN_CAP_RFLPF + * DN_EN_VHFUHFBAR + * DN_GAIN_ADJUST + * Change the boundary reference from RF_IN to RF_LO + */ + if (state->RF_LO < 40000000UL) return -1; - } + if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { - // Look-Up Table implementation status += MXL_ControlWrite(fe, DN_POLY, 2); status += MXL_ControlWrite(fe, DN_RFGAIN, 3); status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423); @@ -2563,7 +2359,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); } if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { - // Look-Up Table implementation status += MXL_ControlWrite(fe, DN_POLY, 3); status += MXL_ControlWrite(fe, DN_RFGAIN, 3); status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222); @@ -2571,7 +2366,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); } if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { - // Look-Up Table implementation status += MXL_ControlWrite(fe, DN_POLY, 3); status += MXL_ControlWrite(fe, DN_RFGAIN, 3); status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147); @@ -2579,7 +2373,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); } if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { - // Look-Up Table implementation status += MXL_ControlWrite(fe, DN_POLY, 3); status += MXL_ControlWrite(fe, DN_RFGAIN, 3); status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9); @@ -2587,34 +2380,31 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); } if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { - // Look-Up Table implementation - status += MXL_ControlWrite(fe, DN_POLY, 3) ; - status += MXL_ControlWrite(fe, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 3); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3); } if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) { - // Look-Up Table implementation - status += MXL_ControlWrite(fe, DN_POLY, 3) ; - status += MXL_ControlWrite(fe, DN_RFGAIN, 1) ; - status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; - status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 1); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3); } if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) { - // Look-Up Table implementation - status += MXL_ControlWrite(fe, DN_POLY, 3) ; - status += MXL_ControlWrite(fe, DN_RFGAIN, 2) ; - status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; - status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 2); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3); } - if (state->RF_LO > 900000000UL) { + if (state->RF_LO > 900000000UL) return -1; - } - // DN_IQTNBUF_AMP - // DN_IQTNGNBFBIAS_BST + + /* DN_IQTNBUF_AMP */ + /* DN_IQTNGNBFBIAS_BST */ if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); @@ -2680,18 +2470,19 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1); } - // - // Set RF Synth and LO Path Control - // - // Look-Up table implementation for: - // RFSYN_EN_OUTMUX - // RFSYN_SEL_VCO_OUT - // RFSYN_SEL_VCO_HI - // RFSYN_SEL_DIVM - // RFSYN_RF_DIV_BIAS - // DN_SEL_FREQ - // - // Set divider_val, Fmax, Fmix to use in Equations + /* + * Set RF Synth and LO Path Control + * + * Look-Up table implementation for: + * RFSYN_EN_OUTMUX + * RFSYN_SEL_VCO_OUT + * RFSYN_SEL_VCO_HI + * RFSYN_SEL_DIVM + * RFSYN_RF_DIV_BIAS + * DN_SEL_FREQ + * + * Set divider_val, Fmax, Fmix to use in Equations + */ FminBin = 28000000UL ; FmaxBin = 42500000UL ; if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) { @@ -2721,12 +2512,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 56000000UL ; FmaxBin = 85000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); divider_val = 32 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2734,12 +2525,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 85000000UL ; FmaxBin = 112000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); divider_val = 32 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2747,12 +2538,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 112000000UL ; FmaxBin = 170000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2); divider_val = 16 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2760,12 +2551,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 170000000UL ; FmaxBin = 225000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2); divider_val = 16 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2773,12 +2564,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 225000000UL ; FmaxBin = 300000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4); divider_val = 8 ; Fmax = 340000000UL ; Fmin = FminBin ; @@ -2786,12 +2577,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 300000000UL ; FmaxBin = 340000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); divider_val = 8 ; Fmax = FmaxBin ; Fmin = 225000000UL ; @@ -2799,12 +2590,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 340000000UL ; FmaxBin = 450000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); divider_val = 8 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2812,12 +2603,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 450000000UL ; FmaxBin = 680000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2825,67 +2616,66 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 680000000UL ; FmaxBin = 900000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; } - // CHCAL_INT_MOD_RF - // CHCAL_FRAC_MOD_RF - // RFSYN_LPF_R - // CHCAL_EN_INT_RF - - // Equation E3 - // RFSYN_VCO_BIAS + /* CHCAL_INT_MOD_RF + * CHCAL_FRAC_MOD_RF + * RFSYN_LPF_R + * CHCAL_EN_INT_RF + */ + /* Equation E3 RFSYN_VCO_BIAS */ E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; - status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3) ; + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3); - // Equation E4 - // CHCAL_INT_MOD_RF - E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000) ; - MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4) ; + /* Equation E4 CHCAL_INT_MOD_RF */ + E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000); + MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4); - // Equation E5 - // CHCAL_FRAC_MOD_RF - // CHCAL_EN_INT_RF - E5 = ((2<<17)*(state->RF_LO/10000*divider_val - (E4*(2*state->Fxtal*Kdbl_RF)/10000)))/(2*state->Fxtal*Kdbl_RF/10000) ; - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ; + /* Equation E5 CHCAL_FRAC_MOD_RF CHCAL_EN_INT_RF */ + E5 = ((2<<17)*(state->RF_LO/10000*divider_val - + (E4*(2*state->Fxtal*Kdbl_RF)/10000))) / + (2*state->Fxtal*Kdbl_RF/10000); - // Equation E5A - // RFSYN_LPF_R + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5); + + /* Equation E5A RFSYN_LPF_R */ E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; - status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A) ; + status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A); - // Euqation E5B - // CHCAL_EN_INIT_RF + /* Euqation E5B CHCAL_EN_INIT_RF */ status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); - //if (E5 == 0) - // status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1); - //else - // status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ; - - // - // Set TG Synth - // - // Look-Up table implementation for: - // TG_LO_DIVVAL - // TG_LO_SELVAL - // - // Set divider_val, Fmax, Fmix to use in Equations - if (state->TG_LO < 33000000UL) { + /*if (E5 == 0) + * status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1); + *else + * status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5); + */ + + /* + * Set TG Synth + * + * Look-Up table implementation for: + * TG_LO_DIVVAL + * TG_LO_SELVAL + * + * Set divider_val, Fmax, Fmix to use in Equations + */ + if (state->TG_LO < 33000000UL) return -1; - } + FminBin = 33000000UL ; FmaxBin = 50000000UL ; if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0); divider_val = 36 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2893,8 +2683,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 50000000UL ; FmaxBin = 67000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0); divider_val = 24 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2902,8 +2692,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 67000000UL ; FmaxBin = 100000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2); divider_val = 18 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2911,8 +2701,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 100000000UL ; FmaxBin = 150000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2); divider_val = 12 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2920,8 +2710,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 150000000UL ; FmaxBin = 200000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2); divider_val = 8 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2929,8 +2719,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 200000000UL ; FmaxBin = 300000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3); divider_val = 6 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2938,8 +2728,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 300000000UL ; FmaxBin = 400000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3); divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2947,8 +2737,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 400000000UL ; FmaxBin = 600000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7); divider_val = 3 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2956,682 +2746,608 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 600000000UL ; FmaxBin = 900000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7); divider_val = 2 ; Fmax = FmaxBin ; Fmin = FminBin ; } - // TG_DIV_VAL - tg_divval = (state->TG_LO*divider_val/100000) - *(MXL_Ceiling(state->Fxtal,1000000) * 100) / (state->Fxtal/1000) ; - status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval) ; + /* TG_DIV_VAL */ + tg_divval = (state->TG_LO*divider_val/100000) * + (MXL_Ceiling(state->Fxtal, 1000000) * 100) / + (state->Fxtal/1000); + + status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval); if (state->TG_LO > 600000000UL) - status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1 ) ; + status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1); Fmax = 1800000000UL ; Fmin = 1200000000UL ; + /* prevent overflow of 32 bit unsigned integer, use + * following equation. Edit for v2.6.4 + */ + /* Fref_TF = Fref_TG * 1000 */ + Fref_TG = (state->Fxtal/1000) / MXL_Ceiling(state->Fxtal, 1000000); - - // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4 - Fref_TG = (state->Fxtal/1000)/ MXL_Ceiling(state->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000 - - Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10 + /* Fvco = Fvco/10 */ + Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8; - //below equation is same as above but much harder to debug. - //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((state->TG_LO/10000)*divider_val*(state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ; - - - status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo) ; - + /* below equation is same as above but much harder to debug. + * tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - + * ((state->TG_LO/10000)*divider_val * + * (state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * + * Xtal_Int/100) + 8; + */ + status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo); - //add for 2.6.5 - //Special setting for QAM - if(state->Mod_Type == MXL_QAM) - { - if(state->RF_IN < 680000000) - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; - else - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2) ; + /* add for 2.6.5 Special setting for QAM */ + if (state->Mod_Type == MXL_QAM) { + if (state->RF_IN < 680000000) + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); + else + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2); } - - //remove 20.48MHz setting for 2.6.10 - - // - // Off Chip Tracking Filter Control - // - if (state->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; - - status += MXL_SetGPIO(fe, 3, 1) ; // turn off Bank 1 - status += MXL_SetGPIO(fe, 1, 1) ; // turn off Bank 2 - status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3 + /* Off Chip Tracking Filter Control */ + if (state->TF_Type == MXL_TF_OFF) { + /* Tracking Filter Off State; turn off all the banks */ + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 3, 1); /* Bank1 Off */ + status += MXL_SetGPIO(fe, 1, 1); /* Bank2 Off */ + status += MXL_SetGPIO(fe, 4, 1); /* Bank3 Off */ } - if (state->TF_Type == MXL_TF_C) // Tracking Filter type C - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; - status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) - { - - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off - } - if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off - } - if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On - } - if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On - } - if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(fe, DAC_DIN_B, 29) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On - } - if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On - } - if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(fe, DAC_DIN_B, 16) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off - } - if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(fe, DAC_DIN_B, 7) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off - } - if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_C) /* Tracking Filter type C */ { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_A, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); + } + if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 4, 1); + } + if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 4, 0); + } + if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 0); + } + if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_B, 29); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 0); + } + if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 0); + } + if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_B, 16); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); + } + if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_B, 7); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); + } + if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); } } - if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only - { - printk("%s() CH filter\n", __func__); - status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) - { - - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off - } - if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off - } - if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On - } - if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On - } - if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On - } - if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On - } - if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off - } - if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off - } - if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_C_H) { + + /* Tracking Filter type C-H for Hauppauge only */ + status += MXL_ControlWrite(fe, DAC_DIN_A, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + } + if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 0); + status += MXL_SetGPIO(fe, 1, 1); + } + if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 0); + status += MXL_SetGPIO(fe, 1, 0); + } + if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 0); + } + if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 0); + } + if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 0); + } + if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + } + if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + } + if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); } } - if (state->TF_Type == MXL_TF_D) // Tracking Filter type D - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_D) { /* Tracking Filter type D */ + + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } - - if (state->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 - { - status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; - - // if UHF and terrestrial => Turn off Tracking Filter - if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) - { - // Turn off all the banks - status += MXL_SetGPIO(fe, 3, 1) ; - status += MXL_SetGPIO(fe, 1, 1) ; - status += MXL_SetGPIO(fe, 4, 1) ; - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; - - status += MXL_ControlWrite(fe, AGC_IF, 10) ; - } - - else // if VHF or cable => Turn on Tracking Filter - { - if (state->RF_IN >= 43000000 && state->RF_IN < 140000000) - { - - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off + if (state->TF_Type == MXL_TF_D_L) { + + /* Tracking Filter type D-L for Lumanate ONLY change 2.6.3 */ + status += MXL_ControlWrite(fe, DAC_DIN_A, 0); + + /* if UHF and terrestrial => Turn off Tracking Filter */ + if (state->RF_IN >= 471000000 && + (state->RF_IN - 471000000)%6000000 != 0) { + /* Turn off all the banks */ + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, AGC_IF, 10); + } else { + /* if VHF or cable => Turn on Tracking Filter */ + if (state->RF_IN >= 43000000 && + state->RF_IN < 140000000) { + + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); } - if (state->RF_IN >= 140000000 && state->RF_IN < 240000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off + if (state->RF_IN >= 140000000 && + state->RF_IN < 240000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); } - if (state->RF_IN >= 240000000 && state->RF_IN < 340000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off + if (state->RF_IN >= 240000000 && + state->RF_IN < 340000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); } - if (state->RF_IN >= 340000000 && state->RF_IN < 430000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On + if (state->RF_IN >= 340000000 && + state->RF_IN < 430000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); } - if (state->RF_IN >= 430000000 && state->RF_IN < 470000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On + if (state->RF_IN >= 430000000 && + state->RF_IN < 470000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); } - if (state->RF_IN >= 470000000 && state->RF_IN < 570000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On + if (state->RF_IN >= 470000000 && + state->RF_IN < 570000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); } - if (state->RF_IN >= 570000000 && state->RF_IN < 620000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Offq + if (state->RF_IN >= 570000000 && + state->RF_IN < 620000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } - if (state->RF_IN >= 620000000 && state->RF_IN < 760000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->RF_IN >= 620000000 && + state->RF_IN < 760000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } - if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->RF_IN >= 760000000 && + state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } } - if (state->TF_Type == MXL_TF_E) // Tracking Filter type E - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_E) /* Tracking Filter type E */ { + + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } - if (state->TF_Type == MXL_TF_F) // Tracking Filter type F - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_F) { + + /* Tracking Filter type F */ + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } - if (state->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_E_2) { + + /* Tracking Filter type E_2 */ + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } - if (state->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) //modified for 2.6.11 - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_G) { + + /* Tracking Filter type G add for v2.6.8 */ + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) { + + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } - if (state->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - // if UHF and terrestrial=> Turn off Tracking Filter - if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) - { - // Turn off all the banks - status += MXL_SetGPIO(fe, 3, 1) ; - status += MXL_SetGPIO(fe, 1, 1) ; - status += MXL_SetGPIO(fe, 4, 1) ; - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; - - //2.6.12 - //Turn on RSSI - status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1) ; - - // RSSI reference point - status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5) ; - status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3) ; - status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2) ; - - - //status += MXL_ControlWrite(fe, AGC_IF, 10) ; //doesn't matter since RSSI is turn on - - //following parameter is from analog OTA mode, can be change to seek better performance - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; - } - - else //if VHF or Cable => Turn on Tracking Filter - { - //2.6.12 - //Turn off RSSI - status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0) ; - - //change back from above condition - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5) ; - - - if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_E_NA) { + + /* Tracking Filter type E-NA for Empia ONLY change for 2.6.8 */ + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + /* if UHF and terrestrial=> Turn off Tracking Filter */ + if (state->RF_IN >= 471000000 && + (state->RF_IN - 471000000)%6000000 != 0) { + + /* Turn off all the banks */ + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + + /* 2.6.12 Turn on RSSI */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); + + /* following parameter is from analog OTA mode, + * can be change to seek better performance */ + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); + } else { + /* if VHF or Cable => Turn on Tracking Filter */ + + /* 2.6.12 Turn off RSSI */ + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); + + /* change back from above condition */ + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); + + + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { + + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } } @@ -3679,72 +3395,24 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) return status; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_ControlWrite // -// // -// Description: Update control name value // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// MXL_ControlWrite( Tuner, controlName, value, Group ) // -// // -// Inputs: // -// Tuner : Tuner structure // -// ControlName : Control name to be updated // -// value : Value to be written // -// // -// Outputs: // -// Tuner : Tuner structure defined at higher level // -// // -// Return: // -// 0 : Successful write // -// >0 : Value exceed maximum allowed for control number // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { u16 status = 0; /* Will write ALL Matching Control Name */ - status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control */ - status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control */ + /* Write Matching INIT Control */ + status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); + /* Write Matching CH Control */ + status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); #ifdef _MXL_INTERNAL - status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control */ + /* Write Matching MXL Control */ + status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); #endif return status; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_ControlWrite // -// // -// Description: Update control name value // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// strcmp // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// ControlName : Control Name // -// value : Value Assigned to Control Name // -// controlGroup : Control Register Group // -// // -// Outputs: // -// NONE // -// // -// Return: // -// 0 : Successful write // -// 1 : Value exceed maximum allowed for control name // -// 2 : Control name not found // -// // -/////////////////////////////////////////////////////////////////////////////// -u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) +u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, + u16 controlGroup) { struct mxl5005s_state *state = fe->tuner_priv; u16 i, j, k; @@ -3763,13 +3431,12 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]), (u8)(state->Init_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ); + (u8)((value>>j) & 0x01)); } ctrlVal = 0; for (k = 0; k < state->Init_Ctrl[i].size; k++) ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); - } - else + } else return -1; } } @@ -3778,7 +3445,7 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u for (i = 0; i < state->CH_Ctrl_Num; i++) { - if (controlNum == state->CH_Ctrl[i].Ctrl_Num ) { + if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { highLimit = 1 << state->CH_Ctrl[i].size; if (value < highLimit) { @@ -3786,13 +3453,12 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]), (u8)(state->CH_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ); + (u8)((value>>j) & 0x01)); } ctrlVal = 0; for (k = 0; k < state->CH_Ctrl[i].size; k++) ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); - } - else + } else return -1; } } @@ -3802,21 +3468,20 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u for (i = 0; i < state->MXL_Ctrl_Num; i++) { - if (controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { + if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { - highLimit = (1 << state->MXL_Ctrl[i].size) ; + highLimit = (1 << state->MXL_Ctrl[i].size); if (value < highLimit) { for (j = 0; j < state->MXL_Ctrl[i].size; j++) { state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]), (u8)(state->MXL_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ); + (u8)((value>>j) & 0x01)); } ctrlVal = 0; - for(k = 0; k < state->MXL_Ctrl[i].size; k++) + for (k = 0; k < state->MXL_Ctrl[i].size; k++) ctrlVal += state->MXL_Ctrl[i].val[k] * (1 << k); - } - else + } else return -1; } } @@ -3825,31 +3490,6 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u return 0 ; /* successful return */ } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_RegWrite // -// // -// Description: Update tuner register value // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// RegNum : Register address to be assigned a value // -// RegVal : Register value to write // -// // -// Outputs: // -// NONE // -// // -// Return: // -// 0 : Successful write // -// -1 : Invalid Register Address // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3865,37 +3505,13 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) return 1; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_RegRead // -// // -// Description: Retrieve tuner register value // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// RegNum : Register address to be assigned a value // -// // -// Outputs: // -// RegVal : Retrieved register value // -// // -// Return: // -// 0 : Successful read // -// -1 : Invalid Register Address // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; int i ; for (i = 0; i < 104; i++) { - if (RegNum == state->TunerRegs[i].Reg_Num ) { + if (RegNum == state->TunerRegs[i].Reg_Num) { *RegVal = (u8)(state->TunerRegs[i].Reg_Val); return 0; } @@ -3904,27 +3520,6 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) return 1; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_ControlRead // -// // -// Description: Retrieve the control value based on the control name // -// // -// Globals: // -// NONE // -// // -// Inputs: // -// Tuner_struct : structure defined at higher level // -// ControlName : Control Name // -// // -// Outputs: // -// value : returned control value // -// // -// Return: // -// 0 : Successful read // -// -1 : Invalid control name // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3937,7 +3532,7 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) ctrlVal = 0; for (k = 0; k < state->Init_Ctrl[i].size; k++) - ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); + ctrlVal += state->Init_Ctrl[i].val[k] * (1<tuner_priv; u16 i, j, k ; @@ -4004,7 +3577,7 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int for (i = 0; i < state->Init_Ctrl_Num ; i++) { - if ( controlNum == state->Init_Ctrl[i].Ctrl_Num ) { + if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { Count = 1; RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]); @@ -4013,9 +3586,10 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int for (j = 0; j < Count; j++) { - if (state->Init_Ctrl[i].addr[k] != RegNum[j]) { + if (state->Init_Ctrl[i].addr[k] != + RegNum[j]) { - Count ++; + Count++; RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]); } @@ -4028,18 +3602,19 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int } for (i = 0; i < state->CH_Ctrl_Num ; i++) { - if ( controlNum == state->CH_Ctrl[i].Ctrl_Num ) { + if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { Count = 1; RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]); for (k = 1; k < state->CH_Ctrl[i].size; k++) { - for (j= 0; jCH_Ctrl[i].addr[k] != RegNum[j]) { + if (state->CH_Ctrl[i].addr[k] != + RegNum[j]) { - Count ++; + Count++; RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]); } @@ -4052,18 +3627,19 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int #ifdef _MXL_INTERNAL for (i = 0; i < state->MXL_Ctrl_Num ; i++) { - if ( controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { + if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { Count = 1; RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]); for (k = 1; k < state->MXL_Ctrl[i].size; k++) { - for (j = 0; jMXL_Ctrl[i].addr[k] != RegNum[j]) { + if (state->MXL_Ctrl[i].addr[k] != + RegNum[j]) { - Count ++; + Count++; RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k]; } @@ -4078,29 +3654,6 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int return 1; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_RegWriteBit // -// // -// Description: Write a register for specified register address, // -// register bit and register bit value // -// // -// Globals: // -// NONE // -// // -// Inputs: // -// Tuner_struct : structure defined at higher level // -// address : register address // -// bit : register bit number // -// bitVal : register bit value // -// // -// Outputs: // -// NONE // -// // -// Return: // -// NONE // -// // -/////////////////////////////////////////////////////////////////////////////// void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4125,38 +3678,14 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) } } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_Ceiling // -// // -// Description: Complete to closest increment of resolution // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// value : Input number to compute // -// resolution : Increment step // -// // -// Outputs: // -// NONE // -// // -// Return: // -// Computed value // -// // -/////////////////////////////////////////////////////////////////////////////// u32 MXL_Ceiling(u32 value, u32 resolution) { return (value/resolution + (value % resolution > 0 ? 1 : 0)); } -// -// Retrieve the Initialzation Registers -// -u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) +/* Retrieve the Initialzation Registers */ +u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count) { u16 status = 0; int i ; @@ -4178,21 +3707,24 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c return status; } -u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) +u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, + int *count) { u16 status = 0; int i ; -//add 77, 166, 167, 168 register for 2.6.12 +/* add 77, 166, 167, 168 register for 2.6.12 */ #ifdef _MXL_PRODUCTION u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; #else u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; - //u8 RegAddr[171]; - //for (i=0; i<=170; i++) - // RegAddr[i] = i; + /* + u8 RegAddr[171]; + for (i = 0; i <= 170; i++) + RegAddr[i] = i; + */ #endif *count = sizeof(RegAddr) / sizeof(u8); @@ -4205,7 +3737,8 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou return status; } -u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) +u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, + int *count) { u16 status = 0; int i; @@ -4222,7 +3755,8 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i return status; } -u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) +u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, + int *count) { u16 status = 0; int i; @@ -4267,23 +3801,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); - if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 1) { + /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 180224); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 180224); } - if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 0) { + /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 222822); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 222822); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 229376); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 229376); } } @@ -4298,23 +3837,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); - if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 1) { + /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 206438); } - if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 0) { + /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 206438); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 16384); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 16384); } } @@ -4329,23 +3873,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); - if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 1) { + /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 173670); } - if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 0) { + /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 173670); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 245760); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 245760); } } @@ -4360,23 +3909,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); - if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 1) { + /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 206438); } - if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 0) { + /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 206438); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 212992); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 212992); } } @@ -4440,7 +3994,7 @@ static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) if (latch == 0) msg.len = 2; - dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); + dprintk(2, "%s(0x%x, 0x%x, 0x%x)\n", __func__, reg, val, msg.addr); if (i2c_transfer(state->i2c, &msg, 1) != 1) { printk(KERN_WARNING "mxl5005s I2C write failed\n"); @@ -4449,7 +4003,8 @@ static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) return 0; } -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len) +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, + u8 len) { int ret = 0, i; @@ -4506,7 +4061,8 @@ int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) return 0; } -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, + u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; struct mxl5005s_config *c = state->config; @@ -4553,8 +4109,8 @@ static int mxl5005s_set_params(struct dvb_frontend *fe, case QAM_AUTO: req_mode = MXL_QAM; break; } - } - else req_mode = MXL_DVBT; + } else + req_mode = MXL_DVBT; /* Change tuner for new modulation type if reqd */ if (req_mode != state->current_mode) { @@ -4655,9 +4211,11 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, state->i2c = i2c; state->current_mode = MXL_QAM; - printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); + printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", + config->i2c_address); - memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, sizeof(struct dvb_tuner_ops)); + memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, + sizeof(struct dvb_tuner_ops)); fe->tuner_priv = state; return fe; diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h index 687cf146c2a0..0027d1e03f99 100644 --- a/drivers/media/common/tuners/mxl5005s.h +++ b/drivers/media/common/tuners/mxl5005s.h @@ -25,8 +25,8 @@ #include -struct mxl5005s_config -{ +struct mxl5005s_config { + /* 7 bit i2c address */ u8 i2c_address; -- cgit v1.2.3 From 66321ba94f59ea7ba6f4451c51e171f5b30f1fd7 Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Sat, 3 May 2008 13:51:11 -0300 Subject: V4L/DVB(7873): mxl5005s: Fix header includes. Ensure we have the correct .h dependencies included. Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h index 0027d1e03f99..396db150bf0c 100644 --- a/drivers/media/common/tuners/mxl5005s.h +++ b/drivers/media/common/tuners/mxl5005s.h @@ -23,7 +23,8 @@ #ifndef __MXL5005S_H #define __MXL5005S_H -#include +#include +#include "dvb_frontend.h" struct mxl5005s_config { -- cgit v1.2.3 From c6c34b1ffd40e00191e05bf0ef543a35ccd7d75d Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Sat, 3 May 2008 14:14:54 -0300 Subject: V4L/DVB(7874): mxl5005s: Fix function statics Fix function statics Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 121 +++++++++++++++++---------------- 1 file changed, 62 insertions(+), 59 deletions(-) diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 21dca5bdca77..96391648871a 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -295,32 +295,34 @@ struct mxl5005s_state { }; -u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); -u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); -u16 MXL_GetMasterControl(u8 *MasterReg, int state); -void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal); -u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, +static u16 MXL_GetMasterControl(u8 *MasterReg, int state); +static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); +static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); +static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, + u8 bitVal); +static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -u32 MXL_Ceiling(u32 value, u32 resolution); -u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); -u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); -u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, +static u32 MXL_Ceiling(u32 value, u32 resolution); +static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); +static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); +static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup); -u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); -u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, +static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); +static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -u32 MXL_GetXtalInt(u32 Xtal_Freq); -u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); -void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); -void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); -u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, +static u32 MXL_GetXtalInt(u32 Xtal_Freq); +static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); +static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); +static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); +static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, +static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); -u16 MXL_IFSynthInit(struct dvb_frontend *fe); -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, +static u16 MXL_IFSynthInit(struct dvb_frontend *fe); +static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, + u32 bandwidth); +static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); -int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); /* ---------------------------------------------------------------- * Begin: Custom code salvaged from the Realtek driver. @@ -334,14 +336,14 @@ int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); * Revision: 080314 - original version */ -int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) +static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { struct mxl5005s_state *state = fe->tuner_priv; unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - u32 IfDivval; + u32 IfDivval = 0; unsigned char MasterControlByte; dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz); @@ -399,7 +401,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) * Begin: Reference driver code found in the Realtek driver. * Copyright (c) 2008 MaxLinear */ -u16 MXL5005_RegisterInit(struct dvb_frontend *fe) +static u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; state->TunerRegs_Num = TUNER_REGS_NUM ; @@ -719,7 +721,7 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) return 0 ; } -u16 MXL5005_ControlInit(struct dvb_frontend *fe) +static u16 MXL5005_ControlInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; state->Init_Ctrl_Num = INITCTRL_NUM; @@ -1659,7 +1661,7 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) return 0 ; } -void InitTunerControls(struct dvb_frontend *fe) +static void InitTunerControls(struct dvb_frontend *fe) { MXL5005_RegisterInit(fe); MXL5005_ControlInit(fe); @@ -1668,7 +1670,7 @@ void InitTunerControls(struct dvb_frontend *fe) #endif } -u16 MXL5005_TunerConfig(struct dvb_frontend *fe, +static u16 MXL5005_TunerConfig(struct dvb_frontend *fe, u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ @@ -1718,7 +1720,7 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, return status; } -void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) +static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; if (state->Mode == 1) /* Digital Mode */ @@ -1731,7 +1733,7 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) } } -void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) +static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1752,7 +1754,7 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) } } -u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) +static u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { u16 status = 0; @@ -1764,7 +1766,7 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) return status; } -u16 MXL_BlockInit(struct dvb_frontend *fe) +static u16 MXL_BlockInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; @@ -2102,7 +2104,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) return status; } -u16 MXL_IFSynthInit(struct dvb_frontend *fe) +static u16 MXL_IFSynthInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; @@ -2306,7 +2308,7 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe) return status ; } -u32 MXL_GetXtalInt(u32 Xtal_Freq) +static u32 MXL_GetXtalInt(u32 Xtal_Freq) { if ((Xtal_Freq % 1000000) == 0) return (Xtal_Freq / 10000); @@ -2314,7 +2316,7 @@ u32 MXL_GetXtalInt(u32 Xtal_Freq) return (((Xtal_Freq / 1000000) + 1)*100); } -u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) +static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; @@ -3354,7 +3356,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) return status ; } -u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) +static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { u16 status = 0; @@ -3395,7 +3397,7 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) return status; } -u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) +static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { u16 status = 0; @@ -3411,8 +3413,8 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) return status; } -u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, - u16 controlGroup) +static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, + u32 value, u16 controlGroup) { struct mxl5005s_state *state = fe->tuner_priv; u16 i, j, k; @@ -3490,7 +3492,7 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, return 0 ; /* successful return */ } -u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) +static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { struct mxl5005s_state *state = fe->tuner_priv; int i ; @@ -3505,7 +3507,7 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) return 1; } -u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) +static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; int i ; @@ -3520,7 +3522,7 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) return 1; } -u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) +static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { struct mxl5005s_state *state = fe->tuner_priv; u32 ctrlVal ; @@ -3568,8 +3570,8 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) return 1; } -u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, - int *count) +static u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, + u8 *RegNum, int *count) { struct mxl5005s_state *state = fe->tuner_priv; u16 i, j, k ; @@ -3654,7 +3656,8 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, return 1; } -void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) +static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, + u8 bitVal) { struct mxl5005s_state *state = fe->tuner_priv; int i ; @@ -3678,13 +3681,13 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) } } -u32 MXL_Ceiling(u32 value, u32 resolution) +static u32 MXL_Ceiling(u32 value, u32 resolution) { return (value/resolution + (value % resolution > 0 ? 1 : 0)); } /* Retrieve the Initialzation Registers */ -u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, +static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -3707,7 +3710,7 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, return status; } -u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, +static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -3737,8 +3740,8 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, return status; } -u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, - int *count) +static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count) { u16 status = 0; int i; @@ -3755,8 +3758,8 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, return status; } -u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, - int *count) +static u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count) { u16 status = 0; int i; @@ -3773,7 +3776,7 @@ u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, return status; } -u16 MXL_GetMasterControl(u8 *MasterReg, int state) +static u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) /* Load_Start */ *MasterReg = 0xF3; @@ -3788,7 +3791,7 @@ u16 MXL_GetMasterControl(u8 *MasterReg, int state) } #ifdef _MXL_PRODUCTION -u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) +static u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; @@ -3937,7 +3940,7 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) return status; } -u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) +static u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; @@ -4003,8 +4006,8 @@ static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) return 0; } -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, - u8 len) +static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, + u8 *datatable, u8 len) { int ret = 0, i; @@ -4025,14 +4028,14 @@ int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, return ret; } - -int mxl5005s_init(struct dvb_frontend *fe) +static int mxl5005s_init(struct dvb_frontend *fe) { dprintk(1, "%s()\n", __func__); return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ); } -int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) +static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, + u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4061,7 +4064,7 @@ int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) return 0; } -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, +static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; -- cgit v1.2.3 From 90257e787faaf5ebfaa1839917e4dc6c5c104c14 Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Sat, 3 May 2008 14:21:58 -0300 Subject: V4L/DVB(7875): mxl5005s: Remove redundant functions Remove redundant functions Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 120 --------------------------------- 1 file changed, 120 deletions(-) diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 96391648871a..786f8daa6de9 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -304,7 +304,6 @@ static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); static u32 MXL_Ceiling(u32 value, u32 resolution); static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); -static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup); static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); @@ -3492,21 +3491,6 @@ static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, return 0 ; /* successful return */ } -static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) -{ - struct mxl5005s_state *state = fe->tuner_priv; - int i ; - - for (i = 0; i < 104; i++) { - if (RegNum == state->TunerRegs[i].Reg_Num) { - state->TunerRegs[i].Reg_Val = RegVal; - return 0; - } - } - - return 1; -} - static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3570,92 +3554,6 @@ static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) return 1; } -static u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, - u8 *RegNum, int *count) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u16 i, j, k ; - u16 Count ; - - for (i = 0; i < state->Init_Ctrl_Num ; i++) { - - if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { - - Count = 1; - RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]); - - for (k = 1; k < state->Init_Ctrl[i].size; k++) { - - for (j = 0; j < Count; j++) { - - if (state->Init_Ctrl[i].addr[k] != - RegNum[j]) { - - Count++; - RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]); - - } - } - - } - *count = Count; - return 0; - } - } - for (i = 0; i < state->CH_Ctrl_Num ; i++) { - - if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { - - Count = 1; - RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]); - - for (k = 1; k < state->CH_Ctrl[i].size; k++) { - - for (j = 0; j < Count; j++) { - - if (state->CH_Ctrl[i].addr[k] != - RegNum[j]) { - - Count++; - RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]); - - } - } - } - *count = Count; - return 0; - } - } -#ifdef _MXL_INTERNAL - for (i = 0; i < state->MXL_Ctrl_Num ; i++) { - - if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { - - Count = 1; - RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]); - - for (k = 1; k < state->MXL_Ctrl[i].size; k++) { - - for (j = 0; j < Count; j++) { - - if (state->MXL_Ctrl[i].addr[k] != - RegNum[j]) { - - Count++; - RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k]; - - } - } - } - *count = Count; - return 0; - } - } -#endif - *count = 0; - return 1; -} - static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { @@ -3758,24 +3656,6 @@ static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, return status; } -static u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, - u8 *RegVal, int *count) -{ - u16 status = 0; - int i; - - u8 RegAddr[] = { 138 }; - - *count = sizeof(RegAddr) / sizeof(u8); - - for (i = 0; i < *count; i++) { - RegNum[i] = RegAddr[i]; - status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); - } - - return status; -} - static u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) /* Load_Start */ -- cgit v1.2.3 From 7fa2a1462fe0a258fb629f8447f31c1b3a6d6c68 Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Sat, 3 May 2008 14:25:55 -0300 Subject: V4L/DVB(7876): mxl5005s: Remove incorrect copyright holders I was informed by Jan Hoogenraad that two people needed to be removed from the original copyright comments. Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index 786f8daa6de9..a32c35766a4d 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -16,8 +16,8 @@ mxl5005s_release() mxl5005s_attach() - Copyright (c) 2008 Realtek - Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + Copyright (C) 2008 Realtek + Copyright (C) 2008 Jan Hoogenraad Functions: mxl5005s_SetRfFreqHz() @@ -325,8 +325,8 @@ static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, /* ---------------------------------------------------------------- * Begin: Custom code salvaged from the Realtek driver. - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * Copyright (C) 2008 Realtek + * Copyright (C) 2008 Jan Hoogenraad * This code is placed under the terms of the GNU General Public License * * Released by Realtek under GPLv2. @@ -398,7 +398,7 @@ static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) /* ---------------------------------------------------------------- * Begin: Reference driver code found in the Realtek driver. - * Copyright (c) 2008 MaxLinear + * Copyright (C) 2008 MaxLinear */ static u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { -- cgit v1.2.3 From 77ad55ec2159735b1b88a006a90f8dd2ffe291ca Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Sat, 3 May 2008 14:28:43 -0300 Subject: V4L/DVB(7877): mxl5005s: Ensure debug is off Ensure debug is off Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/mxl5005s.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c index a32c35766a4d..5d05b5390f66 100644 --- a/drivers/media/common/tuners/mxl5005s.c +++ b/drivers/media/common/tuners/mxl5005s.c @@ -66,7 +66,7 @@ #include "dvb_frontend.h" #include "mxl5005s.h" -static int debug = 2; +static int debug; #define dprintk(level, arg...) do { \ if (level <= debug) \ -- cgit v1.2.3 From 9426954277aa57e0417d89bfe3e0964d6901cfa3 Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 8 May 2008 12:14:40 -0300 Subject: V4L/DVB(7878): mxl55005s: Makefile and Kconfig additions Makefile and Kconfig additions Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/Kconfig | 7 +++++++ drivers/media/common/tuners/Makefile | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/media/common/tuners/Kconfig b/drivers/media/common/tuners/Kconfig index 10f12bad1044..394cb050bc77 100644 --- a/drivers/media/common/tuners/Kconfig +++ b/drivers/media/common/tuners/Kconfig @@ -139,4 +139,11 @@ config MEDIA_TUNER_XC5000 This device is only used inside a SiP called togther with a demodulator for now. +config MEDIA_TUNER_MXL5005S + tristate "MaxLinear MSL5005S silicon tuner" + depends on I2C + default m if DVB_FE_CUSTOMISE + help + A driver for the silicon tuner MXL5005S from MaxLinear. + endif # MEDIA_TUNER_CUSTOMIZE diff --git a/drivers/media/common/tuners/Makefile b/drivers/media/common/tuners/Makefile index 236d9932fd92..55f7e6706297 100644 --- a/drivers/media/common/tuners/Makefile +++ b/drivers/media/common/tuners/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_MEDIA_TUNER_MT2060) += mt2060.o obj-$(CONFIG_MEDIA_TUNER_MT2266) += mt2266.o obj-$(CONFIG_MEDIA_TUNER_QT1010) += qt1010.o obj-$(CONFIG_MEDIA_TUNER_MT2131) += mt2131.o +obj-$(CONFIG_MEDIA_TUNER_MXL5005S) += mxl5005s.o EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core EXTRA_CFLAGS += -Idrivers/media/dvb/frontends -- cgit v1.2.3 From 671294719628f1671faefd4882764886f8ad08cb Mon Sep 17 00:00:00 2001 From: Steven Toth Date: Thu, 1 May 2008 07:23:23 -0300 Subject: V4L/DVB(7879): Adding cx18 Support for mxl5005s Adding cx18 Support Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/cx18/Kconfig | 1 + drivers/media/video/cx18/cx18-cards.c | 3 ++- drivers/media/video/cx18/cx18-dvb.c | 40 +++++++++++++++++------------------ 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/media/video/cx18/Kconfig b/drivers/media/video/cx18/Kconfig index 35a55998a8d3..5f942690570c 100644 --- a/drivers/media/video/cx18/Kconfig +++ b/drivers/media/video/cx18/Kconfig @@ -11,6 +11,7 @@ config VIDEO_CX18 select VIDEO_CX2341X select VIDEO_CS5345 select DVB_S5H1409 + select MEDIA_TUNER_MXL5005S ---help--- This is a video4linux driver for Conexant cx23418 based PCI combo video recorder devices. diff --git a/drivers/media/video/cx18/cx18-cards.c b/drivers/media/video/cx18/cx18-cards.c index f5e3ba1f5354..bf6f7edca887 100644 --- a/drivers/media/video/cx18/cx18-cards.c +++ b/drivers/media/video/cx18/cx18-cards.c @@ -51,7 +51,8 @@ static const struct cx18_card cx18_card_hvr1600_esmt = { .v4l2_capabilities = CX18_CAP_ENCODER, .hw_audio_ctrl = CX18_HW_CX23418, .hw_muxer = CX18_HW_CS5345, - .hw_all = CX18_HW_TVEEPROM | CX18_HW_TUNER | CX18_HW_CS5345, + .hw_all = CX18_HW_TVEEPROM | CX18_HW_TUNER | CX18_HW_CS5345 + | CX18_HW_DVB, .video_inputs = { { CX18_CARD_INPUT_VID_TUNER, 0, CX23418_COMPOSITE7 }, { CX18_CARD_INPUT_SVIDEO1, 1, CX23418_SVIDEO1 }, diff --git a/drivers/media/video/cx18/cx18-dvb.c b/drivers/media/video/cx18/cx18-dvb.c index 65efe69d939a..c9744173f969 100644 --- a/drivers/media/video/cx18/cx18-dvb.c +++ b/drivers/media/video/cx18/cx18-dvb.c @@ -24,25 +24,27 @@ #include "cx18-streams.h" #include "cx18-cards.h" #include "s5h1409.h" - -/* Wait until the MXL500X driver is merged */ -#ifdef HAVE_MXL500X -#include "mxl500x.h" -#endif +#include "mxl5005s.h" DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); #define CX18_REG_DMUX_NUM_PORT_0_CONTROL 0xd5a000 -#ifdef HAVE_MXL500X -static struct mxl500x_config hauppauge_hvr1600_tuner = { - .delsys = MXL500x_MODE_ATSC, - .octf = MXL500x_OCTF_CH, - .xtal_freq = 16000000, - .iflo_freq = 5380000, - .ref_freq = 322800000, - .rssi_ena = MXL_RSSI_ENABLE, - .addr = 0xC6 >> 1, +static struct mxl5005s_config hauppauge_hvr1600_tuner = { + .i2c_address = 0xC6 >> 1, + .if_freq = IF_FREQ_5380000HZ, + .xtal_freq = CRYSTAL_FREQ_16000000HZ, + .agc_mode = MXL_SINGLE_AGC, + .tracking_filter = MXL_TF_C_H, + .rssi_enable = MXL_RSSI_ENABLE, + .cap_select = MXL_CAP_SEL_ENABLE, + .div_out = MXL_DIV_OUT_4, + .clock_out = MXL_CLOCK_OUT_DISABLE, + .output_load = MXL5005S_IF_OUTPUT_LOAD_200_OHM, + .top = MXL5005S_TOP_25P2, + .mod_mode = MXL_DIGITAL_MODE, + .if_mode = MXL_ZERO_IF, + .AgcMasterByte = 0x00, }; static struct s5h1409_config hauppauge_hvr1600_config = { @@ -55,7 +57,6 @@ static struct s5h1409_config hauppauge_hvr1600_config = { .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK }; -#endif static int dvb_register(struct cx18_stream *stream); @@ -252,21 +253,18 @@ static int dvb_register(struct cx18_stream *stream) int ret = 0; switch (cx->card->type) { -/* Wait until the MXL500X driver is merged */ -#ifdef HAVE_MXL500X case CX18_CARD_HVR_1600_ESMT: case CX18_CARD_HVR_1600_SAMSUNG: dvb->fe = dvb_attach(s5h1409_attach, &hauppauge_hvr1600_config, &cx->i2c_adap[0]); if (dvb->fe != NULL) { - dvb_attach(mxl500x_attach, dvb->fe, - &hauppauge_hvr1600_tuner, - &cx->i2c_adap[0]); + dvb_attach(mxl5005s_attach, dvb->fe, + &cx->i2c_adap[0], + &hauppauge_hvr1600_tuner); ret = 0; } break; -#endif default: /* No Digital Tv Support */ break; -- cgit v1.2.3 From c1d6861b5178c184d78ae5f239cbaa9c2c63dd72 Mon Sep 17 00:00:00 2001 From: Hartmut Hackmann Date: Thu, 8 May 2008 22:57:20 -0300 Subject: V4L/DVB (7880): saa7134: remove explicit GPIO initialization This causes a problem with the audio mute on some cards and is done implictly in the audio initialization code. Signed-off-by: Hartmut Hackmann Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/saa7134/saa7134-core.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/media/video/saa7134/saa7134-core.c b/drivers/media/video/saa7134/saa7134-core.c index eec127864fe3..d9ad2f8b4234 100644 --- a/drivers/media/video/saa7134/saa7134-core.c +++ b/drivers/media/video/saa7134/saa7134-core.c @@ -1065,11 +1065,6 @@ static int __devinit saa7134_initdev(struct pci_dev *pci_dev, if (TUNER_ABSENT != dev->tuner_type) saa7134_i2c_call_clients(dev, TUNER_SET_STANDBY, NULL); - if (card(dev).gpiomask != 0) { - mask = card(dev).gpiomask; - saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, mask, mask); - saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, mask, 0); - } return 0; fail4: -- cgit v1.2.3 From 6db6ae2165863e26b7f41af54a8cf1ef9051a608 Mon Sep 17 00:00:00 2001 From: Hartmut Hackmann Date: Mon, 12 May 2008 20:34:02 -0300 Subject: V4L/DVB (7881): saa7134: fixed a compile warning in saa7134-core.c patch 779169257208 made the variable mask unnecessary. This patch just removes the declaration. Signed-off-by: Hartmut Hackmann Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/saa7134/saa7134-core.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/media/video/saa7134/saa7134-core.c b/drivers/media/video/saa7134/saa7134-core.c index d9ad2f8b4234..2c19cd0113c8 100644 --- a/drivers/media/video/saa7134/saa7134-core.c +++ b/drivers/media/video/saa7134/saa7134-core.c @@ -864,7 +864,6 @@ static int __devinit saa7134_initdev(struct pci_dev *pci_dev, struct saa7134_dev *dev; struct saa7134_mpeg_ops *mops; int err; - int mask; if (saa7134_devcount == SAA7134_MAXBOARDS) return -ENOMEM; -- cgit v1.2.3 From 9dcbf35afb7359466efdf7fb81ee32f3ae2d56a3 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 12 May 2008 13:57:18 -0300 Subject: V4L/DVB (7887): cx18: fix Compro H900 analog support. Tuner, S-Video and Composite are all working for the Compro H900. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/cx18/cx18-cards.c | 12 +++++---- drivers/media/video/cx18/cx18-cards.h | 5 ++-- drivers/media/video/cx18/cx18-gpio.c | 47 +++++++++++++++++++++++++++-------- 3 files changed, 46 insertions(+), 18 deletions(-) diff --git a/drivers/media/video/cx18/cx18-cards.c b/drivers/media/video/cx18/cx18-cards.c index bf6f7edca887..0f2bfb4ba844 100644 --- a/drivers/media/video/cx18/cx18-cards.c +++ b/drivers/media/video/cx18/cx18-cards.c @@ -135,14 +135,15 @@ static const struct cx18_card_pci_info cx18_pci_h900[] = { static const struct cx18_card cx18_card_h900 = { .type = CX18_CARD_COMPRO_H900, .name = "Compro VideoMate H900", - .comment = "Not yet supported!\n", - .v4l2_capabilities = 0, + .comment = "DVB & VBI are not yet supported\n", + .v4l2_capabilities = CX18_CAP_ENCODER, .hw_audio_ctrl = CX18_HW_CX23418, .hw_all = CX18_HW_TUNER, .video_inputs = { - { CX18_CARD_INPUT_VID_TUNER, 0, CX23418_COMPOSITE7 }, - { CX18_CARD_INPUT_SVIDEO1, 1, CX23418_SVIDEO1 }, - { CX18_CARD_INPUT_COMPOSITE1, 1, CX23418_COMPOSITE3 }, + { CX18_CARD_INPUT_VID_TUNER, 0, CX23418_COMPOSITE2 }, + { CX18_CARD_INPUT_SVIDEO1, 1, + CX23418_SVIDEO_LUMA3 | CX23418_SVIDEO_CHROMA4 }, + { CX18_CARD_INPUT_COMPOSITE1, 1, CX23418_COMPOSITE1 }, }, .audio_inputs = { { CX18_CARD_INPUT_AUD_TUNER, @@ -164,6 +165,7 @@ static const struct cx18_card cx18_card_h900 = { .tune_lane = 0, .initial_emrs = 0, }, + .xceive_pin = 15, .pci_list = cx18_pci_h900, .i2c = &cx18_i2c_std, }; diff --git a/drivers/media/video/cx18/cx18-cards.h b/drivers/media/video/cx18/cx18-cards.h index bca249bdd337..bccb67f0db16 100644 --- a/drivers/media/video/cx18/cx18-cards.h +++ b/drivers/media/video/cx18/cx18-cards.h @@ -114,8 +114,8 @@ struct cx18_card_pci_info { /* The mask is the set of bits used by the operation */ struct cx18_gpio_init { /* set initial GPIO DIR and OUT values */ - u16 direction; /* DIR setting. Leave to 0 if no init is needed */ - u16 initial_value; + u32 direction; /* DIR setting. Leave to 0 if no init is needed */ + u32 initial_value; }; struct cx18_card_tuner { @@ -153,6 +153,7 @@ struct cx18_card { struct cx18_card_audio_input radio_input; /* GPIO card-specific settings */ + u8 xceive_pin; /* XCeive tuner GPIO reset pin */ struct cx18_gpio_init gpio_init; struct cx18_card_tuner tuners[CX18_CARD_MAX_TUNERS]; diff --git a/drivers/media/video/cx18/cx18-gpio.c b/drivers/media/video/cx18/cx18-gpio.c index 19253e6b8673..bb8bc86086d0 100644 --- a/drivers/media/video/cx18/cx18-gpio.c +++ b/drivers/media/video/cx18/cx18-gpio.c @@ -35,6 +35,9 @@ #define CX18_REG_GPIO_OUT2 0xc78104 #define CX18_REG_GPIO_DIR2 0xc7810c +static u32 gpio_dir; +static u32 gpio_val; + /* * HVR-1600 GPIO pins, courtesy of Hauppauge: * @@ -44,31 +47,53 @@ * gpio13: cs5345 reset pin */ +static void gpio_write(struct cx18 *cx) +{ + write_reg((gpio_dir & 0xffff) << 16, CX18_REG_GPIO_DIR1); + write_reg(((gpio_dir & 0xffff) << 16) | (gpio_val & 0xffff), + CX18_REG_GPIO_OUT1); + write_reg(gpio_dir & 0xffff0000, CX18_REG_GPIO_DIR2); + write_reg((gpio_dir & 0xffff0000) | ((gpio_val & 0xffff0000) >> 16), + CX18_REG_GPIO_OUT2); +} + void cx18_gpio_init(struct cx18 *cx) { - if (cx->card->gpio_init.direction == 0) + gpio_dir = cx->card->gpio_init.direction; + gpio_val = cx->card->gpio_init.initial_value; + + if (gpio_dir == 0) return; - CX18_DEBUG_INFO("GPIO initial dir: %08x out: %08x\n", - read_reg(CX18_REG_GPIO_DIR1), read_reg(CX18_REG_GPIO_OUT1)); + gpio_dir |= 1 << cx->card->xceive_pin; + gpio_val |= 1 << cx->card->xceive_pin; - /* init output data then direction */ - write_reg(cx->card->gpio_init.direction << 16, CX18_REG_GPIO_DIR1); - write_reg(0, CX18_REG_GPIO_DIR2); - write_reg((cx->card->gpio_init.direction << 16) | - cx->card->gpio_init.initial_value, CX18_REG_GPIO_OUT1); - write_reg(0, CX18_REG_GPIO_OUT2); + CX18_DEBUG_INFO("GPIO initial dir: %08x/%08x out: %08x/%08x\n", + read_reg(CX18_REG_GPIO_DIR1), read_reg(CX18_REG_GPIO_DIR2), + read_reg(CX18_REG_GPIO_OUT1), read_reg(CX18_REG_GPIO_OUT2)); + + gpio_write(cx); } /* Xceive tuner reset function */ int cx18_reset_tuner_gpio(void *dev, int cmd, int value) { struct i2c_algo_bit_data *algo = dev; - struct cx18 *cx = algo->data; -/* int curdir, curout;*/ + struct cx18_i2c_algo_callback_data *cb_data = algo->data; + struct cx18 *cx = cb_data->cx; if (cmd != XC2028_TUNER_RESET) return 0; CX18_DEBUG_INFO("Resetting tuner\n"); + + gpio_dir |= 1 << cx->card->xceive_pin; + gpio_val &= ~(1 << cx->card->xceive_pin); + + gpio_write(cx); + schedule_timeout_interruptible(msecs_to_jiffies(1)); + + gpio_val |= 1 << cx->card->xceive_pin; + gpio_write(cx); + schedule_timeout_interruptible(msecs_to_jiffies(1)); return 0; } -- cgit v1.2.3 From 6b13cf164958a18436075fdae31f8bd9442353fa Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 12 May 2008 14:00:33 -0300 Subject: V4L/DVB (7888): cx18: minor card definition updates. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/cx18/cx18-cards.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/media/video/cx18/cx18-cards.c b/drivers/media/video/cx18/cx18-cards.c index 0f2bfb4ba844..18489cce18d8 100644 --- a/drivers/media/video/cx18/cx18-cards.c +++ b/drivers/media/video/cx18/cx18-cards.c @@ -47,12 +47,12 @@ static struct cx18_card_tuner_i2c cx18_i2c_std = { static const struct cx18_card cx18_card_hvr1600_esmt = { .type = CX18_CARD_HVR_1600_ESMT, .name = "Hauppauge HVR-1600", - .comment = "DVB & VBI are not yet supported\n", + .comment = "VBI is not yet supported\n", .v4l2_capabilities = CX18_CAP_ENCODER, .hw_audio_ctrl = CX18_HW_CX23418, .hw_muxer = CX18_HW_CS5345, - .hw_all = CX18_HW_TVEEPROM | CX18_HW_TUNER | CX18_HW_CS5345 - | CX18_HW_DVB, + .hw_all = CX18_HW_TVEEPROM | CX18_HW_TUNER | + CX18_HW_CS5345 | CX18_HW_DVB, .video_inputs = { { CX18_CARD_INPUT_VID_TUNER, 0, CX23418_COMPOSITE7 }, { CX18_CARD_INPUT_SVIDEO1, 1, CX23418_SVIDEO1 }, @@ -203,8 +203,6 @@ static const struct cx18_card cx18_card_mpc718 = { /* XC3028 tuner */ { .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 }, }, - /* tuner reset */ - .gpio_init = { .direction = 0x1000, .initial_value = 0x1000 }, .ddr = { /* Probably Samsung K4D263238G-VC33 memory */ .chip_config = 0x003, @@ -214,6 +212,7 @@ static const struct cx18_card cx18_card_mpc718 = { .tune_lane = 0, .initial_emrs = 2, }, + .xceive_pin = 15, .pci_list = cx18_pci_mpc718, .i2c = &cx18_i2c_std, }; -- cgit v1.2.3 From 1d081601315f5c9b9537b702bcb2c8d96fc089ef Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 12 May 2008 14:45:19 -0300 Subject: V4L/DVB (7889): cx18: improve HVR-1600 detection. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/cx18/cx18-cards.c | 5 +++-- drivers/media/video/cx18/cx18-driver.c | 8 ++++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/media/video/cx18/cx18-cards.c b/drivers/media/video/cx18/cx18-cards.c index 18489cce18d8..553adbf2cd44 100644 --- a/drivers/media/video/cx18/cx18-cards.c +++ b/drivers/media/video/cx18/cx18-cards.c @@ -87,11 +87,12 @@ static const struct cx18_card cx18_card_hvr1600_esmt = { static const struct cx18_card cx18_card_hvr1600_samsung = { .type = CX18_CARD_HVR_1600_SAMSUNG, .name = "Hauppauge HVR-1600 (Preproduction)", - .comment = "DVB & VBI are not yet supported\n", + .comment = "VBI is not yet supported\n", .v4l2_capabilities = CX18_CAP_ENCODER, .hw_audio_ctrl = CX18_HW_CX23418, .hw_muxer = CX18_HW_CS5345, - .hw_all = CX18_HW_TVEEPROM | CX18_HW_TUNER | CX18_HW_CS5345, + .hw_all = CX18_HW_TVEEPROM | CX18_HW_TUNER | + CX18_HW_CS5345 | CX18_HW_DVB, .video_inputs = { { CX18_CARD_INPUT_VID_TUNER, 0, CX23418_COMPOSITE7 }, { CX18_CARD_INPUT_SVIDEO1, 1, CX23418_SVIDEO1 }, diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c index 3e9979eff3e0..98e1bddc290b 100644 --- a/drivers/media/video/cx18/cx18-driver.c +++ b/drivers/media/video/cx18/cx18-driver.c @@ -210,13 +210,13 @@ static void cx18_process_eeprom(struct cx18 *cx) /* Many thanks to Steven Toth from Hauppauge for providing the model numbers */ + /* Note: the Samsung memory models cannot be reliably determined + from the model number. Use the cardtype module option if you + have one of these preproduction models. */ switch (tv.model) { - case 74000 ... 74099: + case 74000 ... 74999: cx->card = cx18_get_card(CX18_CARD_HVR_1600_ESMT); break; - case 74700 ... 74799: - cx->card = cx18_get_card(CX18_CARD_HVR_1600_SAMSUNG); - break; case 0: CX18_ERR("Invalid EEPROM\n"); return; -- cgit v1.2.3 From cba627a51a26eaed3526c423f5fd0410dd721ae2 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 12 May 2008 14:48:26 -0300 Subject: V4L/DVB (7890): cx18: removed bogus and confusing conditional Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/cx18/cx18-driver.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c index 98e1bddc290b..0dd4e0529970 100644 --- a/drivers/media/video/cx18/cx18-driver.c +++ b/drivers/media/video/cx18/cx18-driver.c @@ -904,8 +904,7 @@ static void cx18_remove(struct pci_dev *pci_dev) free_irq(cx->dev->irq, (void *)cx); - if (cx->dev) - cx18_iounmap(cx); + cx18_iounmap(cx); release_mem_region(cx->base_addr, CX18_MEM_SIZE); -- cgit v1.2.3 From 07c87a833e9ef92280ed24ab85cd4eb49cbca9c0 Mon Sep 17 00:00:00 2001 From: Andy Walls Date: Mon, 12 May 2008 15:01:27 -0300 Subject: V4L/DVB (7891): cx18/ivtv: fix open() kernel oops Upon error conditions in cx18/ivtv_probe(), the code at the 'err:' label leaves a NULL entry in cx18/ivtv_cards[]. This can cause a NULL pointer de-reference in cx18/ivtv_v4l2_open() which is fixed by this patch. Signed-off-by: Andy Walls Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/cx18/cx18-fileops.c | 2 ++ drivers/media/video/ivtv/ivtv-fileops.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/media/video/cx18/cx18-fileops.c b/drivers/media/video/cx18/cx18-fileops.c index 91eff6e671a7..0b3141db174b 100644 --- a/drivers/media/video/cx18/cx18-fileops.c +++ b/drivers/media/video/cx18/cx18-fileops.c @@ -662,6 +662,8 @@ int cx18_v4l2_open(struct inode *inode, struct file *filp) for (x = 0; cx == NULL && x < cx18_cards_active; x++) { /* find out which stream this open was on */ for (y = 0; y < CX18_MAX_STREAMS; y++) { + if (cx18_cards[x] == NULL) + continue; s = &cx18_cards[x]->streams[y]; if (s->v4l2dev && s->v4l2dev->minor == minor) { cx = cx18_cards[x]; diff --git a/drivers/media/video/ivtv/ivtv-fileops.c b/drivers/media/video/ivtv/ivtv-fileops.c index 2b74b0ab1477..f2fa434b677b 100644 --- a/drivers/media/video/ivtv/ivtv-fileops.c +++ b/drivers/media/video/ivtv/ivtv-fileops.c @@ -987,6 +987,8 @@ int ivtv_v4l2_open(struct inode *inode, struct file *filp) /* Find which card this open was on */ spin_lock(&ivtv_cards_lock); for (x = 0; itv == NULL && x < ivtv_cards_active; x++) { + if (ivtv_cards[x] == NULL) + continue; /* find out which stream this open was on */ for (y = 0; y < IVTV_MAX_STREAMS; y++) { s = &ivtv_cards[x]->streams[y]; -- cgit v1.2.3 From 48723543aff1f46091840222490ded5fe09c0e37 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sat, 10 May 2008 14:34:09 -0300 Subject: V4L/DVB (7893): xc5000: bug-fix: allow multiple devices in a single system The current code passes a context pointer in the xc5000_config struct. This context pointer is used in the tuner_callback function, used to reset the device after firmware download. The xc5000_config struct is a static structure, whose .priv member was being assigned before calling xc5000_attach(). If there are more than one of the same device type installed on a single system, the last one to assign xc5000_config.priv will "win", and all others will cease to function properly. This patch passes the context pointer in xc5000_attach() rather that storing it within the static struct xc5000_config. Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/xc5000.c | 9 +++++---- drivers/media/common/tuners/xc5000.h | 22 ++++++++++++---------- drivers/media/common/tuners/xc5000_priv.h | 2 ++ drivers/media/video/au0828/au0828-dvb.c | 6 ++---- drivers/media/video/cx23885/cx23885-dvb.c | 6 ++---- drivers/media/video/cx88/cx88-dvb.c | 10 ++++------ drivers/media/video/tuner-core.c | 4 ++-- 7 files changed, 29 insertions(+), 30 deletions(-) diff --git a/drivers/media/common/tuners/xc5000.c b/drivers/media/common/tuners/xc5000.c index 43d35bdb221f..ceae6db901ec 100644 --- a/drivers/media/common/tuners/xc5000.c +++ b/drivers/media/common/tuners/xc5000.c @@ -212,7 +212,7 @@ static void xc5000_TunerReset(struct dvb_frontend *fe) dprintk(1, "%s()\n", __func__); if (priv->cfg->tuner_callback) { - ret = priv->cfg->tuner_callback(priv->cfg->priv, + ret = priv->cfg->tuner_callback(priv->devptr, XC5000_TUNER_RESET, 0); if (ret) printk(KERN_ERR "xc5000: reset failed\n"); @@ -900,9 +900,9 @@ static const struct dvb_tuner_ops xc5000_tuner_ops = { .get_status = xc5000_get_status }; -struct dvb_frontend * xc5000_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, - struct xc5000_config *cfg) +struct dvb_frontend *xc5000_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct xc5000_config *cfg, void *devptr) { struct xc5000_priv *priv = NULL; u16 id = 0; @@ -916,6 +916,7 @@ struct dvb_frontend * xc5000_attach(struct dvb_frontend *fe, priv->cfg = cfg; priv->bandwidth = BANDWIDTH_6_MHZ; priv->i2c = i2c; + priv->devptr = devptr; /* Check if firmware has been loaded. It is possible that another instance of the driver has loaded the firmware. diff --git a/drivers/media/common/tuners/xc5000.h b/drivers/media/common/tuners/xc5000.h index 0ee80f9d19b8..c910715addc9 100644 --- a/drivers/media/common/tuners/xc5000.h +++ b/drivers/media/common/tuners/xc5000.h @@ -31,29 +31,31 @@ struct xc5000_config { u8 i2c_address; u32 if_khz; - /* For each bridge framework, when it attaches either analog or digital, - * it has to store a reference back to its _core equivalent structure, - * so that it can service the hardware by steering gpio's etc. - * Each bridge implementation is different so cast priv accordingly. - * The xc5000 driver cares not for this value, other than ensuring - * it's passed back to a bridge during tuner_callback(). - */ - void *priv; int (*tuner_callback) (void *priv, int command, int arg); }; /* xc5000 callback command */ #define XC5000_TUNER_RESET 0 +/* For each bridge framework, when it attaches either analog or digital, + * it has to store a reference back to its _core equivalent structure, + * so that it can service the hardware by steering gpio's etc. + * Each bridge implementation is different so cast devptr accordingly. + * The xc5000 driver cares not for this value, other than ensuring + * it's passed back to a bridge during tuner_callback(). + */ + #if defined(CONFIG_MEDIA_TUNER_XC5000) || \ (defined(CONFIG_MEDIA_TUNER_XC5000_MODULE) && defined(MODULE)) extern struct dvb_frontend* xc5000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, - struct xc5000_config *cfg); + struct xc5000_config *cfg, + void *devptr); #else static inline struct dvb_frontend* xc5000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, - struct xc5000_config *cfg) + struct xc5000_config *cfg, + void *devptr) { printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); return NULL; diff --git a/drivers/media/common/tuners/xc5000_priv.h b/drivers/media/common/tuners/xc5000_priv.h index 13b2d19341da..ecebfe4745ad 100644 --- a/drivers/media/common/tuners/xc5000_priv.h +++ b/drivers/media/common/tuners/xc5000_priv.h @@ -31,6 +31,8 @@ struct xc5000_priv { u8 video_standard; u8 rf_mode; u8 fwloaded; + + void *devptr; }; #endif diff --git a/drivers/media/video/au0828/au0828-dvb.c b/drivers/media/video/au0828/au0828-dvb.c index 1371b4e4b5f1..c86a5f17eca8 100644 --- a/drivers/media/video/au0828/au0828-dvb.c +++ b/drivers/media/video/au0828/au0828-dvb.c @@ -337,12 +337,10 @@ int au0828_dvb_register(struct au0828_dev *dev) dvb->frontend = dvb_attach(au8522_attach, &hauppauge_hvr950q_config, &dev->i2c_adap); - if (dvb->frontend != NULL) { - hauppauge_hvr950q_tunerconfig.priv = dev; + if (dvb->frontend != NULL) dvb_attach(xc5000_attach, dvb->frontend, &dev->i2c_adap, - &hauppauge_hvr950q_tunerconfig); - } + &hauppauge_hvr950q_tunerconfig, dev); break; default: printk(KERN_WARNING "The frontend of your DVB/ATSC card " diff --git a/drivers/media/video/cx23885/cx23885-dvb.c b/drivers/media/video/cx23885/cx23885-dvb.c index 47e3f9e035f9..022aa391937a 100644 --- a/drivers/media/video/cx23885/cx23885-dvb.c +++ b/drivers/media/video/cx23885/cx23885-dvb.c @@ -384,12 +384,10 @@ static int dvb_register(struct cx23885_tsport *port) port->dvb.frontend = dvb_attach(s5h1409_attach, &hauppauge_hvr1500q_config, &dev->i2c_bus[0].i2c_adap); - if (port->dvb.frontend != NULL) { - hauppauge_hvr1500q_tunerconfig.priv = i2c_bus; + if (port->dvb.frontend != NULL) dvb_attach(xc5000_attach, port->dvb.frontend, &i2c_bus->i2c_adap, - &hauppauge_hvr1500q_tunerconfig); - } + &hauppauge_hvr1500q_tunerconfig, i2c_bus); break; case CX23885_BOARD_HAUPPAUGE_HVR1500: i2c_bus = &dev->i2c_bus[1]; diff --git a/drivers/media/video/cx88/cx88-dvb.c b/drivers/media/video/cx88/cx88-dvb.c index 75e2e58349ef..d96173ff1dba 100644 --- a/drivers/media/video/cx88/cx88-dvb.c +++ b/drivers/media/video/cx88/cx88-dvb.c @@ -816,11 +816,10 @@ static int dvb_register(struct cx8802_dev *dev) /* tuner_config.video_dev must point to * i2c_adap.algo_data */ - pinnacle_pctv_hd_800i_tuner_config.priv = - core->i2c_adap.algo_data; if (!dvb_attach(xc5000_attach, dev->dvb.frontend, &core->i2c_adap, - &pinnacle_pctv_hd_800i_tuner_config)) + &pinnacle_pctv_hd_800i_tuner_config, + core->i2c_adap.algo_data)) goto frontend_detach; } break; @@ -878,11 +877,10 @@ static int dvb_register(struct cx8802_dev *dev) /* tuner_config.video_dev must point to * i2c_adap.algo_data */ - dvico_fusionhdtv7_tuner_config.priv = - core->i2c_adap.algo_data; if (!dvb_attach(xc5000_attach, dev->dvb.frontend, &core->i2c_adap, - &dvico_fusionhdtv7_tuner_config)) + &dvico_fusionhdtv7_tuner_config, + core->i2c_adap.algo_data)) goto frontend_detach; } break; diff --git a/drivers/media/video/tuner-core.c b/drivers/media/video/tuner-core.c index 4ca686fad557..5a75788b92ae 100644 --- a/drivers/media/video/tuner-core.c +++ b/drivers/media/video/tuner-core.c @@ -448,10 +448,10 @@ static void set_type(struct i2c_client *c, unsigned int type, xc5000_cfg.i2c_address = t->i2c->addr; xc5000_cfg.if_khz = 5380; - xc5000_cfg.priv = c->adapter->algo_data; xc5000_cfg.tuner_callback = t->tuner_callback; if (!dvb_attach(xc5000_attach, - &t->fe, t->i2c->adapter, &xc5000_cfg)) + &t->fe, t->i2c->adapter, &xc5000_cfg, + c->adapter->algo_data)) goto attach_failed; xc_tuner_ops = &t->fe.ops.tuner_ops; -- cgit v1.2.3 From ee04e0faad386141f52dd812f220a2f0d128f1c6 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Tue, 13 May 2008 01:25:24 -0300 Subject: V4L/DVB (7895): tveeprom: update Hauppauge analog audio and video decoders Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/tveeprom.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/media/video/tveeprom.c b/drivers/media/video/tveeprom.c index 3cf8a8e801e5..9da0e1807ffb 100644 --- a/drivers/media/video/tveeprom.c +++ b/drivers/media/video/tveeprom.c @@ -319,10 +319,12 @@ audioIC[] = {AUDIO_CHIP_INTERNAL, "CX25843"}, {AUDIO_CHIP_INTERNAL, "CX23418"}, {AUDIO_CHIP_INTERNAL, "CX23885"}, - /* 40-42 */ + /* 40-44 */ {AUDIO_CHIP_INTERNAL, "CX23888"}, {AUDIO_CHIP_INTERNAL, "SAA7131"}, {AUDIO_CHIP_INTERNAL, "CX23887"}, + {AUDIO_CHIP_INTERNAL, "SAA7164"}, + {AUDIO_CHIP_INTERNAL, "AU8522"}, }; /* This list is supplied by Hauppauge. Thanks! */ @@ -341,8 +343,10 @@ static const char *decoderIC[] = { "CX882", "TVP5150A", "CX25840", "CX25841", "CX25842", /* 30-34 */ "CX25843", "CX23418", "NEC61153", "CX23885", "CX23888", - /* 35-37 */ - "SAA7131", "CX25837", "CX23887" + /* 35-39 */ + "SAA7131", "CX25837", "CX23887", "CX23885A", "CX23887A", + /* 40-42 */ + "SAA7164", "CX23885B", "AU8522" }; static int hasRadioTuner(int tunerType) -- cgit v1.2.3 From 039d40019f3c5e26ea50ec5af4270189f63365e1 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 14 May 2008 04:36:22 -0300 Subject: V4L/DVB (7898): Fix VIDEO_MEDIA Kconfig logic If one of DVB_CORE or VIDEO_DEV is a module, the modules that can be used by both DVB and V4L cores should also be a module, otherwise, it will break its dependencies. This Kconfig logic implements the following: CONFIG_VIDEO_DEV CONFIG_DVB_CORE CONFIG_VIDEO_MEDIA N N N N M M N Y Y M N M M M M M Y M Y N Y Y M M Y Y Y Signed-off-by: Mauro Carvalho Chehab --- drivers/media/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/Kconfig b/drivers/media/Kconfig index ddf57e135c6c..7a7803b5d497 100644 --- a/drivers/media/Kconfig +++ b/drivers/media/Kconfig @@ -89,8 +89,7 @@ config DVB_CORE config VIDEO_MEDIA tristate - default DVB_CORE || VIDEO_DEV - depends on DVB_CORE || VIDEO_DEV + default (DVB_CORE && (VIDEO_DEV = n)) || (VIDEO_DEV && (DVB_CORE = n)) || (DVB_CORE && VIDEO_DEV) comment "Multimedia drivers" -- cgit v1.2.3 From 2ea336dc117098ef917ca9a19e911d15490587cc Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 14 May 2008 04:57:36 -0300 Subject: V4L/DVB (7899): Fixes a few remaining Kbuild issues at common/tuners - MEDIA_ATTACH now applies also for V4L; - select a FW_LOADER dependent driver should happen only if HOTPLUG; - apply the common tuner dependency to all tuners. This helps to avoid latter issues. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/common/tuners/Kconfig | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/media/common/tuners/Kconfig b/drivers/media/common/tuners/Kconfig index 394cb050bc77..d6206540476b 100644 --- a/drivers/media/common/tuners/Kconfig +++ b/drivers/media/common/tuners/Kconfig @@ -1,6 +1,6 @@ config MEDIA_ATTACH bool "Load and attach frontend and tuner driver modules as needed" - depends on DVB_CORE + depends on VIDEO_MEDIA depends on MODULES help Remove the static dependency of DVB card drivers on all @@ -22,7 +22,7 @@ config MEDIA_TUNER default VIDEO_MEDIA && I2C depends on VIDEO_MEDIA && I2C select MEDIA_TUNER_XC2028 if !MEDIA_TUNER_CUSTOMIZE && HOTPLUG - select MEDIA_TUNER_XC5000 if !MEDIA_TUNER_CUSTOMIZE + select MEDIA_TUNER_XC5000 if !MEDIA_TUNER_CUSTOMIZE && HOTPLUG select MEDIA_TUNER_MT20XX if !MEDIA_TUNER_CUSTOMIZE select MEDIA_TUNER_TDA8290 if !MEDIA_TUNER_CUSTOMIZE select MEDIA_TUNER_TEA5761 if !MEDIA_TUNER_CUSTOMIZE @@ -46,6 +46,7 @@ if MEDIA_TUNER_CUSTOMIZE config MEDIA_TUNER_SIMPLE tristate "Simple tuner support" + depends on VIDEO_MEDIA && I2C select MEDIA_TUNER_TDA9887 default m if MEDIA_TUNER_CUSTOMIZE help @@ -53,6 +54,7 @@ config MEDIA_TUNER_SIMPLE config MEDIA_TUNER_TDA8290 tristate "TDA 8290/8295 + 8275(a)/18271 tuner combo" + depends on VIDEO_MEDIA && I2C select MEDIA_TUNER_TDA827X select MEDIA_TUNER_TDA18271 default m if MEDIA_TUNER_CUSTOMIZE @@ -61,18 +63,21 @@ config MEDIA_TUNER_TDA8290 config MEDIA_TUNER_TDA827X tristate "Philips TDA827X silicon tuner" + depends on VIDEO_MEDIA && I2C default m if DVB_FE_CUSTOMISE help A DVB-T silicon tuner module. Say Y when you want to support this tuner. config MEDIA_TUNER_TDA18271 tristate "NXP TDA18271 silicon tuner" + depends on VIDEO_MEDIA && I2C default m if DVB_FE_CUSTOMISE help A silicon tuner module. Say Y when you want to support this tuner. config MEDIA_TUNER_TDA9887 tristate "TDA 9885/6/7 analog IF demodulator" + depends on VIDEO_MEDIA && I2C default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for Philips TDA9885/6/7 @@ -80,6 +85,7 @@ config MEDIA_TUNER_TDA9887 config MEDIA_TUNER_TEA5761 tristate "TEA 5761 radio tuner (EXPERIMENTAL)" + depends on VIDEO_MEDIA && I2C depends on EXPERIMENTAL default m if MEDIA_TUNER_CUSTOMIZE help @@ -87,42 +93,49 @@ config MEDIA_TUNER_TEA5761 config MEDIA_TUNER_TEA5767 tristate "TEA 5767 radio tuner" + depends on VIDEO_MEDIA && I2C default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the Philips TEA5767 radio tuner. config MEDIA_TUNER_MT20XX tristate "Microtune 2032 / 2050 tuners" + depends on VIDEO_MEDIA && I2C default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the MT2032 / MT2050 tuner. config MEDIA_TUNER_MT2060 tristate "Microtune MT2060 silicon IF tuner" + depends on VIDEO_MEDIA && I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon IF tuner MT2060 from Microtune. config MEDIA_TUNER_MT2266 tristate "Microtune MT2266 silicon tuner" + depends on VIDEO_MEDIA && I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon baseband tuner MT2266 from Microtune. config MEDIA_TUNER_MT2131 tristate "Microtune MT2131 silicon tuner" + depends on VIDEO_MEDIA && I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon baseband tuner MT2131 from Microtune. config MEDIA_TUNER_QT1010 tristate "Quantek QT1010 silicon tuner" + depends on VIDEO_MEDIA && I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon tuner QT1010 from Quantek. config MEDIA_TUNER_XC2028 tristate "XCeive xc2028/xc3028 tuners" + depends on VIDEO_MEDIA && I2C depends on HOTPLUG select FW_LOADER default m if MEDIA_TUNER_CUSTOMIZE @@ -131,6 +144,7 @@ config MEDIA_TUNER_XC2028 config MEDIA_TUNER_XC5000 tristate "Xceive XC5000 silicon tuner" + depends on VIDEO_MEDIA && I2C depends on HOTPLUG select FW_LOADER default m if DVB_FE_CUSTOMISE @@ -141,7 +155,7 @@ config MEDIA_TUNER_XC5000 config MEDIA_TUNER_MXL5005S tristate "MaxLinear MSL5005S silicon tuner" - depends on I2C + depends on VIDEO_MEDIA && I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon tuner MXL5005S from MaxLinear. -- cgit v1.2.3 From c2b7bbea83b239b1877f3cafe0cdcbbd08e65648 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 14 May 2008 05:08:19 -0300 Subject: V4L/DVB (7900): pvrusb: Fix Kconfig if DVB=m V4L_core=y As reported by Ingo Molnar: x86.git testing found the following build failure: drivers/built-in.o: In function `pvr2_dvb_feed_thread': pvrusb2-dvb.c:(.text+0x127e78): undefined reference to `dvb_dmx_swfilter' drivers/built-in.o: In function `pvr2_dvb_adapter_exit': pvrusb2-dvb.c:(.text+0x128357): undefined reference to `dvb_net_release' pvrusb2-dvb.c:(.text+0x12836f): undefined reference to `dvb_dmxdev_release' [...] with this config: CONFIG_VIDEO_PVRUSB2=y CONFIG_DVB_CORE=m i.e. pvrusb2 is built-in, dvb-core is modular. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/pvrusb2/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/video/pvrusb2/Kconfig b/drivers/media/video/pvrusb2/Kconfig index e2a7a508c2e9..4482b2c72ced 100644 --- a/drivers/media/video/pvrusb2/Kconfig +++ b/drivers/media/video/pvrusb2/Kconfig @@ -1,6 +1,7 @@ config VIDEO_PVRUSB2 tristate "Hauppauge WinTV-PVR USB2 support" depends on VIDEO_V4L2 && I2C + depends on VIDEO_MEDIA # Avoids pvrusb = Y / DVB = M depends on HOTPLUG # due to FW_LOADER select FW_LOADER select VIDEO_TUNER -- cgit v1.2.3