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path: root/drivers/clk/tegra
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2019-11-11clk: tegra: Share clk and rst register defines with Tegra clock driverSowjanya Komatineni2-45/+45
2019-11-11clk: tegra: Use fence_udelay() during PLLU initSowjanya Komatineni1-4/+4
2019-11-11clk: tegra: clk-dfll: Add suspend and resume supportSowjanya Komatineni3-0/+59
2019-11-11clk: tegra: clk-super: Add restore-context supportSowjanya Komatineni1-0/+27
2019-11-11clk: tegra: clk-super: Fix to enable PLLP branches to CPUSowjanya Komatineni4-1/+39
2019-11-11clk: tegra: periph: Add restore_context supportSowjanya Komatineni2-0/+37
2019-11-11clk: tegra: Support for OSC context save and restoreSowjanya Komatineni2-0/+16
2019-11-11clk: tegra: pll: Save and restore pll contextSowjanya Komatineni1-32/+54
2019-11-11clk: tegra: pllout: Save and restore pllout contextSowjanya Komatineni1-0/+9
2019-11-11clk: tegra: divider: Save and restore divider rateSowjanya Komatineni1-0/+11
2019-11-11clk: tegra: Reimplement SOR clocks on Tegra210Thierry Reding1-16/+55
2019-11-11clk: tegra: Reimplement SOR clock on Tegra124Thierry Reding1-9/+13
2019-11-11clk: tegra: Rename sor0_lvds to sor0_outThierry Reding3-8/+8
2019-11-11clk: tegra: Move SOR0 implementation to Tegra124Thierry Reding2-8/+49
2019-11-11clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRCThierry Reding2-2/+2
2019-11-11clk: tegra: Add Tegra20/30 EMC clock implementationDmitry Osipenko5-52/+339
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-8/+12
2019-06-28Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds1-0/+2
2019-06-25clk: tegra: Do not enable PLL_RE_VCO on Tegra210Thierry Reding1-1/+0
2019-06-25clk: tegra: Warn if an enabled PLL is in IDDQThierry Reding1-1/+5
2019-06-25clk: tegra: Do not warn unnecessarilyThierry Reding1-2/+3
2019-06-25clk: tegra210: fix PLLU and PLLU_OUT1JC Kuo1-4/+4
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-4/+1
2019-06-14clk: tegra210: Fix default rates for HDA clocksJon Hunter1-0/+2
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner1-9/+1
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner20-240/+20
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner5-49/+5
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd4-0/+4
2019-05-07Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and...Stephen Boyd4-40/+77
2019-05-07Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-...Stephen Boyd1-1/+1
2019-04-25clk: tegra: divider: Mark Memory Controller clock as read-onlyDmitry Osipenko1-1/+2
2019-04-25clk: tegra: emc: Replace BUG() with WARN_ONCE()Dmitry Osipenko1-1/+4
2019-04-25clk: tegra: emc: Fix EMC max-rate clampingDmitry Osipenko1-7/+10
2019-04-25clk: tegra: emc: Support multiple RAM codesDmitry Osipenko1-14/+23
2019-04-25clk: tegra: emc: Don't enable EMC clock manuallyDmitry Osipenko1-2/+0
2019-04-25clk: tegra124: Remove lock-enable bit from PLLMDmitry Osipenko1-2/+1
2019-04-25clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides dividerDmitry Osipenko1-2/+2
2019-04-23clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski2-5/+5
2019-04-19clk: tegra: Don't enable already enabled PLLsDmitry Osipenko1-13/+37
2019-04-11clk: tegra: Make tegra_clk_super_mux_ops staticYueHaibing1-1/+1
2019-03-14Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-9/+9
2019-03-08Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and ...Stephen Boyd1-9/+9
2019-02-22clk: tegra: dfll: Fix debugfs_simple_attr.cocci warningsYueHaibing1-9/+9
2019-02-18clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' staticWei Yongjun1-1/+1
2019-02-15Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Arnd Bergmann7-98/+913
2019-02-06clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210Peter De Schrijver2-1/+6
2019-02-06clk: tegra: dfll: add CVB tables for Tegra210Joseph Lo2-0/+427
2019-02-06clk: tegra: dfll: round down voltages based on alignmentJoseph Lo1-8/+13
2019-02-06clk: tegra: dfll: support PWM regulator controlJoseph Lo1-67/+377
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