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2012-11-21drm/i915: Add no-lvds quirk for Supermicro X7SPA-HChris Wilson1-0/+8
Reported-and-tested-by: Francois Tigeot <ftigeot@wolfpond.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55375 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit c31407a3672aaebb4acddf90944a114fa5c8af7b)
2012-11-21drm/i915: shut up spurious WARN in the gtt fault handlerDaniel Vetter1-1/+3
-ENOSPC can happen if userspace is being simplistic and tries to map a too big object. To aid further spurious WARN debugging, also print out the error code. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56017 Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit a7c2e1aad6c846f316641bbaa54cf999aeaa7ebc)
2012-11-21Revert "drm/i915: Try harder to complete DP training pattern 1"Daniel Vetter1-5/+10
This reverts commit 2477367083b3eaa97f87993ab26627a02f350551. If (for whatever reason) the DP sink device never asks for the maximal voltage level, we never don't hit the check that should bail us out after 5 retries of the same voltage. Which leads to an endless loop in the DP link training code, which hangs the driver. Now some more DP link training experiments on eDP panels seem to indicate that our training algorithm isn't robust enough anyway and needs more work. Hence for 3.7-fixes, let's just revert the regressing commit instead of trying to apply more duct-tape. Reported-by: Oleksij Rempel <bug-track@fisher-privat.net> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit b06fbda328490ec471e72659a9bf69f16a1c8dc9)
2012-11-21DRM/i915: Restore sdvo_flags after dtd->mode->dtd Roundrtrip.Egbert Eich1-0/+8
For TV and LVDS encoders intel_sdvo_set_input_timings_for_mode() is called to pass a mode to the sdvo chip and retrieve a dtd containing information needed to calculate the adjusted_mode which is done by intel_sdvo_get_dtd_from_mode(). To set this adjusted_mode as input mode for the sdvo chip, a dtd is recalculated using intel_sdvo_get_mode_from_dtd(). During this round trip the sdvo_flags contained in the dtd obtained from the hardware are lost. Since these flags cannot be ignored in all cases this patch preserves and restores them. This regression has been introduced in commit 6651819b4b4fc3caa6964c5d825eb4bb996f3905 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Sun Apr 1 19:16:18 2012 +0200 drm/i915: handle input/output sdvo timings separately in mode_set Signed-off-by: Egbert Eich <eich@suse.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit e751823da27d37d25e5543abef2dc031f8813bc8)
2012-11-21DRM/i915: Don't clone SDVO LVDS with analog.Egbert Eich1-4/+2
SDVO LVDS are not clonable as the input mode gets adjusted by the LVDS encoder. Signed-off-by: Egbert Eich <eich@suse.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit e3b86d6941c7e5f90be05d986fce1fcb40c68d6b)
2012-11-21DRM/i915: Add QUIRK_INVERT_BRIGHTNESS for NCR machines.Egbert Eich1-0/+32
NCR machines with LVDS panels using Intel chipsets need to have the QUIRK_INVERT_BRIGHTNESS bit set. Unfortunately NCR doesn't set a meaningful subvendor/subdevice ID, therefore we add a DMI dependent quirk list. Signed-off-by: Egbert Eich <eich@suse.de> [danvet: fixup whitespace fail.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 5f85f176c2f1c9d2a23f60ca0b99e4d0aa5a26a7)
2012-11-21DRM/i915: Don't delete DPLL Multiplier during DAC init.Egbert Eich1-14/+1
The DPLL multipiler is set up in intel_display.c:i9xx_update_pll() called from i9xx_crtc_mode_set(). There the DPLL multiplier is adjusted so that the SDVO gets a sufficient bus clock. When cloning a CRTC between an SDVO driven encoder and the standard DAC the DAC setup code reseted the multiplier value to 1 thus undoing the correct setup. There is no need to touch the multiplier in the DAC setup code: the correct value (i.e. 1 in case no SDVO encoder is used) is set by i9xx_update_pll() already. A comment at the code suggested that this code is a left over from the days when there was no setup for clone modes. Signed-off-by: Egbert Eich <eich@suse.de> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 6478d414fe4ee3114e760fb6d6df0f8e2f66186a)
2012-11-21Merged everything in drm-intel-next up to 6b8294a4d392c2cDaniel Vetter0-0/+0
... which is what's currently in drm-next. Next up is slurping in all the -fixes for 3.7.
2012-11-21drm/i915: Restore physical HWS_PGA after resumeChris Wilson2-43/+35
By always setting up the HWS register for both physical and virtual address variations during render ring we can reduce the number of different special cases that get set up at varying different times during module load. Fixes regression from commit c630119f43471a8ece356b01dabf07f944f453b3 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Wed Oct 17 11:32:57 2012 +0200 drm/i915: don't save/restore HWS_PGA reg for kms Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 6b8294a4d392c2c9f8867e8505511f3fc9419ba7)
2012-11-21drm/i915: Report amount of usable graphics memory in MiBChris Wilson1-1/+1
...rather than kilo-PTE. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Apply s/Usabel/usable/ bikeshed suggested by Ben Widawsky.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit d640c4b09a5d83a8167eb09d22bd89d9fa7e3b91)
2012-11-21drm/i915/i2c: Track users of GMBUS force-bitChris Wilson2-4/+7
This fixes a regression for SDVO from commit fbfcc4f3a0cf8bbde87646b74241faa8e37426bf Author: Jani Nikula <jani.nikula@intel.com> Date: Mon Oct 22 16:12:18 2012 +0300 drm/i915/sdvo: restore i2c adapter config on intel_sdvo_init() failures As SDVOB and SDVOC are multiplexed on the same pin, if a chipset does not have the second SDVO encoder, it will then remove the force-bit setting on the common i2c adapter during teardown. All subsequent attempts of trying to use GMBUS with SDVOB then fail. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> [danvet: fixup inversion in the debug printout, noticed by Jani Nikulai.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit f2ce9fafc1d443d49a0d1988f524a5da6e086e2c)
2012-11-21drm/i915: Allocate the proper size for contexts.Ben Widawsky1-1/+1
Whoops. This was fixed previously, but not sure how it got lost. It's not needed for -fixes or stable because at the moment drm_i915_file_private is way bigger than i915_hw_context (by 120 bytes on my 64b build). Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit f94982b0022f474d3c9285447d9a33b7a324e771)
2012-11-21drm/i915: Update load-detect failure paths for modeset-reworkChris Wilson1-7/+2
After the rework, intel_set_mode() became a little better behaved in restoring the current mode if we failed to apply the requested modeline. However, the failure path for load-detect would clobber the existing state, leading to an oops during BIOS takeover on older machines. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 0e8b3d3ea7c8f6e65c2c7220d64cbeb78023eff4)
2012-11-21drm/i915: Clear unused fields of mode for framebuffer creationChris Wilson1-1/+1
With the stricter checks introduced in commit ac911edae5960d7dccd9883f5fa5d25b591520de Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Wed Oct 31 17:50:19 2012 +0200 drm/i915: Check the framebuffer offset (and friends), it became especially prudent to make sure that the additional fields inside the mode were cleared before attempting to create a framebuffer. In particular, the fb created for load detection failed to do so and hence failed. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 0fed39bd1d85bfd0d454cb7ba2aedab2f15141d5)
2012-11-21drm/i915: Always calculate 8xx WM values based on a 32-bpp framebufferChris Wilson1-6/+11
The specs for gen2 say that the watermark values "should always be set assuming a 32bpp display mode, even though the display mode may be 15 or 16 bpp." Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit b9e0bda3cd325b55f336efb751736163f62abded)
2012-11-21drm/i915: Fix sparse warnings in from AGP kill codeBen Widawsky1-1/+1
Reported-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit ccdf56cdb2a4d6103eb6627494d6cd34edb1c2ea)
2012-11-21drm/i915: Missed lock change with rps lockBen Widawsky1-1/+3
Fixes a WARN_ON in igt/tests/debugfs_reader CC: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 44cbd33899302fc5294fc5fedfd0276348d796e4)
2012-11-21drm/i915: Move the remaining gtt codeBen Widawsky3-79/+76
It's pretty much all consolidated now that we've killed AGP. We can move the one outlier, and defines too. (Kill some unused defines in the process) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 26b1ff35c8c4888fb544f290e0fc64143f7dbe45)
2012-11-21drm/i915: flush system agent TLBs on SNBBen Widawsky2-2/+11
This allows us to map the PTEs WC. I've not done thorough testing or performance measurements with this patch, but it should be decent. This is based on a patch from Jesse with the original commit message > I've only lightly tested this so far, but the corruption seems to be > gone if I write the GFX_FLSH_CNTL reg after binding an object. This > register should control the TLB for the system agent, which is what CPU > mapped objects will go through. It has been updated for the new AGP-less code by me, and included with it is feedback from the original patch. v2: Updated to reflect paranoia on pte updates/register posting reads. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by [v1]: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 0f9b91c754b7244d3a7345df88c4384f0eb0dd17)
2012-11-21drm/i915: Kill off now unused gen6+ AGP codeBen Widawsky3-402/+11
v2: Accidently removed an ILK case in i9xx_setup (Nicely found by Chris) CC: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by [v1] : Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 009946f89b7795699848a922fc2f7804390017d9)
2012-11-21drm/i915: Calculate correct stolen size for GEN7+Ben Widawsky2-1/+15
This bug existed in the old code, but was easier to fix here in the rework. Unfortunately gen7 doesn't have a nice way to figure out the size and we must use a lookup table. As Jesse pointed out, there is some confusion in the docs about these definitions. We're picking the one which seems more accurate, but we really aren't certain. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 03752f5b7b77b95d83479885040950fba1250850)
2012-11-21drm/i915: Stop using AGP layer for GEN6+Ben Widawsky8-51/+257
As a quick hack we make the old intel_gtt structure mutable so we can fool a bunch of the existing code which depends on elements in that data structure. We can/should try to remove this in a subsequent patch. This should preserve the old gtt init behavior which upon writing these patches seems incorrect. The next patch will fix these things. The one exception is VLV which doesn't have the preserved flush control write behavior. Since we want to do that for all GEN6+ stuff, we'll handle that in a later patch. Mainstream VLV support doesn't actually exist yet anyway. v2: Update the comment to remove the "voodoo" Check that the last pte written matches what we readback v3: actually kill cache_level_to_agp_type since most of the flags will disappear in an upcoming patch v4: v3 was actually not what we wanted (Daniel) Make the ggtt bind assertions better and stricter (Chris) Fix some uncaught errors at gtt init (Chris) Some other random stuff that Chris wanted v5: check for i==0 in gen6_ggtt_bind_object to shut up gcc (Ben) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by [v4]: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Make the cache_level -> agp_flags conversion for pre-gen6 a tad more robust by mapping everything != CACHE_NONE to the cached agp flag - we have a 1:1 uncached mapping, but different modes of cacheable (at least on later generations). Suggested by Chris Wilson.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit e76e9aebcdbfebae8f4cd147e3c0f800d36e97f3)
2012-11-21drm/i915: drop the double-OP_STOREDW usage in blt_ring_flushDaniel Vetter1-1/+1
This has been introduced in "drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op". Reported-by: Fengguang Wu <fengguang.wu@intel.com> Reported-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit b3fcabb15bb83202fb5e4e5b296711b91c4942a3)
2012-11-21drm/i915: don't rewrite the GTT on resume v4Jesse Barnes2-11/+33
The BIOS shouldn't be touching this memory across suspend/resume, so just leave it alone. This saves us ~6ms on resume on my T420 (retested with write combined PTEs). v2: change gtt restore default on pre-gen4 (Chris) move needs_gtt_restore flag into dev_priv v3: make sure we restore GTT on resume from hibernate (Daniel) use opregion support as the cutoff for restore from resume (Chris) v4: use a better check for opregion (Chris) Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: Kill the needs_gtt_restore indirection and check directly for OpRegion. Also explain in a comment what's going on.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 1abd02e2dd7e0bd577000301fb2fd47780637387)
2012-11-21drm/i915: protect RPS/RC6 related accesses (including PCU) with a new mutexJesse Barnes6-44/+41
This allows the power related code to run independently of the rest of the pipeline, extending the resume and init time improvements into userspace, which would otherwise have been blocked on the struct mutex if we were doing PCU communication. v2: Also convert the locking for the rps sysfs interface. Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v1) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 4fc688ce79772496503d22263d61b071a8fb596e)
2012-11-21drm/i915: put ring frequency and turbo setup into a work queue v5Jesse Barnes3-2/+31
Communicating via the mailbox registers with the PCU can take quite awhile. And updating the ring frequency or enabling turbo is not something that needs to happen synchronously, so take it out of our init and resume paths to speed things up (~200ms on my T420). v2: add comment about why we use a work queue (Daniel) make sure work queue is idle on suspend (Daniel) use a delayed work queue since there's no hurry (Daniel) v3: make cleanup symmetric and just call cancel work directly (Daniel) v4: schedule the work using round_jiffies_up to batch work better (Chris) v5: fix the right schedule_delayed_work call (Chris) References: https://bugs.freedesktop.org/show_bug.cgi?id=54089 Signed-of-by: Jesse Barnes <jbarnes@virtuougseek.org> [danvet: bikeshed the placement of the new delayed work, move it to all the other gen6 power mgmt stuff.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 1a01ab3b2dc4394c46c4c3230805748f632f6f74)
2012-11-21drm/i915: don't block resume on fb console resume v2Jesse Barnes3-3/+34
The console lock can be contended, so rather than prevent other drivers after us from being held up, queue the console suspend into the global work queue that can happen anytime. I've measured this to take around 200ms on my T420. Combined with the ring freq/turbo change, we should save almost 1/2 a second on resume. v2: use console_trylock() to try to resume the console immediately (Chris) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: move dev_priv->console_resume_work next to the fbdev pointer.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 073f34d9d49bdbadbea8198ddc3fbb7e736a94dd)
2012-11-21drm/i915: extract l3_parity substruct from dev_privDaniel Vetter4-13/+17
Pretty astonishing how far apart these two members landed ... Especially since I've already removed almost 200 lines in between. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit a4da4fa4e55a8cea7fe603e7564e72db97b77a89)
2012-11-21drm/i915: move dri1 dungeon out of dev_privDaniel Vetter2-28/+31
Also, move dev_priv->counter there, it's only used in i915_dma.c And also move the dri1 dungeon at the end of dev_priv where no one cares about it. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 231f42a48f744c9a4f53752948fad2d793638937)
2012-11-21drm/i915: move pwrctx/renderctx to the other ilk power stateDaniel Vetter3-23/+23
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 3e37394802c1f2b0000da0a096455d2a3900df48)
2012-11-21drm/i915: move dev_priv->(rps|ips) out of lineDaniel Vetter1-31/+36
And give the structs slightly more generic names. I've decided to keep the short rps/ips prefix, since that's just easier and less churn. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit c85aa8855a4b2e0477fe6dfd0835270f2277aa8c)
2012-11-21drm/i915: move the suspend/resume register file out of dev_privDaniel Vetter3-491/+495
dev_priv has grown way too big, and grouping memebers into substructs and moving them out of line helps re-gain some overview. Unfortunatley I couldn't just call the substruct save and drop the prefix, since that will make most member names clash with registers #defines. Changes in i915_drv.h done by hand, everything else changed with s/\<save\([A-Z]*\)/regfile.save\1/ in vim. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit f4c956adc79f852e1f064679c2847b8ece2cd16f)
2012-11-21drm/i915: add clock gating regs to VLV offset check functionJesse Barnes1-0/+9
So we can write them properly. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 310c53a84f592d3e4a54dc26d512d1429695080b)
2012-11-21drm/i915: PIPE_CONTROL TLB invalidate requires CS stallJesse Barnes1-1/+1
"If ENABLED, PIPE_CONTROL command will flush the in flight data written out by render engine to Global Observation point on flush done. Also Requires stall bit ([20] of DW1) set." So set the stall bit to ensure proper invalidation. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 3ac7831314eba873d60b58718123c503f6961337)
2012-11-21drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3Jesse Barnes3-6/+26
So store into the scratch space of the HWS to make sure the invalidate occurs. v2: use GTT address space for store, clean up #defines (Chris) v3: use correct #define in blt ring flush (Chris) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> References: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1063252 Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 9a28977181724ebbd9bdc45291cf29da55a729ee)
2012-11-21drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLVJesse Barnes3-0/+17
Workaround for dual port PS dispatch on GT1. v2: pull in register definition & offset handling v3: use IVB GT1 macro to get the right regs (Ben) v4: add for VLV too (Ben) v5: don't read the reg, it's masked so we'll only enable the one extra bit (Chris) v6: use a _GT2 suffix for the second reg (Chris) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 12f3382bc0262e981a2e58aca900cbbdbbe66825)
2012-11-21drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLVJesse Barnes2-0/+9
This allows us to get the right vblank interrupt frequency. v2: pull in register definition Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 2d809570c8d72b9529ebb72c9d35fa0bf08c033c)
2012-11-21drm/i915: implement WaForceL3Serialization on VLV and IVBJesse Barnes1-0/+4
References: https://bugs.freedesktop.org/show_bug.cgi?id=50250 Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 5c9664d75a65adcdb9763a6df1da1d8d3f417c0c)
2012-11-21drm/i915: implement WaDisableDopClockGatingisable on VLV and IVBJesse Barnes4-1/+26
v2: use correct register v3: remove extra hunks, pull in register definitions & offset check directly v4: add GT1 vs GT2 distinction for IVB portion (Ben) References: https://bugs.freedesktop.org/show_bug.cgi?id=50233 Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 8ab4397640de51f4a93845b09270ad717244ccb3)
2012-11-21drm/i915: implement WaDisableL3CacheAging on VLVJesse Barnes2-1/+2
Needs to be set on every context restore as well, so set it as part of the initial state so we can save/restore it. Note this removes the IVB workaround value from VLV and uses the default value, just adding in the L3 cache aging disable bit, since the IVB value is wrong for VLV. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit d0cf5eadc0182806f8790369d03d93eef748a363)
2012-11-21drm/i915: fix Haswell FDI link disable pathPaulo Zanoni3-3/+30
This covers the "Disable FDI" section from the CRT mode set sequence. This disables the FDI receiver and also the FDI pll. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 1ad960f25ca419ca337284b369cf78d84b6a439e)
2012-11-21drm/i915: fix Haswell FDI link training codePaulo Zanoni3-65/+82
This commit makes hsw_fdi_link_train responsible for implementing everything described in the "Enable and train FDI" section from the Hawell CRT mode set sequence documentation. We completely rewrite hsw_fdi_link_train to match the documentation and we also call it in the right place. This patch was initially sent as a series of tiny patches fixing every little problem of the function, but since there were too many patches fixing the same function it got a little difficult to get the "big picture" of how the function would be in the end, so here we amended all the patches into a single big patch fixing the whole function. Problems we fixed: 1 - Train Haswell FDI at the right time. We need to train the FDI before enabling the pipes and planes, so we're moving the call from lpt_pch_enable to haswell_crtc_enable directly. We are also removing ironlake_fdi_pll_enable since the PLL enablement on Haswell is completely different and is also done during the link training steps. 2 - Use the right FDI_RX_CTL register on Haswell There is only one PCH transcoder, so it's always _FDI_RXA_CTL. Using "pipe" here is wrong. 3 - Don't rely on DDI_BUF_CTL previous values Just set the bits we want, everything else is zero. Also POSTING_READ the register before sleeping. 4 - Program the FDI RX TUSIZE register on hsw_fdi_link_train According to the mode set sequence documentation, this is the right place. According to the FDI_RX_TUSIZE register description, this is the value we should set. Also remove the code that sets this register from the old location: lpt_pch_enable. 5 - Properly program FDI_RX_MISC pwrdn lane values on HSW 6 - Wait only 35us for the FDI link training First we wait 30us for the FDI receiver lane calibration, then we wait 5us for the FDI auto training time. 7 - Remove an useless indentation level on hsw_fdi_link_train We already "break" when the link training succeeds. 8 - Disable FDI_RX_ENABLE, not FDI_RX_PLL_ENABLE When we fail the training. 9 - Change Haswell FDI link training error messages We shouldn't call DRM_ERROR when still looping through voltage levels since this is expected and not really a failure. So in this commit we adjust the error path to only DRM_ERROR when we really fail after trying everything. While at it, replace DRM_DEBUG_DRIVER with DRM_DEBUG_KMS since it's what we use everywhere. 10 - Try each voltage twice at hsw_fdi_link_train Now with Daniel Vetter's suggestion to use "/2" instead of ">>1". Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> [danvet: Applied tiny bikesheds: - mention in comment that we test each voltage/emphasis level twice - realing arguments of the only untouched reg write, it spilled over the 80 char limit ...] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 049456416f74a4a66d058cf9a46075f0051c6383)
2012-11-21drm/i915: remove HAS_eDP as unnecessary and inconsistent indirectionJani Nikula1-5/+5
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 547dc041df2f3f293ab832900d0e1f465ae29bbe)
2012-11-21drm/i915: set the correct number of FDI lanes on HaswellPaulo Zanoni1-2/+3
We had 2 places using X2 and one place using X1. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 349d7e5d7b27ee7b0b596ef1047e5c63908597fa)
2012-11-21drm/i915: kill pch_init_clock_gating indirectionDaniel Vetter2-41/+38
Now that we no longer pretend to have flexibility in matching any north display block with any pch, we can ditch this. v2: Fix the embarassing rebase fail that Paulo Zanoni spotted. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 3107bd48bfaf5ffe47c9c719c5f821c7cce0ca61)
2012-11-21drm/i915: implement WADP0ClockGatingDisableDaniel Vetter2-0/+10
Found in Bspec vol4h South Display Engine Registers [CPT, PPT], section "5.3.1 TRANS_CHICKEN_1—Transcoder Chicken Bits 1" v2: Make it compile. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit ce40141f55fa68f6d6e174fc86d727394897585b)
2012-11-21drm/i915: CPT+ pch transcoder workaroundDaniel Vetter3-17/+27
We need to set the timing override chicken bit after fdi link training has completed and before we enable the transcoder. We also have to clear that bit again after disabling the pch transcoder. See "Graphics BSpec: vol4g North Display Engine Registers [IVB], Display Mode Set Sequence" and "Graphics BSpec: vol4h South Display Engine Registers [CPT, PPT], South Display Engine Transcoder and FDI Control, Transcoder Debug and DFT, TRANS_CHICKEN_2" bit 31: "Workaround : Enable the override prior to enabling the transcoder. Disable the override after disabling the transcoder." While at it, use the _PIPE macro for the other TRANS_DP register. v2: Keep the w/a as-is, but kill the original (but wrongly placed) workaround introduced in commit 3bcf603f6d5d18bd9d076dc280de71f48add4101 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Wed Jul 27 11:51:40 2011 -0700 drm/i915: apply timing generator bug workaround on CPT and PPT and commit d4270e57efe9e2536798c59e1ed2fd0a1e5cdfcf Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Tue Oct 11 10:43:02 2011 -0700 drm/i915: export a CPT mode set verification function Note that this old code has unconditionally set the w/a, which might explain why fdi link training sometimes silently fails, and especially why the auto-train did not seem to work properly. v3: Paulo Zanoni pointed out that this workaround is also required on the LPT PCH. And Arthur Ranyan confirmed that this workaround is requierd for all ports on the pch, not just DP: The important part is that the bit is set whenever the pch transcoder is enabled, and that it is _not_ set while the fdi link is trained. It is also important that the pch transcoder is fully disabled, i.e. we have to wait for bit 30 to clear before clearing the w/a bit. Hence move to workaround into enable/disable_transcoder, where the pch transcoder gets enabled/disabled. v4: Whitespace changes dropped. v5: Don't run the w/a on IBX, we only need it on CPT/PPT and LPT. v6: - resolve conflicts with Paulo's big hsw vga rework - s/!IBX/CPT since hsw paths are now all separate, and Paulo's patch to implement the equivalent w/a for LPT is already merged. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Paulo Zanoni <przanoni@gmail.com> Cc: Arthur Ranyan <arthur.j.runyan@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v5) Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v5) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 23670b322c100c8fb2aa0c3d281ed10af428f664)
2012-11-21drm/i915: drop unnecessary check from fdi_link_train codeDaniel Vetter1-9/+5
They are all written for a specific north disaplay->pch combination. So stop pretending otherwise. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 8f5718a6d9a29bf1f51910c6b32bd0244f905303)
2012-11-21drm/i915: check whether the pch is the soulmate of the cpuDaniel Vetter1-0/+4
We don't really support fancy north display/pch combinations, so put a big yelling WARN_ON in there. It /should/ be impossible, but alas, the rumours don't stop (mostly due to really early silicon sometimes using older PCHs). v2: Fixup the logic fumble noticed by Paulo Zanoni. I should actually try to test run the patch next time around ... Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 7fcb83cde02da2f0c7d7eb8ba2c51df24495c0a8)
2012-11-21drm/i915: move panel connectors to the frontDaniel Vetter1-11/+7
This essentially reverts commit cb0953d734348e8862d6d7edc666cfb3bf6d8fae Author: Adam Jackson <ajax@redhat.com> Date: Fri Jul 16 14:46:29 2010 -0400 drm/i915: Initialize LVDS and eDP outputs before anything else simply because it doesn't scale: It misses SDVO and DVO panels, and now with DDI encoders on haswell this is becoming unmanageable. Instead we simply sort the connector list after everything is set up. Reviewed-by: Adam Jackson <ajax@redhat.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (cherry picked from commit 270b30420c5e0d5f779aa76882367f9265c5aa7d)
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