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authorShawn Lin <shawn.lin@rock-chips.com>2016-09-30 14:18:59 +0800
committerUlf Hansson <ulf.hansson@linaro.org>2016-10-10 14:01:15 +0200
commit4f25580fb84d934d7ecffa3c0aa8f10f7e23af92 (patch)
tree624c64cb0d179ff5ef5732ce4f7d58eaf4302b59 /mm/backing-dev.c
parent1720d3545b772c49b2975eeb3b8f4d3f56dc2085 (diff)
mmc: core: changes frequency to hs_max_dtr when selecting hs400es
Per JESD84-B51 P49, Host need to change frequency to <=52MHz after setting HS_TIMING to 0x1, and host may changes frequency to <= 200MHz after setting HS_TIMING to 0x3. That means the card expects the clock rate to increase from the current used f_init (which is less than 400KHz, but still being less than 52MHz) to 52MHz, otherwise we find some eMMC devices significantly report failure when sending status. Reported-by: Xiao Yao <xiaoyao@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'mm/backing-dev.c')
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