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authorTony Lindgren <tony@atomide.com>2017-12-15 09:41:23 -0800
committerTony Lindgren <tony@atomide.com>2017-12-21 07:28:54 -0800
commitc5a2de97fbd2979fab291fb048084d3fddd322dd (patch)
tree45dfca45e1e9c683c961cb20936d464a2380f673 /include/linux/platform_data/ti-sysc.h
parent566a9b05e1fa47dcfb93a4459145d0fdc06d3046 (diff)
bus: ti-sysc: Add parsing of module capabilities
We need to configure the interconnect target module based on the device three configuration. Let's also add a new quirk for SYSC_QUIRK_RESET_STATUS to indicate that the SYSCONFIG reset bit changes after the reset is done. Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'include/linux/platform_data/ti-sysc.h')
-rw-r--r--include/linux/platform_data/ti-sysc.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h
index 28e5a61d4abc..1be356330b96 100644
--- a/include/linux/platform_data/ti-sysc.h
+++ b/include/linux/platform_data/ti-sysc.h
@@ -41,6 +41,7 @@ struct sysc_regbits {
s8 emufree_shift;
};
+#define SYSC_QUIRK_RESET_STATUS BIT(7)
#define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6)
#define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5)
#define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4)
@@ -49,6 +50,8 @@ struct sysc_regbits {
#define SYSC_QUIRK_UNCACHED BIT(1)
#define SYSC_QUIRK_USE_CLOCKACT BIT(0)
+#define SYSC_NR_IDLEMODES 4
+
/**
* struct sysc_capabilities - capabilities for an interconnect target module
*
@@ -65,10 +68,17 @@ struct sysc_capabilities {
/**
* struct sysc_config - configuration for an interconnect target module
+ * @sysc_val: configured value for sysc register
+ * @midlemodes: bitmask of supported master idle modes
+ * @sidlemodes: bitmask of supported master idle modes
* @srst_udelay: optional delay needed after OCP soft reset
* @quirks: bitmask of enabled quirks
*/
struct sysc_config {
+ u32 sysc_val;
+ u32 syss_mask;
+ u8 midlemodes;
+ u8 sidlemodes;
u8 srst_udelay;
u32 quirks;
};