diff options
| author | Samuel Holland <samuel@sholland.org> | 2022-07-12 21:52:30 -0500 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2022-07-18 11:39:33 +0200 |
| commit | 88df36f2e6aa171a674715f8079d3b6ee4165ac3 (patch) | |
| tree | c806cf4695882ab96d2993823df21b9015730500 /drivers/pinctrl/sunxi/pinctrl-sunxi.h | |
| parent | fc153c8f283bf5925615195fc9d4056414d7b168 (diff) | |
pinctrl: sunxi: Support the 2.5V I/O bias mode
H616 and newer SoCs feature a 2.5V I/O bias mode in addition to the
1.8V and 3.3V modes. This mode is entered by selecting the 3.3V level
and disabling the "withstand function".
H616 supports this capability on its main PIO only. A100 supports this
capability on both its PIO and R-PIO.
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-4-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/sunxi/pinctrl-sunxi.h')
| -rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sunxi.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index a32bb5bcb754..0f1aab58650c 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -98,6 +98,7 @@ #define PINCTRL_SUN8I_V3S BIT(10) #define PIO_POW_MOD_SEL_REG 0x340 +#define PIO_POW_MOD_CTL_REG 0x344 enum sunxi_desc_bias_voltage { BIAS_VOLTAGE_NONE, @@ -111,6 +112,12 @@ enum sunxi_desc_bias_voltage { * register, as seen on H6 SoC, for example. */ BIAS_VOLTAGE_PIO_POW_MODE_SEL, + /* + * Bias voltage is set through PIO_POW_MOD_SEL_REG + * and PIO_POW_MOD_CTL_REG register, as seen on + * A100 and D1 SoC, for example. + */ + BIAS_VOLTAGE_PIO_POW_MODE_CTL, }; struct sunxi_desc_function { |