diff options
| author | Xing Zheng <zhengxing@rock-chips.com> | 2016-08-02 15:22:26 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-08-08 10:57:21 +0200 |
| commit | efc4204cf7b0792374676219fefc0651a9ca1e27 (patch) | |
| tree | 423ad3acb15f0ae58635870cc57841a551494d94 /drivers/clk/rockchip/clk-rk3399.c | |
| parent | 29b4817d4018df78086157ea3a55c1d9424a7cfc (diff) | |
clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMI
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3399.c')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3399.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index c109d80e7a8a..e4ca8a983d12 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -100,8 +100,10 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0), RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0), + RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0), RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0), + RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0), RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0), RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0), { /* sentinel */ }, |