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authorJames Morris <james.l.morris@oracle.com>2014-06-24 18:46:07 +1000
committerJames Morris <james.l.morris@oracle.com>2014-06-24 18:46:07 +1000
commitf01387d2693813eb5271a3448e6a082322c7d75d (patch)
treeb591ca73c85276bae53d7db57ff1565be45a29da /arch/hexagon/include/asm/io.h
parent92953ff38ba59b4f7b1a54ab28b84be35fafaecc (diff)
parent1860e379875dfe7271c649058aeddffe5afd9d0d (diff)
Merge commit 'v3.15' into next
Diffstat (limited to 'arch/hexagon/include/asm/io.h')
-rw-r--r--arch/hexagon/include/asm/io.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/hexagon/include/asm/io.h b/arch/hexagon/include/asm/io.h
index 1b7698e19139..70298996e9b2 100644
--- a/arch/hexagon/include/asm/io.h
+++ b/arch/hexagon/include/asm/io.h
@@ -189,6 +189,8 @@ static inline void writel(u32 data, volatile void __iomem *addr)
#define writew_relaxed __raw_writew
#define writel_relaxed __raw_writel
+#define mmiowb()
+
/*
* Need an mtype somewhere in here, for cache type deals?
* This is probably too long for an inline.