agp/intel: Experiment with a 855GM GWB bit

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

2 files changed, 29 insertions, 2 deletions

diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 010e3defd6c3..5fef204b54ae 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -128,6 +128,7 @@
 #define INTEL_GMCH_GMS_STOLEN_352M	(0xd << 4)
 
 #define I915_IFPADDR    0x60
+#define I830_HIC        0x70
 
 /* Intel 965G registers */
 #define I965_MSAC 0x62
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 356f73e0d17e..799ad17b70a1 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -21,6 +21,7 @@
 #include <linux/kernel.h>
 #include <linux/pagemap.h>
 #include <linux/agp_backend.h>
+#include <linux/delay.h>
 #include <asm/smp.h>
 #include "agp.h"
 #include "intel-agp.h"
@@ -61,6 +62,7 @@ struct intel_gtt_driver {
 static struct _intel_private {
 	struct intel_gtt base;
 	const struct intel_gtt_driver *driver;
+	unsigned int gmch_chip_id;
 	struct pci_dev *pcidev;	/* device one */
 	struct pci_dev *bridge_dev;
 	u8 __iomem *registers;
@@ -86,6 +88,7 @@ static struct _intel_private {
 #define IS_PINEVIEW	intel_private.driver->is_pineview
 #define IS_IRONLAKE	intel_private.driver->is_ironlake
 #define HAS_PGTBL_EN	intel_private.driver->has_pgtbl_enable
+#define IS_855GM	(intel_private.gmch_chip_id == PCI_DEVICE_ID_INTEL_82855GM_IG)
 
 int intel_gtt_map_memory(struct page **pages, unsigned int num_entries,
 			 struct scatterlist **sg_list, int *num_sg)
@@ -745,6 +748,24 @@ static void intel_i830_setup_flush(void)
 		i830_cleanup();
 }
 
+static void i855_chipset_flush(void)
+{
+	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
+
+	/* Now we've only seen documents for this magic bit on 855GM,
+	 * we hope it exists for the other gen2 chipsets...
+	 */
+	writel(readl(intel_private.registers+I830_HIC) | (1<<31),
+	       intel_private.registers+I830_HIC);
+
+	while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
+		if (time_after(jiffies, timeout))
+			break;
+
+		udelay(50);
+	}
+}
+
 /* The chipset_flush interface needs to get data that has already been
  * flushed out of the CPU all the way out to main memory, because the GPU
  * doesn't snoop those buffers.
@@ -757,10 +778,13 @@ static void intel_i830_setup_flush(void)
  */
 static void i830_chipset_flush(void)
 {
-	unsigned int *pg = intel_private.i8xx_flush_page;
+	unsigned int *pg;
 
-	memset(pg, 0, 1024);
+	if (IS_855GM)
+		return i855_chipset_flush();
 
+	pg = intel_private.i8xx_flush_page;
+	memset(pg, 0, 1024);
 	if (cpu_has_clflush)
 		clflush_cache_range(pg, 1024);
 	else if (wbinvd_on_all_cpus() != 0)
@@ -1456,6 +1480,8 @@ int intel_gmch_probe(struct pci_dev *pdev,
 		if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
 			intel_private.driver =
 				intel_gtt_chipsets[i].gtt_driver;
+			intel_private.gmch_chip_id =
+				intel_gtt_chipsets[i].gmch_chip_id;
 			break;
 		}
 	}