diff options
| author | Kukjin Kim <kgene.kim@samsung.com> | 2010-10-01 20:50:20 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-10-23 11:50:59 +0900 |
| commit | e27ecd7306992fbe58ab03f20aa3452a8b40499a (patch) | |
| tree | 8823d4aa7e17f9f1741a1673d20b919be590700a /arch/arm/mach-s5pc100/setup-ide.c | |
| parent | 54bce6c73dcd6d150d917e954154521de116e17b (diff) | |
ARM: S5PC100: 2nd Change to using s3c_gpio_cfgall_range()
This patch changes the code setting range of GPIO pins' configuration and
pull state to use the recently introduced s3c_gpio_cfgpin_range().
NOTE: This is for missed things from the previous patch.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pc100/setup-ide.c')
| -rw-r--r-- | arch/arm/mach-s5pc100/setup-ide.c | 42 |
1 files changed, 15 insertions, 27 deletions
diff --git a/arch/arm/mach-s5pc100/setup-ide.c b/arch/arm/mach-s5pc100/setup-ide.c index 83575671fb5..d8b0d0eac13 100644 --- a/arch/arm/mach-s5pc100/setup-ide.c +++ b/arch/arm/mach-s5pc100/setup-ide.c @@ -17,52 +17,40 @@ #include <mach/regs-clock.h> #include <plat/gpio-cfg.h> +static void s5pc100_ide_cfg_gpios(unsigned int base, unsigned int nr) +{ + s3c_gpio_cfgall_range(base, nr, S3C_GPIO_SFN(4), S3C_GPIO_PULL_NONE); + + for (; nr > 0; nr--, base++) + s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4); +} + void s5pc100_ide_setup_gpio(void) { u32 reg; - u32 gpio = 0; /* Independent CF interface, CF chip select configuration */ reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f); writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG); /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */ - for (gpio = S5PC100_GPJ0(0); gpio <= S5PC100_GPJ0(7); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } + s5pc100_ide_cfg_gpios(S5PC100_GPJ0(0), 8); /*CF_Data[0 - 7] */ - for (gpio = S5PC100_GPJ2(0); gpio <= S5PC100_GPJ2(7); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } + s5pc100_ide_cfg_gpios(S5PC100_GPJ2(0), 8); /* CF_Data[8 - 15] */ - for (gpio = S5PC100_GPJ3(0); gpio <= S5PC100_GPJ3(7); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } + s5pc100_ide_cfg_gpios(S5PC100_GPJ3(0), 8); /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */ - for (gpio = S5PC100_GPJ4(0); gpio <= S5PC100_GPJ4(3); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); - } + s5pc100_ide_cfg_gpios(S5PC100_GPJ4(0), 4); /* EBI_OE, EBI_WE */ - for (gpio = S5PC100_GPK0(6); gpio <= S5PC100_GPK0(7); gpio++) - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0)); + s3c_gpio_cfgpin_range(S5PC100_GPK0(6), 2, S3C_GPIO_SFN(0)); /* CF_OE, CF_WE */ - for (gpio = S5PC100_GPK1(6); gpio <= S5PC100_GPK1(7); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } + s3c_gpio_cfgall_range(S5PC100_GPK1(6), 8, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_NONE); /* CF_CD */ s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2)); |