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path: root/target-sparc/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2012-06-04target-sparc: Let cpu_sparc_init() return SPARCCPUAndreas Färber1-3/+14
2012-04-14Use uintptr_t for various op related functionsBlue Swirl1-1/+1
2012-04-07target-sparc: QOM'ify CPUAndreas Färber1-0/+1
2012-03-24target-sparc: Add compiler attribute to some functions which don't returnStefan Weil1-2/+3
2012-03-18Sparc: avoid AREG0 wrappers for memory access helpersBlue Swirl1-83/+2
2012-03-18Sparc: avoid AREG0 for memory access helpersBlue Swirl1-0/+82
2012-03-17sparc64: implement PCI and ISA irqsBlue Swirl1-0/+3
2012-03-17sparc: reset CPU state on resetBlue Swirl1-2/+3
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber1-1/+1
2012-03-14target-sparc: Don't overuse CPUStateAndreas Färber1-28/+28
2012-03-14target-sparc: Typedef struct CPUSPARCState earlyAndreas Färber1-2/+4
2011-10-26target-sparc: Change fpr representation to doubles.Richard Henderson1-3/+4
2011-10-26target-sparc: Pass float64 parameters instead of dt0/1 temporaries.Richard Henderson1-1/+0
2011-10-26Sparc: split MMU helpersBlue Swirl1-1/+1
2011-10-26Sparc: avoid AREG0 for softint op helpers and Leon cache controlBlue Swirl1-6/+25
2011-10-23Sparc: split CWP and PSTATE op helpersBlue Swirl1-1/+3
2011-10-23Sparc: split helper.cBlue Swirl1-1/+2
2011-09-10Gdbstub: Fix back-trace on SPARC32Fabien Chouteau1-0/+7
2011-08-07Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl1-1/+1
2011-07-21SPARC64: implement addtional MMU faults related to nonfaulting loadTsuneo Saito1-0/+4
2011-07-21SPARC64: split cpu_get_phys_page_debug() from cpu_get_phys_page_nofault()Tsuneo Saito1-0/+2
2011-07-21SPARC64: SFSR cleanup and fixTsuneo Saito1-0/+22
2011-07-21SPARC64: TTE bits cleanupTsuneo Saito1-0/+7
2011-07-20Fix unassigned memory access handlingBlue Swirl1-2/+2
2011-07-14Sparc: fix FPU and AM enable checks for translationBlue Swirl1-16/+33
2011-06-26Move cpu_has_work and cpu_pc_from_tb to cpu.hBlue Swirl1-0/+14
2011-06-26sparc: move do_interrupt to helper.cBlue Swirl1-0/+4
2011-06-26Sparc32: dummy implementation of MXCC MMU breakpoint registersBlue Swirl1-1/+3
2011-02-01SPARC: Fix Leon3 cache controlFabien Chouteau1-2/+6
2011-01-24SPARC: Add asr17 register supportFabien Chouteau1-0/+1
2011-01-24SPARC: Emulation of Leon3Fabien Chouteau1-14/+23
2010-12-19Sparc: implement monitor command 'info tlb'Blue Swirl1-1/+1
2010-12-04target-sparc: Use fprintf_function (format checking)Stefan Weil1-2/+2
2010-12-03target-sparc: remove unused functions cpu_lock(), cpu_unlock()Peter Maydell1-2/+0
2010-07-03remove exec-all.h inclusion from cpu.hPaolo Bonzini1-1/+0
2010-07-03move cpu_pc_from_tb to target-*/exec.hPaolo Bonzini1-6/+0
2010-05-22sparc64: fix mmu context at trap levels above zeroIgor V. Kovalenko1-4/+10
2010-05-22sparc64: fix pstate privilege bitsIgor V. Kovalenko1-18/+43
2010-05-16sparc64: fix TT_WOTHER valueIgor V. Kovalenko1-1/+1
2010-05-09sparc: Fix lazy flag calculation on interrupts, refactorBlue Swirl1-90/+12
2010-05-06sparc64: handle asi referencing nucleus and secondary MMU contextsIgor V. Kovalenko1-1/+12
2010-05-06sparc64: implement global translation table entries v1Igor V. Kovalenko1-0/+18
2010-04-17target-sparc: Fix TARGET_{PHYS,VIRT}_ADDR_SPACE_BITS.Richard Henderson1-6/+6
2010-03-12Target specific usermode cleanupPaul Brook1-0/+2
2010-03-12Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.Richard Henderson1-0/+8
2010-01-27sparc64: reimplement tick timers v4Igor V. Kovalenko1-6/+22
2010-01-27sparc64: correct write extra bits to cwpIgor V. Kovalenko1-1/+1
2010-01-08sparc64: interrupt trap handlingIgor V. Kovalenko1-0/+10
2010-01-08sparc64: move cpu_interrupts_enabled to cpu.hIgor V. Kovalenko1-0/+13
2010-01-08sparc64: add macros to deal with softint and timer interruptIgor V. Kovalenko1-0/+4
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