diff options
| -rw-r--r-- | target-unicore32/cpu.h | 24 | ||||
| -rw-r--r-- | target-unicore32/helper.c | 62 | ||||
| -rw-r--r-- | target-unicore32/op_helper.c | 8 | ||||
| -rw-r--r-- | target-unicore32/translate.c | 60 |
4 files changed, 77 insertions, 77 deletions
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index 923db052c..171f0a912 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -92,9 +92,9 @@ typedef struct CPUUniCore32State { #define UC32_EXCP_TRAP (ASR_MODE_TRAP) /* Return the current ASR value. */ -target_ulong cpu_asr_read(CPUState *env1); +target_ulong cpu_asr_read(CPUUniCore32State *env1); /* Set the ASR. Note that some bits of mask must be all-set or all-clear. */ -void cpu_asr_write(CPUState *env1, target_ulong val, target_ulong mask); +void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask); /* UniCore-F64 system registers. */ #define UC32_UCF64_FPSCR (31) @@ -128,10 +128,10 @@ void cpu_asr_write(CPUState *env1, target_ulong val, target_ulong mask); #define cpu_signal_handler uc32_cpu_signal_handler #define cpu_handle_mmu_fault uc32_cpu_handle_mmu_fault -CPUState *uc32_cpu_init(const char *cpu_model); -int uc32_cpu_exec(CPUState *s); +CPUUniCore32State *uc32_cpu_init(const char *cpu_model); +int uc32_cpu_exec(CPUUniCore32State *s); int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc); -int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw, +int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw, int mmu_idx); #define CPU_SAVE_VERSION 2 @@ -140,12 +140,12 @@ int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw, #define MMU_MODE0_SUFFIX _kernel #define MMU_MODE1_SUFFIX _user #define MMU_USER_IDX 1 -static inline int cpu_mmu_index(CPUState *env) +static inline int cpu_mmu_index(CPUUniCore32State *env) { return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0; } -static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) +static inline void cpu_clone_regs(CPUUniCore32State *env, target_ulong newsp) { if (newsp) { env->regs[29] = newsp; @@ -153,7 +153,7 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) env->regs[0] = 0; } -static inline void cpu_set_tls(CPUState *env, target_ulong newtls) +static inline void cpu_set_tls(CPUUniCore32State *env, target_ulong newtls) { env->regs[16] = newtls; } @@ -161,12 +161,12 @@ static inline void cpu_set_tls(CPUState *env, target_ulong newtls) #include "cpu-all.h" #include "exec-all.h" -static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) +static inline void cpu_pc_from_tb(CPUUniCore32State *env, TranslationBlock *tb) { env->regs[31] = tb->pc; } -static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, +static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc, target_ulong *cs_base, int *flags) { *pc = env->regs[31]; @@ -178,10 +178,10 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, } void uc32_translate_init(void); -void do_interrupt(CPUState *); +void do_interrupt(CPUUniCore32State *); void switch_mode(CPUUniCore32State *, int); -static inline bool cpu_has_work(CPUState *env) +static inline bool cpu_has_work(CPUUniCore32State *env) { return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c index ee7f82bdc..6af492daf 100644 --- a/target-unicore32/helper.c +++ b/target-unicore32/helper.c @@ -11,7 +11,7 @@ #include "helper.h" #include "host-utils.h" -static inline void set_feature(CPUState *env, int feature) +static inline void set_feature(CPUUniCore32State *env, int feature) { env->features |= feature; } @@ -43,13 +43,13 @@ static uint32_t uc32_cpu_find_by_name(const char *name) return id; } -CPUState *uc32_cpu_init(const char *cpu_model) +CPUUniCore32State *uc32_cpu_init(const char *cpu_model) { - CPUState *env; + CPUUniCore32State *env; uint32_t id; static int inited = 1; - env = g_malloc0(sizeof(CPUState)); + env = g_malloc0(sizeof(CPUUniCore32State)); cpu_exec_init(env); id = uc32_cpu_find_by_name(cpu_model); @@ -94,12 +94,12 @@ uint32_t HELPER(clz)(uint32_t x) return clz32(x); } -void do_interrupt(CPUState *env) +void do_interrupt(CPUUniCore32State *env) { env->exception_index = -1; } -int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw, +int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw, int mmu_idx) { env->exception_index = UC32_EXCP_TRAP; @@ -108,44 +108,44 @@ int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw, } /* These should probably raise undefined insn exceptions. */ -void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val) +void HELPER(set_cp)(CPUUniCore32State *env, uint32_t insn, uint32_t val) { int op1 = (insn >> 8) & 0xf; cpu_abort(env, "cp%i insn %08x\n", op1, insn); return; } -uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn) +uint32_t HELPER(get_cp)(CPUUniCore32State *env, uint32_t insn) { int op1 = (insn >> 8) & 0xf; cpu_abort(env, "cp%i insn %08x\n", op1, insn); return 0; } -void HELPER(set_cp0)(CPUState *env, uint32_t insn, uint32_t val) +void HELPER(set_cp0)(CPUUniCore32State *env, uint32_t insn, uint32_t val) { cpu_abort(env, "cp0 insn %08x\n", insn); } -uint32_t HELPER(get_cp0)(CPUState *env, uint32_t insn) +uint32_t HELPER(get_cp0)(CPUUniCore32State *env, uint32_t insn) { cpu_abort(env, "cp0 insn %08x\n", insn); return 0; } -void switch_mode(CPUState *env, int mode) +void switch_mode(CPUUniCore32State *env, int mode) { if (mode != ASR_MODE_USER) { cpu_abort(env, "Tried to switch out of user mode\n"); } } -void HELPER(set_r29_banked)(CPUState *env, uint32_t mode, uint32_t val) +void HELPER(set_r29_banked)(CPUUniCore32State *env, uint32_t mode, uint32_t val) { cpu_abort(env, "banked r29 write\n"); } -uint32_t HELPER(get_r29_banked)(CPUState *env, uint32_t mode) +uint32_t HELPER(get_r29_banked)(CPUUniCore32State *env, uint32_t mode) { cpu_abort(env, "banked r29 read\n"); return 0; @@ -178,7 +178,7 @@ static inline int ucf64_exceptbits_from_host(int host_bits) return target_bits; } -uint32_t HELPER(ucf64_get_fpscr)(CPUState *env) +uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env) { int i; uint32_t fpscr; @@ -212,7 +212,7 @@ static inline int ucf64_exceptbits_to_host(int target_bits) return host_bits; } -void HELPER(ucf64_set_fpscr)(CPUState *env, uint32_t val) +void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val) { int i; uint32_t changed; @@ -246,42 +246,42 @@ void HELPER(ucf64_set_fpscr)(CPUState *env, uint32_t val) set_float_exception_flags(i, &env->ucf64.fp_status); } -float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUState *env) +float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env) { return float32_add(a, b, &env->ucf64.fp_status); } -float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUState *env) +float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env) { return float64_add(a, b, &env->ucf64.fp_status); } -float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUState *env) +float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env) { return float32_sub(a, b, &env->ucf64.fp_status); } -float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUState *env) +float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env) { return float64_sub(a, b, &env->ucf64.fp_status); } -float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUState *env) +float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env) { return float32_mul(a, b, &env->ucf64.fp_status); } -float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUState *env) +float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env) { return float64_mul(a, b, &env->ucf64.fp_status); } -float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUState *env) +float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env) { return float32_div(a, b, &env->ucf64.fp_status); } -float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUState *env) +float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUniCore32State *env) { return float64_div(a, b, &env->ucf64.fp_status); } @@ -307,7 +307,7 @@ float64 HELPER(ucf64_absd)(float64 a) } /* XXX: check quiet/signaling case */ -void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUState *env) +void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUUniCore32State *env) { int flag; flag = float32_compare_quiet(a, b, &env->ucf64.fp_status); @@ -355,7 +355,7 @@ void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUState *env) | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff); } -void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c, CPUState *env) +void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c, CPUUniCore32State *env) { int flag; flag = float64_compare_quiet(a, b, &env->ucf64.fp_status); @@ -449,34 +449,34 @@ static inline uint64_t ucf64_dtoi(float64 d) } /* Integer to float conversion. */ -float32 HELPER(ucf64_si2sf)(float32 x, CPUState *env) +float32 HELPER(ucf64_si2sf)(float32 x, CPUUniCore32State *env) { return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status); } -float64 HELPER(ucf64_si2df)(float32 x, CPUState *env) +float64 HELPER(ucf64_si2df)(float32 x, CPUUniCore32State *env) { return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status); } /* Float to integer conversion. */ -float32 HELPER(ucf64_sf2si)(float32 x, CPUState *env) +float32 HELPER(ucf64_sf2si)(float32 x, CPUUniCore32State *env) { return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status)); } -float32 HELPER(ucf64_df2si)(float64 x, CPUState *env) +float32 HELPER(ucf64_df2si)(float64 x, CPUUniCore32State *env) { return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status)); } /* floating point conversion */ -float64 HELPER(ucf64_sf2df)(float32 x, CPUState *env) +float64 HELPER(ucf64_sf2df)(float32 x, CPUUniCore32State *env) { return float32_to_float64(x, &env->ucf64.fp_status); } -float32 HELPER(ucf64_df2sf)(float64 x, CPUState *env) +float32 HELPER(ucf64_df2sf)(float64 x, CPUUniCore32State *env) { return float64_to_float32(x, &env->ucf64.fp_status); } diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c index 6cf5255b2..638a02097 100644 --- a/target-unicore32/op_helper.c +++ b/target-unicore32/op_helper.c @@ -28,9 +28,9 @@ static target_ulong asr_read(void) (env->CF << 29) | ((env->VF & 0x80000000) >> 3); } -target_ulong cpu_asr_read(CPUState *env1) +target_ulong cpu_asr_read(CPUUniCore32State *env1) { - CPUState *saved_env; + CPUUniCore32State *saved_env; target_ulong ret; saved_env = env; @@ -61,9 +61,9 @@ static void asr_write(target_ulong val, target_ulong mask) env->uncached_asr = (env->uncached_asr & ~mask) | (val & mask); } -void cpu_asr_write(CPUState *env1, target_ulong val, target_ulong mask) +void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask) { - CPUState *saved_env; + CPUUniCore32State *saved_env; saved_env = env; env = env1; diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 4d0aa43da..3b3ba163a 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -64,7 +64,7 @@ void uc32_translate_init(void) for (i = 0; i < 32; i++) { cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, regs[i]), regnames[i]); + offsetof(CPUUniCore32State, regs[i]), regnames[i]); } #define GEN_HELPER 2 @@ -94,7 +94,7 @@ static inline TCGv load_cpu_offset(int offset) return tmp; } -#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name)) +#define load_cpu_field(name) load_cpu_offset(offsetof(CPUUniCore32State, name)) static inline void store_cpu_offset(TCGv var, int offset) { @@ -103,7 +103,7 @@ static inline void store_cpu_offset(TCGv var, int offset) } #define store_cpu_field(var, name) \ - store_cpu_offset(var, offsetof(CPUState, name)) + store_cpu_offset(var, offsetof(CPUUniCore32State, name)) /* Set a variable to the value of a CPU register. */ static void load_reg_var(DisasContext *s, TCGv var, int reg) @@ -223,7 +223,7 @@ static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b) return tmp1; } -#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF)) +#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, CF)) /* Set CF to the top bit of var. */ static void gen_set_CF_bit31(TCGv var) @@ -237,8 +237,8 @@ static void gen_set_CF_bit31(TCGv var) /* Set N and Z flags from var. */ static inline void gen_logic_CC(TCGv var) { - tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF)); - tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF)); + tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, NF)); + tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, ZF)); } /* dest = T0 + T1 + CF. */ @@ -634,10 +634,10 @@ static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn, static inline long ucf64_reg_offset(int reg) { if (reg & 1) { - return offsetof(CPUState, ucf64.regs[reg >> 1]) + return offsetof(CPUUniCore32State, ucf64.regs[reg >> 1]) + offsetof(CPU_DoubleU, l.upper); } else { - return offsetof(CPUState, ucf64.regs[reg >> 1]) + return offsetof(CPUUniCore32State, ucf64.regs[reg >> 1]) + offsetof(CPU_DoubleU, l.lower); } } @@ -646,7 +646,7 @@ static inline long ucf64_reg_offset(int reg) #define ucf64_gen_st32(var, reg) store_cpu_offset(var, ucf64_reg_offset(reg)) /* UniCore-F64 single load/store I_offset */ -static void do_ucf64_ldst_i(CPUState *env, DisasContext *s, uint32_t insn) +static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { int offset; TCGv tmp; @@ -692,7 +692,7 @@ static void do_ucf64_ldst_i(CPUState *env, DisasContext *s, uint32_t insn) } /* UniCore-F64 load/store multiple words */ -static void do_ucf64_ldst_m(CPUState *env, DisasContext *s, uint32_t insn) +static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { unsigned int i; int j, n, freg; @@ -777,7 +777,7 @@ static void do_ucf64_ldst_m(CPUState *env, DisasContext *s, uint32_t insn) } /* UniCore-F64 mrc/mcr */ -static void do_ucf64_trans(CPUState *env, DisasContext *s, uint32_t insn) +static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { TCGv tmp; @@ -841,7 +841,7 @@ static void do_ucf64_trans(CPUState *env, DisasContext *s, uint32_t insn) } /* UniCore-F64 convert instructions */ -static void do_ucf64_fcvt(CPUState *env, DisasContext *s, uint32_t insn) +static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { if (UCOP_UCF64_FMT == 3) { ILLEGAL; @@ -907,7 +907,7 @@ static void do_ucf64_fcvt(CPUState *env, DisasContext *s, uint32_t insn) } /* UniCore-F64 compare instructions */ -static void do_ucf64_fcmp(CPUState *env, DisasContext *s, uint32_t insn) +static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { if (UCOP_SET(25)) { ILLEGAL; @@ -985,7 +985,7 @@ static void do_ucf64_fcmp(CPUState *env, DisasContext *s, uint32_t insn) } while (0) /* UniCore-F64 data processing */ -static void do_ucf64_datap(CPUState *env, DisasContext *s, uint32_t insn) +static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { if (UCOP_UCF64_FMT == 3) { ILLEGAL; @@ -1018,7 +1018,7 @@ static void do_ucf64_datap(CPUState *env, DisasContext *s, uint32_t insn) } /* Disassemble an F64 instruction */ -static void disas_ucf64_insn(CPUState *env, DisasContext *s, uint32_t insn) +static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { if (!UCOP_SET(29)) { if (UCOP_SET(26)) { @@ -1123,7 +1123,7 @@ static void gen_exception_return(DisasContext *s, TCGv pc) s->is_jmp = DISAS_UPDATE; } -static void disas_coproc_insn(CPUState *env, DisasContext *s, uint32_t insn) +static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { switch (UCOP_CPNUM) { case 2: @@ -1168,7 +1168,7 @@ static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) } /* data processing instructions */ -static void do_datap(CPUState *env, DisasContext *s, uint32_t insn) +static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { TCGv tmp; TCGv tmp2; @@ -1359,7 +1359,7 @@ static void do_datap(CPUState *env, DisasContext *s, uint32_t insn) } /* multiply */ -static void do_mult(CPUState *env, DisasContext *s, uint32_t insn) +static void do_mult(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { TCGv tmp; TCGv tmp2; @@ -1399,7 +1399,7 @@ static void do_mult(CPUState *env, DisasContext *s, uint32_t insn) } /* miscellaneous instructions */ -static void do_misc(CPUState *env, DisasContext *s, uint32_t insn) +static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { unsigned int val; TCGv tmp; @@ -1475,7 +1475,7 @@ static void do_misc(CPUState *env, DisasContext *s, uint32_t insn) } /* load/store I_offset and R_offset */ -static void do_ldst_ir(CPUState *env, DisasContext *s, uint32_t insn) +static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { unsigned int i; TCGv tmp; @@ -1524,7 +1524,7 @@ static void do_ldst_ir(CPUState *env, DisasContext *s, uint32_t insn) } /* SWP instruction */ -static void do_swap(CPUState *env, DisasContext *s, uint32_t insn) +static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { TCGv addr; TCGv tmp; @@ -1551,7 +1551,7 @@ static void do_swap(CPUState *env, DisasContext *s, uint32_t insn) } /* load/store hw/sb */ -static void do_ldst_hwsb(CPUState *env, DisasContext *s, uint32_t insn) +static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { TCGv addr; TCGv tmp; @@ -1603,7 +1603,7 @@ static void do_ldst_hwsb(CPUState *env, DisasContext *s, uint32_t insn) } /* load/store multiple words */ -static void do_ldst_m(CPUState *env, DisasContext *s, uint32_t insn) +static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { unsigned int val, i; int j, n, reg, user, loaded_base; @@ -1743,7 +1743,7 @@ static void do_ldst_m(CPUState *env, DisasContext *s, uint32_t insn) } /* branch (and link) */ -static void do_branch(CPUState *env, DisasContext *s, uint32_t insn) +static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { unsigned int val; int32_t offset; @@ -1772,7 +1772,7 @@ static void do_branch(CPUState *env, DisasContext *s, uint32_t insn) gen_jmp(s, val); } -static void disas_uc32_insn(CPUState *env, DisasContext *s) +static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s) { unsigned int insn; @@ -1850,7 +1850,7 @@ static void disas_uc32_insn(CPUState *env, DisasContext *s) /* generate intermediate code in gen_opc_buf and gen_opparam_buf for basic block 'tb'. If search_pc is TRUE, also generate PC information for each intermediate instruction. */ -static inline void gen_intermediate_code_internal(CPUState *env, +static inline void gen_intermediate_code_internal(CPUUniCore32State *env, TranslationBlock *tb, int search_pc) { DisasContext dc1, *dc = &dc1; @@ -2030,12 +2030,12 @@ done_generating: } } -void gen_intermediate_code(CPUState *env, TranslationBlock *tb) +void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb) { gen_intermediate_code_internal(env, tb, 0); } -void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) +void gen_intermediate_code_pc(CPUUniCore32State *env, TranslationBlock *tb) { gen_intermediate_code_internal(env, tb, 1); } @@ -2046,7 +2046,7 @@ static const char *cpu_mode_names[16] = { }; #define UCF64_DUMP_STATE -void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf, +void cpu_dump_state(CPUUniCore32State *env, FILE *f, fprintf_function cpu_fprintf, int flags) { int i; @@ -2097,7 +2097,7 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf, #endif } -void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) +void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb, int pc_pos) { env->regs[31] = gen_opc_pc[pc_pos]; } |