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author | Rafael Antognolli <rafael.antognolli@intel.com> | 2018-03-14 15:59:10 -0700 |
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committer | Rafael Antognolli <rafael.antognolli@intel.com> | 2018-03-14 16:03:23 -0700 |
commit | 357c40b56cd78f62181e08b6dac7411144673c32 (patch) | |
tree | 4f90b907948f7133ac3a9df6f97a61f42f9ef48c | |
parent | f0120c88dd90dee3a1352a8a178d5ac78fd77e22 (diff) |
anv: Enable object level preemption.
-rw-r--r-- | src/intel/vulkan/genX_state.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index c6e5404691..c130fba7b0 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -169,6 +169,24 @@ genX(init_device_state)(struct anv_device *device) gen10_emit_wa_lri_to_cache_mode_zero(&batch); #endif +#if GEN_GEN >= 9 + /* A fixed function pipe flush is required before modifying this field */ + anv_batch_emit(&batch, GENX(PIPE_CONTROL), pipe) { + pipe.PipeControlFlushEnable = true; + } + + /* enable object level preemption */ + uint32_t csc1; + + anv_pack_struct(&csc1, GENX(CS_CHICKEN1), + .ReplayMode = ObjectLevelPreemption, + .ReplayModeMask = 1); + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(CS_CHICKEN1_num); + lri.DataDWord = csc1; + } +#endif + anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe); assert(batch.next <= batch.end); |