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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2020-03-12 19:42:57 +0900 |
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committer | Ulf Hansson <ulf.hansson@linaro.org> | 2020-03-17 12:25:29 +0100 |
commit | 18b587b45c13bb6a07ed0edac15f06892593d07a (patch) | |
tree | 671f69b2b21cfba2d98dc0d168517d17eaf6a62e /drivers/rtc/rtc-rv3029c2.c | |
parent | 3397b251ea02003f47f0b1667f3fe30bb4f9ce90 (diff) |
mmc: sdhci-cadence: set SDHCI_QUIRK2_PRESET_VALUE_BROKEN for UniPhier
The SDHCI_PRESET_FOR_* registers are not set for the UniPhier platform
integration. (They are all read as zeros).
Set the SDHCI_QUIRK2_PRESET_VALUE_BROKEN quirk flag. Otherwise, the
High Speed DDR mode on the eMMC controller (MMC_TIMING_MMC_DDR52)
would not work.
I split the platform data to give no impact to other platforms,
although the UniPhier platform is currently only the upstream user
of this IP.
The SDHCI_QUIRK2_PRESET_VALUE_BROKEN flag is set if the compatible
string matches to "socionext,uniphier-sd4hc".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20200312104257.21017-1-yamada.masahiro@socionext.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/rtc/rtc-rv3029c2.c')
0 files changed, 0 insertions, 0 deletions