From ce41c91c5c554b4c2643792651d60c161a62be35 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Wed, 10 Jul 2013 19:49:20 -0300 Subject: drm/i915: make IER optional at intel_irq_reg_reset Some interrupts (e.g., FDI_RX, SRD, PCH_GTC) don't have an IER register, just IMR and IIR, so add support for them at intel_irq_reg_reset. The next patches are going to add these interrupts. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_irq.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index c9afe121b738..a1829d44b49f 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -83,8 +83,12 @@ static void intel_irq_reg_reset16(struct drm_i915_private *dev_priv, uint32_t ier, uint32_t imr, uint32_t iir) { I915_WRITE16(imr, 0xffff); - I915_WRITE16(ier, 0); - POSTING_READ16(ier); + if (ier) { + I915_WRITE16(ier, 0); + POSTING_READ16(ier); + } else { + POSTING_READ16(imr); + } I915_WRITE16(iir, 0xffff); if (I915_READ16(iir)) { @@ -97,8 +101,12 @@ static void intel_irq_reg_reset(struct drm_i915_private *dev_priv, uint32_t ier, uint32_t imr, uint32_t iir) { I915_WRITE(imr, 0xffffffff); - I915_WRITE(ier, 0); - POSTING_READ(ier); + if (ier) { + I915_WRITE(ier, 0); + POSTING_READ(ier); + } else { + POSTING_READ(imr); + } I915_WRITE(iir, 0xffffffff); if (I915_READ(iir)) { -- cgit v1.2.3