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2014-02-26drm/i915: add more debugging power to the unclaimed register errorsbdw-runtime-pm-2014-02-26Paulo Zanoni1-9/+10
So we can find out what's happening on BDW. This should probably never be upstreamed as it will make everything slower. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: get/put runtime PM at i915_semaphore_statusPaulo Zanoni1-0/+3
Testcase: igt/pm_pc8/debugfs-read Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i195: add BDW runtime PM supportPaulo Zanoni2-3/+8
This sould be enough. v2: BDW should also run hsw_runtime_resume (Ben). Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: only check for irqs_disabled when disabling LCPLLPaulo Zanoni1-10/+7
Because if we keep the current code, we'll get tons of WARNs on Broadwell, since the code is Haswell-specific. We could have also added a Broadwell-specific code there, but it's not really needed since we never disable LCPLL with the hotplug interrupts still enabled. So keep the easy-and-simple-to-maintain solution until we actually need something else. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: remove HAS_PC8 checkPaulo Zanoni3-13/+2
Now that PC8 is part of runtime PM, the check is useless. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: BDW needs D_COMP writes through MCHBARPaulo Zanoni1-10/+18
That's what the spec said! And HSW needs it through pcode (you can only read it through MCHBAR), so create hsw_write_dcomp to abstract the weirdness. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: add SNB runtime PM supportPaulo Zanoni3-3/+33
Just because I have a SNB machine and I can easily test it. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: add gen-specific runtime suspend/resume functionsPaulo Zanoni1-8/+24
We're adding runtime suspend support to more platforms, so organize the code in a way that all a new platform needs to do is to add its own gen-specific functions. Also rename the i915_ functions to intel_ to make it clear that it's the top level one, not something that just runs on i915 platforms. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: kill dev_priv->pm.regsavePaulo Zanoni4-90/+16
Now that we don't keep the hotplug interrupts enabled anymore, we can kill the regsave struct and just cal the normal IRQ preinstall, postinstall and uninstall functions. This makes it easier to add runtime PM support to non-HSW platforms. The only downside is in case we get a request to update interrupts while they are disabled, won't be able to update the regsave struct. But this should never happen anyway, so we're not losing too much. v2: - Rebase. v3: - Rebase. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: init pm.suspended earlierPaulo Zanoni1-2/+1
Function intel_init_runtime_pm is supposed to start allowing runtime PM from that point, but it's called very late on the driver initialization code, to prevent the driver from trying to suspend while still initializing. The problem is that variables are accessed earlier than that, so initalize them at intel_pm_setup, which is supposed to be the correct place. Notice that this shouldn't fix any specific bugs because dev_priv is zeroed when allocated, so the value is already correct right from the start. v2: - Rebase. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: update the PC8 and runtime PM documentationPaulo Zanoni2-40/+35
Now that PC8 got much simpler, there are less things to document. Also, runtime PM already has a nice documentation, so we don't need to re-explain it on our driver. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: rename __hsw_do_{en,dis}able_pc8Paulo Zanoni3-6/+6
After we removed all the intermediate abstractions, we can rename these functions to just hsw_{en,dis}able_pc8. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: kill struct i915_package_c8Paulo Zanoni3-9/+0
The only remaining field of the struct was the lock, which was useless. v2: - Rebase. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: move pc8.irqs_disabled to pm.irqs_disabledPaulo Zanoni7-44/+45
When other platforms add runtime PM support they will also need to disable interrupts, so move the variable to the runtime PM struct. v2: - Rebase. v3: - Rebase. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: remove dev_priv->pc8.enabledPaulo Zanoni4-9/+0
It was just being used on debugfs and on a WARN inside hsw_set_power_well. But now that we PC8 is part of runtime PM and we get/put runtime PM when we get/put any power domain, we shouldn't need the WARN anymore. v2: - Rebase. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: don't get/put PC8 when getting/putting power wellsPaulo Zanoni3-32/+2
Because we already get/put runtime PM every time we get/put any power domain, and now PC8 and runtime PM are the same thing. With this, we can also now kill the hsw_{en,dis}able_package_c8 functions. v2: - Rebase. v3: - Rebase. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: get/put runtime PM references for GMBUS and DP AUXPaulo Zanoni4-17/+4
We had these intel_aux_display_runtime_{get,put} abstractions that would just get/put PC8 references, but now that runtime PM and PC8 are the same stuff, we just need the runtime PM references, so just get/put runtime PM directly, because that's what the rest of our code does. Another way to solve this problem would be to add DP_AUX and GMBUS power domains, and then use intel_display_power_{get,put}, but every power domain already gets/puts runtime PM references, so this would just make things more complex. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: don't get/put PC8 reference on freeze/thawPaulo Zanoni1-5/+0
We already get runtime PM references, and PC8 is now part of runtime PM, so this is enough. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: remove an indirection level on PC8 functionsPaulo Zanoni1-14/+2
After the latest changes, the indirection is useless. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: kill pc8.disable_countPaulo Zanoni4-17/+0
Since after the latest patches it's only being used to prevent getting/putting the runtime PM refcount. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: get runtime PM references when the GPU is idle/busyPaulo Zanoni1-2/+2
... instead of PC8 references. Now that both are the same thing and we are killing PC8, just get the runtime PM reference. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: remove dev_priv->pc8.requirements_metPaulo Zanoni4-59/+3
The requirements_met variable was used to track two things: enabled CRTCs and the power well. After the latest chagnes, we get a runtime PM reference whenever we get any of the power domains, and we get power domains when we enable CRTCs or the power well, so we should already be covered, not needing this specific tracking. v2: - Rebase. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: get/put runtime PM when we get/put a power domainPaulo Zanoni1-0/+4
Any power domain will require the HW to be in PCI D0 state, so just do the simple thing. Dear maintainer: since intel_display_power_put() and intel_display_power_get() are almost identical, git-am has failed apply the patch on my local machine once: it added both chunks to put(), instead of one chunk to get() and another to put(). When you apply this patch to your tree, please check if it is correct. v2: - Add the warning above. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: make PC8 be part of runtime PM suspend/resumePaulo Zanoni7-51/+23
Currently, when our driver becomes idle for i915.pc8_timeout (default: 5s) we enable PC8, so we save some power, but not everything we can. Then, while PC8 is enabled, if we stay idle for more autosuspend_delay_ms (default: 10s) we'll enter runtime PM and put the graphics device in D3 state, saving even more power. The two features are separate things with increasing levels of power savings, but if we disable PC8 we'll never get into D3. While from the modularity point of view it would be nice to keep these features as separate, we have reasons to merge them: - We are not aware of anybody wanting a "PC8 without D3" environment. - If we keep both features as separate, we'll have to to test both PC8 and PC8+D3 code paths. We're already having a major pain to make QA do automated testing of just one thing, testing both paths will cost even more. - Only Haswell+ supports PC8, so if we want to add runtime PM support to, for example, IVB, we'll have to copy some code from the PC8 feature to runtime PM, so merging both features as a single thing will make it easier for enabling runtime PM on other platforms. This patch only does the very basic steps required to have PC8 and runtime PM merged on a single feature: the next patches will take care of cleaning up everything. v2: - Rebase. v3: - Rebase. - Fully remove the deprecated i915 params since Daniel doesn't consider them as part of the ABI. v4: - Rebase. - Fix typo in the commit message. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: extract __hsw_do_{en,dis}able_package_c8Paulo Zanoni1-26/+38
When we merge PC8 and runtime PM, these new functions are going to be called by the runtime suspend/resume functions, and their callers are going to be removed. v2: - Rebase Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: add forcewake functions that don't touch runtime PMPaulo Zanoni2-0/+44
To solve a chicken-and-egg problem. Currently when we get/put forcewake we also get/put runtime PM and this works fine because the runtime PM code doesn't need forcewake. But we're going to merge PC8 and runtime PM into a single feature, and the PC8 code (the LCPLL code) does need the forcewake, so that specific piece of code needs to call the _no_rpm version so it doesn't try to get runtime PM in the code that gets runtime PM. For now the new functions are unused, we'll use them on the patch that merges PC8 with runtime PM. Also notice that, so simplify things, the put() function doesn't use the workqueue, since the workqueue also puts runtime PM. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: get/put runtime PM without holding rps.hw_lockPaulo Zanoni1-5/+7
We'll need this when we merge PC8 and Runtime PM: the PC8 enable/disable functions need that lock. Also, it's good practice to not hold a lock for longer than strictly needed. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: rename modeset_update_power_wellsPaulo Zanoni1-2/+2
To modeset_update_crtc_power_domains, since this function is responsible for updating all the power domains of all CRTCs after a modeset. In the future we should also run this function on all platforms, not just Haswell. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: add POSTING_READs to the IRQ init/reset macrosPaulo Zanoni1-11/+5
I previously chose to keep the POSTING_READ calls as something to be done by the macro callers, but the conclusion after discussing this on the mailing list is that leaving the POSTING_READ calls to the macros makes the code safer, and the additional useless register reads shouldn't be noticeable. So move the POSTING_READ calls to the callers. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: only enable HWSTAM interrupts on postinstall on ILK+Paulo Zanoni1-6/+4
We should only enable interrupts at postinstall. And now on ILK/SNB/IVB/HSW the irq_preinstall and irq_postinstall functions leave the hardware in the same state. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: add gen8_irq_resetPaulo Zanoni1-19/+7
So we can merge all the common code from postinstall and uninstall. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: add ironlake_irq_resetPaulo Zanoni1-11/+12
To merge the common code of ironlake_irq_preinstall and ironlake_irq_uninstall. We should also probably do something about that HSWSTAM write on a later commit. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: add missing intel_hpd_irq_uninstallPaulo Zanoni1-0/+2
Missing from gen8_irq_uninstall. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: remove ibx_irq_uninstallPaulo Zanoni1-18/+5
After the latest changes, ibx_irq_preinstall and ibx_irq_uninstall are the same, so remove one of the copies and rename the other to ibx_irq_reset (since we're using the "reset" name for things which are called both at preinstall and uninstall). Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: enable SDEIER laterPaulo Zanoni1-6/+21
On the preinstall stage we should just disable all the interrupts, but we currently enable all the south display interrupts due to the way we touch SDEIER at the IRQ handlers (note: they are still masked and our IRQ handler is disabled). Instead of doing that, let's make the preinstall stage just disable all the south interrupts, and do the proper interrupt dance/ordering at the postinstall stage, including an assert to check if everything is behaving as expected. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: call ibx_irq_uninstall from gen8_irq_uninstallPaulo Zanoni1-0/+2
After all, we call ibx_irq_preinstall from gen8_irq_preinstall. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: extract ibx_irq_uninstallPaulo Zanoni1-7/+14
Just like ibx_irq_preinstall. We'll call this from somewhere else in the next patch. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: fix open coded gen5_gt_irq_preinstallPaulo Zanoni1-7/+4
The duplicate was at an _uninstall function, so rename it to gen5_gt_irq_reset. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: fix GEN7_ERR_INT init/reset codePaulo Zanoni1-2/+5
Same as SERR_INT and the other IIR registers: reset on preinstall/uninstall and WARN for non-zero values at postinstall. This one also doesn't need double-clear. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: fix SERR_INT init/reset codePaulo Zanoni1-2/+6
The SERR_INT register is very similar to the other IIR registers, so let's zero it at preinstall/uninstall and WARN for a non-zero value at postinstall, just like we do with the other IIR registers. For this one, there's no need to double-clear since it can't store more than one interrupt. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: check if IIR is still zero at postinstall on Gen5+Paulo Zanoni1-17/+15
Instead of trying to clear it again. It should already be masked and disabled and zeroed at preinstall/uninstall. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: add GEN5_IRQ_INITPaulo Zanoni1-15/+18
And the equivalent GEN8_IRQ_INIT_NDX macro. These macros are for the postinstall functions. The next patch will improve this macro. Notice that I could have included POSTING_READ calls to the macro, but that would mean the code would do a few more POSTING_READs than necessary. OTOH it would be more fail-proof. I can change that if needed. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: properly clear IIR at irq_uninstall on Gen5+Paulo Zanoni1-48/+28
The IRQ_INIT and IRQ_FINI macros are basically the same thing, with the exception that IRQ_FINI doesn't properly clear IIR twice and doesn't have as many POSTING_READs as IRQ_INIT. So rename the macro to IRQ_RESET and use it everywhere. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: don't forget to uninstall the PM IRQsPaulo Zanoni1-0/+2
It's the only thihg missing, apparently. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: add GEN5_IRQ_FINIPaulo Zanoni1-9/+8
Same as the _INIT macro: the goal is to reuse the GEN8 macros, but there are still some slight differences. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: use GEN8_IRQ_INIT on GEN5Paulo Zanoni1-26/+23
And rename is to GEN5_IRQ_INIT. We have discussed doing equivalent changes on July 2013, and I even sent a patch series for this: "[PATCH 00/15] Unify interrupt register init/reset". Now that the BDW code was merged, I have one more argument in favor of these changes. Here's what really changes with the Gen 5 IRQ init code: - We now clear the IIR registers at preinstall (they are also cleared at postinstall, but we will change that later). - We have an additional POSTING_READ at the IMR register. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: also use GEN5_IRQ_INIT with south display interruptsPaulo Zanoni1-2/+1
This interrupt gets initialized with a different IER value, so it was not using the macro. The problem is that we plan to modify the macro to make it do additional things, and we want the SDE interrupts updated too. So let's make sure we call the macro, then, after it, we do the necessary SDE-specific changes. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: add GEN5_IRQ_INIT macroPaulo Zanoni1-14/+10
The goal is to reuse the GEN8 macros, but a few changes are needed, so let's make things easier to review. I could also use these macros on older code, but since I plan to change how the interrupts are initialized, we'll risk breaking the older code in the next commits, so I'll leave this out for now. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: add unclaimed register checks to BDWPaulo Zanoni2-0/+4
Just like we do to Haswell. v2: - Rebase. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2014-02-26drm/i915: don't read pp_ctrl_reg if we're suspendedPaulo Zanoni1-1/+2
... at edp_have_panel_vdd. Just return false, saying we don't have the panel VDD since the device is suspended. We started getting WARNs about this problem since the patch that started checking if we're suspended while reading registers. Testcase: igt/pm_pc8 Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-21 13:21:12 +0000