drm/i915: add intel_irq_reg_init{,16}

Same reason as intel_irq_reg_reset: let's standardize the way we init
registers so we make sure all the code is doing the same thing, and
then we can also change everybody at the same time if we need. This
function is for irq_postinstall functions. Again, this patch only
converts the cases where the new code perfectly matches the old one,
other cases will be done in separate patches for better bisectability.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

1 files changed, 38 insertions, 26 deletions

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 305ec87b72fa..e78c5f3ab12d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -109,6 +109,28 @@ static void intel_irq_reg_reset(struct drm_i915_private *dev_priv, uint32_t ier,
 	}
 }
 
+static void intel_irq_reg_init16(struct drm_i915_private *dev_priv,
+				 uint32_t ier, uint16_t ier_val, uint32_t imr,
+				 uint16_t imr_val, uint32_t iir)
+{
+	if (iir)
+		I915_WRITE16(iir, I915_READ16(iir));
+	I915_WRITE16(imr, imr_val);
+	I915_WRITE16(ier, ier_val);
+	POSTING_READ16(ier);
+}
+
+static void intel_irq_reg_init(struct drm_i915_private *dev_priv, uint32_t ier,
+			       uint32_t ier_val, uint32_t imr, uint32_t imr_val,
+			       uint32_t iir)
+{
+	if (iir)
+		I915_WRITE(iir, I915_READ(iir));
+	I915_WRITE(imr, imr_val);
+	I915_WRITE(ier, ier_val);
+	POSTING_READ(ier);
+}
+
 /* For display hotplug interrupt */
 static void
 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
@@ -2161,10 +2183,8 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
 		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
 	}
 
-	I915_WRITE(GTIIR, I915_READ(GTIIR));
-	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
-	I915_WRITE(GTIER, gt_irqs);
-	POSTING_READ(GTIER);
+	intel_irq_reg_init(dev_priv, GTIER, gt_irqs, GTIMR,
+			   dev_priv->gt_irq_mask, GTIIR);
 
 	if (INTEL_INFO(dev)->gen >= 6) {
 		pm_irqs |= GEN6_PM_RPS_EVENTS;
@@ -2172,10 +2192,8 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
 		if (HAS_VEBOX(dev))
 			pm_irqs |= PM_VEBOX_USER_INTERRUPT;
 
-		I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
-		I915_WRITE(GEN6_PMIMR, 0xffffffff);
-		I915_WRITE(GEN6_PMIER, pm_irqs);
-		POSTING_READ(GEN6_PMIER);
+		intel_irq_reg_init(dev_priv, GEN6_PMIER, pm_irqs, GEN6_PMIMR,
+				   0xffffffff, GEN6_PMIIR);
 	}
 }
 
@@ -2205,11 +2223,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 
 	dev_priv->irq_mask = ~display_mask;
 
-	/* should always can generate irq */
-	I915_WRITE(DEIIR, I915_READ(DEIIR));
-	I915_WRITE(DEIMR, dev_priv->irq_mask);
-	I915_WRITE(DEIER, display_mask | extra_mask);
-	POSTING_READ(DEIER);
+	intel_irq_reg_init(dev_priv, DEIER, display_mask | extra_mask, DEIMR,
+			   dev_priv->irq_mask, DEIIR);
 
 	gen5_gt_irq_postinstall(dev);
 
@@ -2345,6 +2360,10 @@ static void i8xx_irq_preinstall(struct drm_device * dev)
 static int i8xx_irq_postinstall(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	uint32_t enable_mask = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+			       I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
+			       I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
+			       I915_USER_INTERRUPT;
 
 	I915_WRITE16(EMR,
 		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
@@ -2356,14 +2375,9 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
 		  I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
 		  I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
 		  I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
-	I915_WRITE16(IMR, dev_priv->irq_mask);
 
-	I915_WRITE16(IER,
-		     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-		     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
-		     I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
-		     I915_USER_INTERRUPT);
-	POSTING_READ16(IER);
+	intel_irq_reg_init16(dev_priv, IER, enable_mask, IMR,
+			    dev_priv->irq_mask, 0);
 
 	return 0;
 }
@@ -2531,9 +2545,8 @@ static int i915_irq_postinstall(struct drm_device *dev)
 		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
 	}
 
-	I915_WRITE(IMR, dev_priv->irq_mask);
-	I915_WRITE(IER, enable_mask);
-	POSTING_READ(IER);
+	intel_irq_reg_init(dev_priv, IER, enable_mask, IMR, dev_priv->irq_mask,
+			   0);
 
 	i915_enable_asle_pipestat(dev);
 
@@ -2759,9 +2772,8 @@ static int i965_irq_postinstall(struct drm_device *dev)
 	}
 	I915_WRITE(EMR, error_mask);
 
-	I915_WRITE(IMR, dev_priv->irq_mask);
-	I915_WRITE(IER, enable_mask);
-	POSTING_READ(IER);
+	intel_irq_reg_init(dev_priv, IER, enable_mask, IMR, dev_priv->irq_mask,
+			   0);
 
 	I915_WRITE(PORT_HOTPLUG_EN, 0);
 	POSTING_READ(PORT_HOTPLUG_EN);