diff options
| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2013-07-09 14:06:08 -0300 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2013-07-15 11:52:31 -0300 |
| commit | 2a6b25617a4b2834809ac44279aa374675c1e003 (patch) | |
| tree | e6bdea1f5f953bbd89dbfe57494fe1b92b51bbc1 | |
| parent | 7c988c700b44e5f3d1594e72b970cf3780799270 (diff) | |
drm/i915: port i965 IME/IER/IIR to intel_irq_reg_reset
The problem here is that we have the PIPESTAT registers between IER
and IIR, so when we use intel_irq_reg_reset we flip the order used to
reset IIR and PIPESTAT. That should be safe since after we clear
IMR/IER we won't get any other IIR/PIPESTAT interrupts. Still, the
change is on its own patch, so it should be easy to bisect and revert
if needed.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 2b41726d2e53..a6fc79861c86 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2927,13 +2927,11 @@ static void i965_irq_uninstall(struct drm_device * dev) I915_WRITE(HWSTAM, 0xffffffff); for_each_pipe(pipe) I915_WRITE(PIPESTAT(pipe), 0); - I915_WRITE(IMR, 0xffffffff); - I915_WRITE(IER, 0x0); + intel_irq_reg_reset(dev_priv, IER, IMR, IIR); for_each_pipe(pipe) I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)) & 0x8000ffff); - I915_WRITE(IIR, I915_READ(IIR)); } static void i915_reenable_hotplug_timer_func(unsigned long data) |