diff options
| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2014-01-10 19:02:17 -0200 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2014-02-26 18:42:28 -0300 |
| commit | 1702fa7cdc9a880eaa2cc2565a1e1ac78da37504 (patch) | |
| tree | 37e00d184a142387b856ee5e63fa0f1bd606e9af | |
| parent | bddf14e399953c768139300ae1fc1bb4799dd7fc (diff) | |
drm/i915: fix SERR_INT init/reset code
The SERR_INT register is very similar to the other IIR registers, so
let's zero it at preinstall/uninstall and WARN for a non-zero value at
postinstall, just like we do with the other IIR registers. For this
one, there's no need to double-clear since it can't store more than
one interrupt.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 0550c98ea517..75862294894e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2865,6 +2865,10 @@ static void ibx_irq_preinstall(struct drm_device *dev) return; GEN5_IRQ_RESET(SDE); + + if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) + I915_WRITE(SERR_INT, 0xffffffff); + /* * SDEIER is also touched by the interrupt handler to work around missed * PCH interrupts. Hence we can't update it after the interrupt handler @@ -3003,7 +3007,7 @@ static void ibx_irq_postinstall(struct drm_device *dev) } else { mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT; - I915_WRITE(SERR_INT, I915_READ(SERR_INT)); + GEN5_ASSERT_IIR_IS_ZERO(SERR_INT); } GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); @@ -3281,7 +3285,7 @@ static void ironlake_irq_uninstall(struct drm_device *dev) GEN5_IRQ_RESET(SDE); if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) - I915_WRITE(SERR_INT, I915_READ(SERR_INT)); + I915_WRITE(SERR_INT, 0xffffffff); } static void i8xx_irq_preinstall(struct drm_device * dev) |