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2009-02-18nouveau: Add in-kernel backlight control supportMatthew Garrett3-0/+18
Several nvidia-based systems don't support backlight control via the standard ACPI control mechanisms. Instead, it's necessary for the driver to modify the backlight control registers directly. This patch adds support for determining whether the registers appear to be in use, and if so registers a kernel backlight device to control them. The backlight can then be controlled via existing userspace tools. Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2009-02-15nv40: fail completely if we don't have a ctxprog for the chipsetBen Skeggs1-11/+8
2009-02-15nv50: context info for chipset 0xa0Ben Skeggs2-1/+6168
2009-02-11drm/nv50: fix nv9x chipsetsBen Skeggs1-0/+7
NVIDIA do this fun little sequence after updating the PRAMIN page tables. On 9xxx chips, none of the PRAMIN BAR bindings (except the initial one) worked, hence the majority of the setup needed to create a channel ended up in the wrong place, causing all sorts of fun. This is done by NVIDIA on nv8x chips also, so we'll do it for them too, even though they appear to work without it.
2009-02-11drm/nv50: add context info for nv98Ben Skeggs2-1358/+2583
It won't work yet, just like the other 9xxx chips. Real soon now :)
2009-02-10drm/nv50: use a slightly different initial context for nv96Ben Skeggs2-1/+2046
I'm not 100% sure that the nv94 one we were using won't work. The context layouts are identical (well.. same ctxprog, so of course!), only a couple of registers differ. But, be safe until we actually get some 9xxx chips working.
2009-02-10drm/nv50: correct ramfc pointer in channel headerBen Skeggs1-1/+1
Suprisingly the card still worked without this...
2009-02-10drm/nv50: let the card handle the initial context switchBen Skeggs1-1/+2
Our PFIFO/PGRAPH context save/load functions don't really work well (at all?) on nv5x yet. Depending on what random state the card is in before the drm loads, fbcon probably won't work correctly. Luckily we've setup the GPU in such a way that it'll actually do a hw context switch for the first context. Not sure of how successful this'd be currently on the older chips (actually, pretty sure it won't work), so NV50 only for now.
2009-02-07nouveau: don't try to traverse non-existent listsStuart Bennett1-3/+3
Fixes nouveau_ioctl_mem_free Oops
2009-02-04nouveau: bring in new mm api definitions, without the actual mm codeBen Skeggs4-9/+136
Use of the new bits is guarded with a mm_enabled=0 hardcode.
2009-02-02Remove the "nv" driver.Stephane Marchesin1-52/+0
2009-01-29nouveau: don't save channel context if it has recently become invalidStuart Bennett1-2/+7
Bug exposed by DDX change d9da090c
2009-01-29nouveau: no suspend support for nv50+Stuart Bennett1-0/+5
2009-01-27intel: libdrm support for fence management in execbufJesse Barnes1-0/+2
This patch tries to use the available fence count to figure out whether a given batch can succeed or not (just like the aperture check). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-01-27nv50: support chipset NV96Ben Skeggs1-0/+2
ctxprog seen in okias' trace identical to one we use on NV94, assuming the initial context values for NV94 will work here too.
2009-01-27nv04-nv40: correct RAMHT sizeBen Skeggs2-7/+3
2009-01-12nv50: ack nsource to prevent continuous protection fault irqsBen Skeggs1-2/+22
2008-12-23[FreeBSD] Fix build on FreeBSD after modesetting import.Robert Noland1-0/+2
2008-12-23radeon: only write irq regs if irq is enabledDave Airlie1-2/+4
2008-12-22intel: Rename plane[AB]* back to pipe[AB]*.libdrm-2.4.3Eric Anholt1-8/+19
The values are really going to continue meaning pipe, not plane, and that's what they're called in the kernel copy of the header. Userland hasn't ever made the switch to pipe!=plane, since userland checks are based on DRM version, which is still stuck at 1.6. However, Mesa did start using plane[AB] names, so provide a compat define.
2008-12-22intel: Sync GEM ioctl comments for easier diffing against the kernel.Eric Anholt1-7/+20
2008-12-17libdrm: add mode setting filesJesse Barnes3-0/+299
Add mode setting files to libdrm, including xf86drmMode.* and the new drm_mode.h header. Also add a couple of tests to sanity check the kernel interfaces and update code to support them.
2008-12-10Revert "Merge branch 'modesetting-gem'"Jesse Barnes53-14316/+1239
This reverts commit 6656db10551bbb8770dd945b6d81d5138521f208. We really just want the libdrm and ioctl bits, not all the driver stuff.
2008-12-03Merge branch 'master' into modesetting-gemJesse Barnes2-131/+2417
2008-11-23nv50: support NV94 chipsetBen Skeggs2-0/+2103
2008-11-21nv50: update context-related tables for original 8800GTSBen Skeggs1-131/+314
I either messed up when I pulled these from a mmio-trace last time, or the previous values didn't work on my card. Hopefully it's the former! In any case, at least one of the original NV50 chipsets work now.
2008-11-20DRM: make drm_map_type match upstream kernelJesse Barnes1-2/+2
Since the TTM type isn't upstream yet, we need to make sure libdrm uses what the kernel uses, which is _DRM_GEM = 6.
2008-11-20DRM: make drm_map_type match kernelJesse Barnes1-2/+2
GEM is upstream, but TTM isn't, so _DRM_GEM needs to be 6, not 7.
2008-11-19Unbreak drm build.Stephane Marchesin1-1/+2
2008-11-19Merge branch 'modesetting-gem' of ssh://git.freedesktop.org/git/mesa/drm ↵Jesse Barnes2-0/+7
into modesetting-gem
2008-11-16radeon: protect cs ioctl atomic part with a mutexJerome Glisse2-0/+7
A small subset of CS need to be atomic (relocation+IB commit to ring) right now, because of the way relocation are handled, we need to protect the whole ioctl.
2008-11-13Merge branch 'master' into modesetting-gemJesse Barnes9-8045/+9397
Conflicts: libdrm/Makefile.am libdrm/intel/intel_bufmgr.h libdrm/intel/intel_bufmgr_fake.c libdrm/intel/intel_bufmgr_gem.c shared-core/drm.h shared-core/i915_dma.c shared-core/i915_irq.c shared-core/radeon_cp.c shared-core/radeon_drv.h
2008-11-13libdrm: add support for i915 GTT mapping ioctlJesse Barnes2-1/+15
Add a drm_intel_gem_bo_map_gtt() function for mapping a buffer object through the aperture rather than directly to its CPU cacheable memory.
2008-11-12mode: Minor reodering and renamingJakob Bornecrantz1-4/+4
2008-11-12mode: Reorder the ioctls and numberingJakob Bornecrantz1-18/+19
This is to fill in the gaps left by the removal of the hotplug ioctls. And they also look better :)
2008-11-12mode: Remove hotplug support from ioctl interfaceJakob Bornecrantz2-40/+0
2008-11-12mode: Unify types for ids and stringsJakob Bornecrantz1-18/+18
2008-11-10radeon: add gart useable size to report to userspaceDave Airlie1-0/+2
2008-11-10radeon: fix ring tail overflow issue since alignmentDave Airlie1-0/+2
2008-11-10radeon: disable HDP read cache for nowDave Airlie2-1/+6
2008-11-10radeon: force all ring writes to 16-dword alignment.Dave Airlie2-17/+41
2008-11-09radeon: add more packet3 relocations handlingJerome Glisse1-21/+78
2008-11-03radeon: make build againDave Airlie3-10/+2
2008-11-03radeon: add mtrr support for VRAM aperture.Dave Airlie1-0/+3
2008-11-03radeon: disable AGP for certain chips if not specified until we figure it outDave Airlie1-3/+10
2008-11-03radeon: disable debugging messageDave Airlie1-1/+1
2008-11-03radeon: commit ring after emitting the buffer discardsDave Airlie1-1/+2
2008-11-03radeon: setup isync cntl properlyDave Airlie1-2/+7
2008-11-03radeon: overhaul ring interactionsDave Airlie3-40/+66
emit in 16-dword blocks, emit irqs at same time as everything else
2008-11-03radeon: add proc debugging for interrupts/ringDave Airlie2-0/+4
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