From ddc584bdb5375f260e7dcec3831d1bb32f665d25 Mon Sep 17 00:00:00 2001 From: Leon Alrae Date: Fri, 27 Jun 2014 08:49:07 +0100 Subject: target-mips: do not allow Status.FR=0 mode in 64-bit FPU Status.FR bit must be ignored on write and read as 1 when an implementation of Release 6 of the Architecture in which a 64-bit floating point unit is implemented. Signed-off-by: Leon Alrae Reviewed-by: Yongbok Kim --- target-mips/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'target-mips') diff --git a/target-mips/translate.c b/target-mips/translate.c index 6f57171912..80887812ca 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -17951,6 +17951,12 @@ void cpu_state_reset(CPUMIPSState *env) } } #endif + if ((env->insn_flags & ISA_MIPS32R6) && + (env->active_fpu.fcr0 & (1 << FCR0_F64))) { + /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ + env->CP0_Status |= (1 << CP0St_FR); + } + compute_hflags(env); cs->exception_index = EXCP_NONE; } -- cgit v1.2.3