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2013-06-14Merge remote-tracking branch 'mjt/trivial-patches-next' into stagingAnthony Liguori1-0/+4
# By Michael Tokarev (4) and others # Via Michael Tokarev * mjt/trivial-patches-next: (26 commits) piix: fix some printf errors when debug is enabled cputlb: fix debug logs create qemu_openpty_raw() helper function and move it to a separate file main-loop: do not include slirp/slirp.h, use libslirp.h instead libcacard/vscclient: fix leakage of socket on error paths linux-headers: Update to v3.10-rc5 KVM: PPC: Add dummy kvm_arch_init_irq_routing() KVM: S390: Add dummy kvm_arch_init_irq_routing() KVM: ARM: Add dummy kvm_arch_init_irq_routing() ivshmem: add missing error exit(2) hw/xen: Use g_free instead of free and fix potential memory leaks target-sparc: Replace free by g_free hw/scsi: Don't increment a boolean value device tree: Fix cppcheck warning Makefile: Install qemu-img and qemu-nbd man pages only if built Unbreak -no-quit for GTK, validate SDL options gtk: implement -full-screen char/serial: serial_ioport_write: Factor out common code char/serial: Use generic Fifo8 char/serial: cosmetic fixes. ... Message-id: 1371207042-17980-1-git-send-email-mjt@msgid.tls.msk.ru Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-06-14Merge remote-tracking branch 'pmaydell/target-arm.next' into stagingAnthony Liguori1-1/+1
# By Peter Chubb # Via Peter Maydell * pmaydell/target-arm.next: Fix rfe instruction Message-id: 1370268884-25945-1-git-send-email-peter.maydell@linaro.org Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-06-12KVM: ARM: Add dummy kvm_arch_init_irq_routing()Alexey Kardashevskiy1-0/+4
The common KVM code insists on calling kvm_arch_init_irq_routing() as soon as it sees kernel header support for it (regardless of whether QEMU supports it). Provide a dummy function to satisfy this. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-06-03Fix rfe instructionPeter Chubb1-1/+1
The rfe instruction has been broken since patch 5a839c0d54fac9db0516904db873a4fe01f50f4b because of a typo. Signed-off-by: Peter Chubb <peter.chubb@nicta.com.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-01Remove unnecessary break statementsStefan Weil1-1/+0
Fix these warnings from cppcheck: hw/display/cirrus_vga.c:2603: hw/sd/sd.c:348: hw/timer/exynos4210_mct.c:1033: target-arm/translate.c:9886: target-s390x/mem_helper.c:518: target-unicore32/translate.c:1936: style: Consecutive return, break, continue, goto or throw statements are unnecessary. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-05-26target-arm: Remove gen_{ld,st}* definitionsPeter Maydell1-46/+0
All the uses of the gen_{ld,st}* functions are gone now, so remove the functions themselves. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Remove gen_{ld,st}* from thumb2 decoderPeter Maydell1-10/+20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Remove gen_{ld,st}* from Thumb insnsPeter Maydell1-25/+46
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Remove gen_{ld,st}* from basic ARM insnsPeter Maydell1-32/+69
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Remove use of gen_{ld,st}* from ldrex/strexPeter Maydell1-13/+18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Remove uses of gen_{ld,st}* from Neon codePeter Maydell1-18/+28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Remove uses of gen_{ld,st}* from iWMMXt codePeter Maydell1-8/+10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Remove gen_ld64() and gen_st64()Peter Maydell1-15/+4
gen_ld64() and gen_st64() are used only in one place, so just expand them out. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-26target-arm: Don't use TCGv when we mean TCGv_i32Peter Maydell1-224/+229
TCGv changes size depending on the compile time value of TARGET_LONG_BITS. This is useful for generating code for MIPS style "instructions are the same but the register width changes" CPUs, and also for the generic bits of QEMU which operate on "width of a virtual address" values, but mostly in the ARM target code we were using it purely as a shorthand for "any 32 bit value". This needs to change in preparation for AArch64 support, since an AArch64-capable v8 core will have 64 bit virtual addresses but still use 32 bit values for the 32 bit instruction set. This patch mechanically converts all the occurrences of TCGv, tcg_temp_new(), tcg_temp_free(), tcg_temp_local_new() and TCGV_UNUSED() to their explicitly 32 bit counterparts. This is correct for everything except the arguments to tcg_gen_qemu_{ld,st}*, which really do need to be TCGv and so will require a 32-to-64 conversion when building the 32 bit code for AArch64. Those changes will be in a separate patch for easier review. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-05-03target-arm: Fix incorrect check of kvm_vcpu_ioctl return valuePeter Maydell1-2/+2
kvm_vcpu_ioctl() returns -ETHING on error, not ETHING -- correct an incorrect check in kvm_arch_init_vcpu(). This would not have had any significant ill-effects -- we would just have propagated the less useful ENOENT up to the caller rather than the more accurate EINVAL in the unlikely case that the kernel didn't have VFP-D32 support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-19target-arm: Correctly restore FPSCRPeter Maydell1-7/+41
Use the helper functions to save and restore the FPSCR, so that we correctly propagate rounding mode and flushing behaviour into the float_status fields. This also allows us to stop saving the vector length/stride fields separately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-19target-arm: Add some missing CPU state fields to VMStatePeter Maydell1-3/+10
A number of CPU state fields were accidentally omitted from our migration state: some OMAP specific cp15 registers, and some related to state for load/store exclusive insns. Add them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-19target-arm: port ARM CPU save/load to use VMStateJuan Quintela4-215/+179
Port the ARM CPU save/load code to use VMState. Some state is saved in a slightly different order to simplify things -- for example arrays are saved one after the other rather than 'striped', and we always save all 32 VFP registers even if the CPU happens to only have 16. Use one subsection for each feature. This means that we don't need to bump the version field each time that a new feature gets introduced. Signed-off-by: Juan Quintela <quintela@redhat.com> [PMM: fixed conflicts, updated to use cpu_class_set_vmsd(), updated with new/removed fields since original patch, changed to use custom VMStateInfo for cpsr rather than presave/postload hooks, corrected subsection names so vmload doesn't fail] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-19target-arm: Reinsert missing return statement in ARM mode SRS decodePeter Chubb1-0/+1
Since patch 81465888c5306cd94abb9847e560796fd13d3c2f target-arm: factor out handling of SRS instruction the ARM mode SRS instruction has not worked in QEMU. The problem is a missing return directive that was removed in the refactoring, so after decoding the instruction, qemu would fall through to generate an UNDEF exception for an illegal instruction. Signed-off-by: Peter Chubb <peter.chubb@nicta.com.au> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-04-15arm: fix location of some include filesPeter Maydell2-2/+2
The recent rearrangement of include files had some minor errors: devices.h is not ARM specific and should not be in arm/ arm.h should be in arm/ Move these two headers to correct this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-04-08hw: move headers to include/Paolo Bonzini2-2/+2
Many of these should be cleaned up with proper qdev-/QOM-ification. Right now there are many catch-all headers in include/hw/ARCH depending on cpu.h, and this makes it necessary to compile these files per-target. However, fixing this does not belong in these patches. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-03-12target-arm: Override do_interrupt for ARMv7-M profileAndreas Färber3-6/+19
Enable ARMCPUInfo to specify a custom class_init functions. Introduce arm_v7m_class_init() and use it for "cortex-m3" model. Instead of forwarding from arm_cpu_do_interrupt() to do_interrupt_v7m(), override CPUClass::do_interrupt with arm_v7m_cpu_do_interrupt() in arm_v7m_class_init(). Acked-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber4-5/+10
This removes a global per-target function and thus takes us one step closer to compiling multiple targets into one executable. It will also allow to override the interrupt handling for certain CPU families. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-12cpu: Pass CPUState to cpu_interrupt()Andreas Färber1-1/+1
Move it to qom/cpu.h to avoid issues with include order. Change pc_acpi_smi_interrupt() opaque to X86CPU. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-12cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber3-5/+7
Both fields are used in VMState, thus need to be moved together. Explicitly zero them on reset since they were located before breakpoints. Pass PowerPCCPU to kvmppc_handle_halt(). Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-05target-arm: Use MemoryListener to identify GIC base address for KVMPeter Maydell2-0/+119
When using an in-kernel GIC with KVM, we need to tell the kernel where the GIC's memory mapped registers live. Do this by registering a MemoryListener which tracks where the board model maps the A15's private peripherals, so we can finish the GIC initialisation when the GIC is actually mapped. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2013-03-05ARM KVM: save and load VFP registers from kernelPeter Maydell1-3/+75
Add support for saving and restoring VFP register state from the kernel. This includes a check that the KVM-created CPU has full VFP support (as the TCG Cortex-A15 model always does), since for the moment ARM QEMU doesn't have any way to tweak optional features on created CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2013-03-05ARM: KVM: Add support for KVM on ARM architectureChristoffer Dall4-1/+337
Add basic support for KVM on ARM architecture. Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu> [PMM: Minor tweaks and code cleanup, switch to ONE_REG] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2013-03-05target-arm: Drop CPUARMState* argument from bank_number()Peter Maydell1-7/+6
Drop the CPUARMState* argument from bank_number(), since we only use it for passing to cpu_abort(). Use hw_error() instead. This avoids propagating further interfaces using env pointers. In the long term this function's callers need auditing to fix problems where badly behaved guests can pass invalid bank numbers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2013-03-05target-arm: Don't decode RFE or SRS on M profile coresPeter Maydell1-2/+3
M profile cores do not have the RFE or SRS instructions, so correctly UNDEF these insn patterns on those cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-03-05target-arm: Factor out handling of SRS instructionPeter Maydell1-67/+69
Factor out the handling of the SRS instruction rather than duplicating it between the Thumb and ARM decoders. This in passing fixes two bugs in the Thumb decoder's SRS handling which didn't exist in the ARM decoder: * (LP:1079080) storing CPSR rather than SPSR (fixed in the ARM decoder in commit c67b6b71 in 2009) * failing to free the 'addr' TCG temp in the writeback case Reported-by: Cesson Vincent <vcesson@stmi.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell1-2/+2
The gen_icount_start/end functions are now somewhat misnamed since they are useful for generic "start/end of TB" code, used for more than just icount. Rename them to gen_tb_start/end. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-03-03cpu: Introduce ENV_OFFSET macrosAndreas Färber1-0/+2
Introduce ENV_OFFSET macros which can be used in non-target-specific code that needs to generate TCG instructions which reference CPUState fields given the cpu_env register that TCG targets set up with a pointer to the CPUArchState struct. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-25target-arm: Fix sbc_CC carryRichard Henderson1-24/+4
While T0+~T1+CF = T0-T1+CF-1 is true for the low 32-bits, it does not produce the correct carry-out to bit 33. Do exactly what the manual says. Using the ~T1 makes the add and subtract code paths nearly identical, so have sbc_CC use adc_CC. Cc: Peter Maydell <peter.maydell@linaro.org> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-02-25arm/translate.c: Fix adc_CC/sbc_CC implementationPeter Crosthwaite1-2/+2
commits 49b4c31efcce45ab714f286f14fa5d5173f9069d and 2de68a4900ef6eb67380b0c128abfe1976bc66e8 reworked the implementation of adc_CC and sub_CC. The new implementations (on the TCG_TARGET_HAS_add2_i32 code path) are incorrect. The new logic is: CF:NF = 0:A +/- 0:CF CF:NF = CF:A +/- 0:B The lower 32 bits of the intermediate result stored in NF needs to be passes into the second addition in place of A (s/CF:A/CF:NF): CF:NF = 0:A +/- 0:CF CF:NF = CF:NF +/- 0:B This patch fixes the issue. Cc: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-02-23target-arm: Implement sbc_cc inlineRichard Henderson3-25/+39
Use sub2 if available, otherwise use 64-bit arithmetic. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-arm: Implement adc_cc inlineRichard Henderson3-21/+34
Use add2 if available, otherwise use 64-bit arithmetic. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-arm: Use add2 in gen_add_CCRichard Henderson1-4/+3
Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-arm: Use mul[us]2 and add2 in umlal et alRichard Henderson3-19/+14
Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-arm: Use mul[us]2 in gen_mul[us]_i64_i32Richard Henderson1-16/+22
Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-16cpu: Add CPUArchState pointer to CPUStateAndreas Färber1-0/+2
The target-specific ENV_GET_CPU() macros have allowed us to navigate from CPUArchState to CPUState. The reverse direction was not supported. Avoid introducing CPU_GET_ENV() macros by initializing an untyped pointer that is initialized in derived instance_init functions. The field may not be called "env" due to it being poisoned. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-02-16target-arm: Move TCG initialization to ARMCPU initfnAndreas Färber2-6/+6
Ensures that a QOM-created ARMCPU is usable. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-02-16target-arm: Update ARMCPU to QOM realizefnAndreas Färber4-12/+27
Turn arm_cpu_realize() into a QOM realize function, no longer called via cpu.h prototype. To maintain the semantics of cpu_init(), set realized = true explicitly in cpu_arm_init(). Move GDB coprocessor registration, CPU reset and vCPU initialization into the realizefn. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-30target-arm: Rename CPU typesAndreas Färber2-5/+14
In the initial conversion of CPU models to QOM types, model names were mapped 1:1 to type names. As a side effect this gained us a type "any", which is now a device. To avoid "-device any" silliness and to pave the way for compiling multiple targets into one executable, adopt a <name>-<arch>-cpu scheme. This leads to names like arm926-arm-cpu but is easiest to handle. No functional changes for -cpu arguments or -cpu ? output. Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-01-30target-arm: Fix TCG temp leaks for WI and UNDEF VFP sysreg writesPeter Maydell1-1/+4
Fix a leak of a TCG temporary in code paths for VFP system register writes for cases which UNDEF or are write-ignored. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-01-27target-arm: Catch attempt to instantiate abstract type in cpu_init()Andreas Färber1-1/+2
This fixes -cpu arm-cpu asserting. Cc: qemu-stable@nongnu.org Acked-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-27target-arm: Detect attempt to instantiate non-CPU type in cpu_init()Andreas Färber2-2/+21
Consolidate model checking into a new arm_cpu_class_by_name(). If the name matches an existing type, also check whether that type is actually (a sub-type of) TYPE_ARM_CPU. This fixes, e.g., -cpu tmp105 asserting. Cc: qemu-stable <qemu-stable@nongnu.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-15cpu: Move cpu_index field to CPUStateAndreas Färber2-2/+3
Note that target-alpha accesses this field from TCG, now using a negative offset. Therefore the field is placed last in CPUState. Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change. Move common parts of mips cpu_state_reset() to mips_cpu_reset(). Acked-by: Richard Henderson <rth@twiddle.net> (for alpha) [AF: Rebased onto ppc CPU subclasses and openpic changes] Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-11target-arm: Fix SWI (SVC) instruction in M profile.Alex_Rozenman@mentor.com1-1/+1
When do_interrupt_v7m is called with EXCP_SWI, the PC already points to the next instruction. Don't modify it here. Signed-off-by: Alex Rozenman <Alex_Rozenman@mentor.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-01-11target-arm: use type_register() instead of type_register_static()Eduardo Habkost1-1/+1
The type_register_static() interface is documented as: type_register_static: @info: The #TypeInfo of the new type. @info and all of the strings it points to should exist for the life time that the type is registered. But cpu_register() uses a stack variable for the 'info' argument, so it has to use type_register() instead of type_register_static(). Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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