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Diffstat (limited to 'hw/ppc405_uc.c')
-rw-r--r--hw/ppc405_uc.c153
1 files changed, 59 insertions, 94 deletions
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index dfe1905c90..e050b75e45 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -164,7 +164,7 @@ static void ppc4xx_plb_reset (void *opaque)
plb->besr = 0x00000000;
}
-void ppc4xx_plb_init (CPUState *env)
+static void ppc4xx_plb_init(CPUState *env)
{
ppc4xx_plb_t *plb;
@@ -241,7 +241,7 @@ static void ppc4xx_pob_reset (void *opaque)
pob->besr[1] = 0x0000000;
}
-void ppc4xx_pob_init (CPUState *env)
+static void ppc4xx_pob_init(CPUState *env)
{
ppc4xx_pob_t *pob;
@@ -250,14 +250,13 @@ void ppc4xx_pob_init (CPUState *env)
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
qemu_register_reset(ppc4xx_pob_reset, pob);
- ppc4xx_pob_reset(env);
+ ppc4xx_pob_reset(pob);
}
/*****************************************************************************/
/* OPB arbitrer */
typedef struct ppc4xx_opba_t ppc4xx_opba_t;
struct ppc4xx_opba_t {
- target_phys_addr_t base;
uint8_t cr;
uint8_t pr;
};
@@ -271,7 +270,7 @@ static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
printf("%s: addr " PADDRX "\n", __func__, addr);
#endif
opba = opaque;
- switch (addr - opba->base) {
+ switch (addr) {
case 0x00:
ret = opba->cr;
break;
@@ -295,7 +294,7 @@ static void opba_writeb (void *opaque,
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
#endif
opba = opaque;
- switch (addr - opba->base) {
+ switch (addr) {
case 0x00:
opba->cr = value & 0xF8;
break;
@@ -374,20 +373,19 @@ static void ppc4xx_opba_reset (void *opaque)
opba->pr = 0x11;
}
-void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
- target_phys_addr_t offset)
+static void ppc4xx_opba_init(target_phys_addr_t base)
{
ppc4xx_opba_t *opba;
+ int io;
opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
- opba->base = offset;
#ifdef DEBUG_OPBA
- printf("%s: offset " PADDRX "\n", __func__, offset);
+ printf("%s: offset " PADDRX "\n", __func__, base);
#endif
- ppc4xx_mmio_register(env, mmio, offset, 0x002,
- opba_read, opba_write, opba);
- qemu_register_reset(ppc4xx_opba_reset, opba);
+ io = cpu_register_io_memory(opba_read, opba_write, opba);
+ cpu_register_physical_memory(base, 0x002, io);
ppc4xx_opba_reset(opba);
+ qemu_register_reset(ppc4xx_opba_reset, opba);
}
/*****************************************************************************/
@@ -574,7 +572,7 @@ static void ebc_reset (void *opaque)
ebc->cfg = 0x80400000;
}
-void ppc405_ebc_init (CPUState *env)
+static void ppc405_ebc_init(CPUState *env)
{
ppc4xx_ebc_t *ebc;
@@ -665,7 +663,7 @@ static void ppc405_dma_reset (void *opaque)
dma->pol = 0x00000000;
}
-void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
+static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
{
ppc405_dma_t *dma;
@@ -727,7 +725,6 @@ void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
/* GPIO */
typedef struct ppc405_gpio_t ppc405_gpio_t;
struct ppc405_gpio_t {
- target_phys_addr_t base;
uint32_t or;
uint32_t tcr;
uint32_t osrh;
@@ -829,48 +826,19 @@ static void ppc405_gpio_reset (void *opaque)
gpio = opaque;
}
-void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
- target_phys_addr_t offset)
+static void ppc405_gpio_init(target_phys_addr_t base)
{
ppc405_gpio_t *gpio;
+ int io;
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
- gpio->base = offset;
- ppc405_gpio_reset(gpio);
- qemu_register_reset(&ppc405_gpio_reset, gpio);
#ifdef DEBUG_GPIO
- printf("%s: offset " PADDRX "\n", __func__, offset);
-#endif
- ppc4xx_mmio_register(env, mmio, offset, 0x038,
- ppc405_gpio_read, ppc405_gpio_write, gpio);
-}
-
-/*****************************************************************************/
-/* Serial ports */
-static CPUReadMemoryFunc *serial_mm_read[] = {
- &serial_mm_readb,
- &serial_mm_readw,
- &serial_mm_readl,
-};
-
-static CPUWriteMemoryFunc *serial_mm_write[] = {
- &serial_mm_writeb,
- &serial_mm_writew,
- &serial_mm_writel,
-};
-
-void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
- target_phys_addr_t offset, qemu_irq irq,
- CharDriverState *chr)
-{
- void *serial;
-
-#ifdef DEBUG_SERIAL
- printf("%s: offset " PADDRX "\n", __func__, offset);
+ printf("%s: offset " PADDRX "\n", __func__, base);
#endif
- serial = serial_mm_init(offset, 0, irq, 399193, chr, 0);
- ppc4xx_mmio_register(env, mmio, offset, 0x008,
- serial_mm_read, serial_mm_write, serial);
+ io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);
+ cpu_register_physical_memory(base, 0x038, io);
+ ppc405_gpio_reset(gpio);
+ qemu_register_reset(&ppc405_gpio_reset, gpio);
}
/*****************************************************************************/
@@ -1021,7 +989,7 @@ static void ocm_reset (void *opaque)
ocm->dsacntl = dsacntl;
}
-void ppc405_ocm_init (CPUState *env)
+static void ppc405_ocm_init(CPUState *env)
{
ppc405_ocm_t *ocm;
@@ -1043,7 +1011,6 @@ void ppc405_ocm_init (CPUState *env)
/* I2C controller */
typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
struct ppc4xx_i2c_t {
- target_phys_addr_t base;
qemu_irq irq;
uint8_t mdata;
uint8_t lmadr;
@@ -1071,7 +1038,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
printf("%s: addr " PADDRX "\n", __func__, addr);
#endif
i2c = opaque;
- switch (addr - i2c->base) {
+ switch (addr) {
case 0x00:
// i2c_readbyte(&i2c->mdata);
ret = i2c->mdata;
@@ -1138,7 +1105,7 @@ static void ppc4xx_i2c_writeb (void *opaque,
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
#endif
i2c = opaque;
- switch (addr - i2c->base) {
+ switch (addr) {
case 0x00:
i2c->mdata = value;
// i2c_sendbyte(&i2c->mdata);
@@ -1266,20 +1233,19 @@ static void ppc4xx_i2c_reset (void *opaque)
i2c->directcntl = 0x0F;
}
-void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
- target_phys_addr_t offset, qemu_irq irq)
+static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
{
ppc4xx_i2c_t *i2c;
+ int io;
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
- i2c->base = offset;
i2c->irq = irq;
- ppc4xx_i2c_reset(i2c);
#ifdef DEBUG_I2C
- printf("%s: offset " PADDRX "\n", __func__, offset);
+ printf("%s: offset " PADDRX "\n", __func__, base);
#endif
- ppc4xx_mmio_register(env, mmio, offset, 0x011,
- i2c_read, i2c_write, i2c);
+ io = cpu_register_io_memory(i2c_read, i2c_write, i2c);
+ cpu_register_physical_memory(base, 0x011, io);
+ ppc4xx_i2c_reset(i2c);
qemu_register_reset(ppc4xx_i2c_reset, i2c);
}
@@ -1287,7 +1253,6 @@ void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
/* General purpose timers */
typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
struct ppc4xx_gpt_t {
- target_phys_addr_t base;
int64_t tb_offset;
uint32_t tb_freq;
struct QEMUTimer *timer;
@@ -1399,7 +1364,7 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
printf("%s: addr " PADDRX "\n", __func__, addr);
#endif
gpt = opaque;
- switch (addr - gpt->base) {
+ switch (addr) {
case 0x00:
/* Time base counter */
ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
@@ -1428,12 +1393,12 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
break;
case 0x80 ... 0x90:
/* Compare timer */
- idx = ((addr - gpt->base) - 0x80) >> 2;
+ idx = (addr - 0x80) >> 2;
ret = gpt->comp[idx];
break;
case 0xC0 ... 0xD0:
/* Compare mask */
- idx = ((addr - gpt->base) - 0xC0) >> 2;
+ idx = (addr - 0xC0) >> 2;
ret = gpt->mask[idx];
break;
default:
@@ -1454,7 +1419,7 @@ static void ppc4xx_gpt_writel (void *opaque,
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
#endif
gpt = opaque;
- switch (addr - gpt->base) {
+ switch (addr) {
case 0x00:
/* Time base counter */
gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq)
@@ -1492,13 +1457,13 @@ static void ppc4xx_gpt_writel (void *opaque,
break;
case 0x80 ... 0x90:
/* Compare timer */
- idx = ((addr - gpt->base) - 0x80) >> 2;
+ idx = (addr - 0x80) >> 2;
gpt->comp[idx] = value & 0xF8000000;
ppc4xx_gpt_compute_timer(gpt);
break;
case 0xC0 ... 0xD0:
/* Compare mask */
- idx = ((addr - gpt->base) - 0xC0) >> 2;
+ idx = (addr - 0xC0) >> 2;
gpt->mask[idx] = value & 0xF8000000;
ppc4xx_gpt_compute_timer(gpt);
break;
@@ -1545,24 +1510,24 @@ static void ppc4xx_gpt_reset (void *opaque)
}
}
-void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
- target_phys_addr_t offset, qemu_irq irqs[5])
+static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
{
ppc4xx_gpt_t *gpt;
int i;
+ int io;
gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
- gpt->base = offset;
- for (i = 0; i < 5; i++)
+ for (i = 0; i < 5; i++) {
gpt->irqs[i] = irqs[i];
+ }
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
- ppc4xx_gpt_reset(gpt);
#ifdef DEBUG_GPT
- printf("%s: offset " PADDRX "\n", __func__, offset);
+ printf("%s: offset " PADDRX "\n", __func__, base);
#endif
- ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
- gpt_read, gpt_write, gpt);
+ io = cpu_register_io_memory(gpt_read, gpt_write, gpt);
+ cpu_register_physical_memory(base, 0x0d4, io);
qemu_register_reset(ppc4xx_gpt_reset, gpt);
+ ppc4xx_gpt_reset(gpt);
}
/*****************************************************************************/
@@ -1778,7 +1743,7 @@ static void ppc40x_mal_reset (void *opaque)
mal->txeobisr = 0x00000000;
}
-void ppc405_mal_init (CPUState *env, qemu_irq irqs[4])
+static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
{
ppc40x_mal_t *mal;
int i;
@@ -2183,20 +2148,18 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
clk_setup_t clk_setup[PPC405CR_CLK_NB];
qemu_irq dma_irqs[4];
CPUState *env;
- ppc4xx_mmio_t *mmio;
qemu_irq *pic, *irqs;
memset(clk_setup, 0, sizeof(clk_setup));
env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
&clk_setup[PPC405CR_TMR_CLK], sysclk);
/* Memory mapped devices registers */
- mmio = ppc4xx_mmio_init(env, 0xEF600000);
/* PLB arbitrer */
ppc4xx_plb_init(env);
/* PLB to OPB bridge */
ppc4xx_pob_init(env);
/* OBP arbitrer */
- ppc4xx_opba_init(env, mmio, 0x600);
+ ppc4xx_opba_init(0xef600600);
/* Universal interrupt controller */
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
irqs[PPCUIC_OUTPUT_INT] =
@@ -2217,15 +2180,17 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
ppc405_dma_init(env, dma_irqs);
/* Serial ports */
if (serial_hds[0] != NULL) {
- ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
+ serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
+ serial_hds[0], 1);
}
if (serial_hds[1] != NULL) {
- ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
+ serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
+ serial_hds[1], 1);
}
/* IIC controller */
- ppc405_i2c_init(env, mmio, 0x500, pic[2]);
+ ppc405_i2c_init(0xef600500, pic[2]);
/* GPIO */
- ppc405_gpio_init(env, mmio, 0x700);
+ ppc405_gpio_init(0xef600700);
/* CPU control */
ppc405cr_cpc_init(env, clk_setup, sysclk);
@@ -2528,7 +2493,6 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
CPUState *env;
- ppc4xx_mmio_t *mmio;
qemu_irq *pic, *irqs;
memset(clk_setup, 0, sizeof(clk_setup));
@@ -2539,13 +2503,12 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
/* Internal devices init */
/* Memory mapped devices registers */
- mmio = ppc4xx_mmio_init(env, 0xEF600000);
/* PLB arbitrer */
ppc4xx_plb_init(env);
/* PLB to OPB bridge */
ppc4xx_pob_init(env);
/* OBP arbitrer */
- ppc4xx_opba_init(env, mmio, 0x600);
+ ppc4xx_opba_init(0xef600600);
/* Universal interrupt controller */
irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
irqs[PPCUIC_OUTPUT_INT] =
@@ -2566,15 +2529,17 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
dma_irqs[3] = pic[8];
ppc405_dma_init(env, dma_irqs);
/* IIC controller */
- ppc405_i2c_init(env, mmio, 0x500, pic[2]);
+ ppc405_i2c_init(0xef600500, pic[2]);
/* GPIO */
- ppc405_gpio_init(env, mmio, 0x700);
+ ppc405_gpio_init(0xef600700);
/* Serial ports */
if (serial_hds[0] != NULL) {
- ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
+ serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
+ serial_hds[0], 1);
}
if (serial_hds[1] != NULL) {
- ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
+ serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
+ serial_hds[1], 1);
}
/* OCM */
ppc405_ocm_init(env);
@@ -2584,7 +2549,7 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
gpt_irqs[2] = pic[21];
gpt_irqs[3] = pic[22];
gpt_irqs[4] = pic[23];
- ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
+ ppc4xx_gpt_init(0xef600000, gpt_irqs);
/* PCI */
/* Uses pic[3], pic[16], pic[18] */
/* MAL */
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-28 20:32:17 +0000