blob: a5516f2765fe0ad9f7e337a92e1dd3da4e8ef740 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
|
/*
* Copyright (C) 2009 RDC Semiconductor Co.,Ltd
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* For technical support :
* <jason.lin@rdc.com.tw>
*/
#ifdef FPGA
#define MAX_HResolution 1024
#define MAX_VResolution 768
#else
#define MAX_HResolution 1920
#define MAX_VResolution 1200
#endif
#define TextModeIndex 0
#define EGAModeIndex 1
#define VGAModeIndex 2
#define HiCModeIndex 3
#define TrueCModeIndex 4
#define VCLK25_175 0x00
#define VCLK28_322 0x01
#define VCLK31_5 0x02
#define VCLK36 0x03
#define VCLK40 0x04
#define VCLK49_5 0x05
#define VCLK50 0x06
#define VCLK56_25 0x07
#define VCLK65 0x08
#define VCLK75 0x09
#define VCLK78_75 0x0A
#define VCLK94_5 0x0B
#define VCLK108 0x0C
#define VCLK135 0x0D
#define VCLK157_5 0x0E
#define VCLK162 0x0F
#define VCLK154 0x10
#define Charx8Dot 0x00000001
#define HalfDCLK 0x00000002
#define DoubleScanMode 0x00000004
#define LineCompareOff 0x00000008
#define SyncPP 0x00000000
#define SyncPN 0x00000040
#define SyncNP 0x00000080
#define SyncNN 0x000000C0
#define HBorder 0x00000020
#define VBorder 0x00000010
#define DAC_NUM_TEXT 64
#define DAC_NUM_EGA 64
#define DAC_NUM_VGA 256
#define LCD_TIMING 0x00010000
typedef struct {
UCHAR MISC;
UCHAR SEQ[4];
UCHAR CRTC[25];
UCHAR AR[20];
UCHAR GR[9];
} VBIOS_STDTABLE_STRUCT, *PVBIOS_STDTABLE_STRUCT;
typedef struct {
UCHAR ucNS;
UCHAR ucMS;
UCHAR ucRS;
} VBIOS_DCLK_INFO, *PVBIOS_DCLK_INFO;
typedef struct _RRateInfo{
float fRefreshRate;
Bool BInterlaced;
UCHAR ucRRateIndex;
}RRateInfo;
typedef struct _MODE_PRIVATE
{
USHORT Mode_ID_8bpp;
USHORT Mode_ID_16bpp;
USHORT Mode_ID_32bpp;
UCHAR ucRRate_ID;
} MODE_PRIVATE;
|
