summaryrefslogtreecommitdiff
path: root/src/gallium
AgeCommit message (Expand)AuthorFilesLines
2018-01-16gallium: add user_stride parameter to pipe_context::transfer_mapNicolai Hähnle33-12/+53
2018-01-16gallium: use pipe_transfer_map_box inline helperNicolai Hähnle27-45/+61
2018-01-15r600/shader: Initialize max_driver_temp_used correctly for the first timeGert Wollny1-0/+1
2018-01-14freedreno/ir3: "soft" depth scheduling for SFU instructionsRob Clark1-9/+21
2018-01-14freedreno/a5xx: work around SWAP vs TILE_MODE constraintRob Clark1-0/+20
2018-01-14freedreno/a5xx: texture tilingRob Clark16-25/+339
2018-01-14freedreno: update generated headersRob Clark6-26/+35
2018-01-14freedreno: add screen->setup_slices() for tex layoutRob Clark3-19/+43
2018-01-14r300g: remove double assignmentGrazvydas Ignotas1-1/+0
2018-01-13ac: fix build error in si_shaderMauro Rossi1-1/+1
2018-01-13radv/radeonsi/nir: lower 64bit flrpTimothy Arceri1-0/+1
2018-01-12broadcom/vc5: Fix up channel swizzling for textures on 4.x.Eric Anholt1-2/+5
2018-01-12broadcom/vc5: Port the draw-time state emission to V3D 4.1.Eric Anholt7-27/+76
2018-01-12broadcom/vc5: Rename V3D 3.x Flat Shade Action to match v4.x naming.Eric Anholt1-5/+5
2018-01-12broadcom/vc5: Update pixel center setup for V3D 4.x.Eric Anholt1-2/+12
2018-01-12broadcom/vc5: Print the buffer name in simulator overflow checks.Eric Anholt1-2/+4
2018-01-12broadcom/vc5: Update state setup for V3D 4.1.Eric Anholt7-14/+206
2018-01-12broadcom/vc5: Set up depth formats for V3D 4.x.Eric Anholt1-1/+12
2018-01-12broadcom/vc5: Always use the RGBA8 formats for RGBX8.Eric Anholt1-3/+7
2018-01-12broadcom/vc5: Move the formats table to per-V3D-version compile.Eric Anholt12-337/+451
2018-01-12broadcom/vc5: Use THRSW to enable multi-threaded shaders.Eric Anholt1-3/+26
2018-01-12broadcom/vc5: Port drawing commands to V3D 4.x.Eric Anholt9-20/+93
2018-01-12broadcom/vc5: Enable the driver on V3D 4.1Eric Anholt1-1/+1
2018-01-12broadcom/vc5: Port the simulator to support V3D 4.1Eric Anholt9-125/+216
2018-01-12broadcom/vc5: Port the RCL setup to V3D4.1.Eric Anholt7-58/+360
2018-01-12broadcom/vc5: Fix per-tile extra clear packet.Eric Anholt1-1/+1
2018-01-12broadcom/vc5: Move the TLB loads and stores to helper functions.Eric Anholt1-35/+50
2018-01-12broadcom/vc5: Convert vc5_cl.h to use the V3DX() macros.Eric Anholt7-10/+24
2018-01-11meson: move libsensors dependency to libgalliumDylan Baker8-13/+7
2018-01-11meson: Use dependencies for nirDylan Baker6-17/+21
2018-01-11meson: Use consistent style for testsDylan Baker3-4/+12
2018-01-11meson: Use consistent styleDylan Baker1-2/+4
2018-01-11svga: simplify failure code in emit_rss_vgpu9()Brian Paul1-17/+12
2018-01-11svga: remove unused fail parameter to EMIT_RS(), EMIT_RS_FLOAT()Brian Paul1-57/+57
2018-01-11svga: add assertion in svga_queue_rs()Brian Paul1-0/+1
2018-01-11svga: whitespace/formatting fixes in svga_state_rss.cBrian Paul1-79/+75
2018-01-11ac: add load_patch_vertices_in() to the abiTimothy Arceri1-6/+14
2018-01-10tgsi: include struct definitions for tgsi_build declarationsRob Herring1-5/+1
2018-01-10swr: Handle indirect indices in GSGeorge Kyriazis1-8/+39
2018-01-10amd/common: import get_{load,store}_intr_attribs() from RadeonSISamuel Pitoiset1-21/+5
2018-01-10swr/rast: switch win32 jit format to COFFTim Rowley1-2/+2
2018-01-10swr/rast: don't use 32-bit gathers for elements < 32-bits in sizeTim Rowley1-1/+60
2018-01-10swr/rast: autogenerate named structs instead of literal structsTim Rowley1-8/+15
2018-01-10swr/rast: SIMD16 fetch shader jitter cleanupTim Rowley1-720/+368
2018-01-10swr/rast: shuffle header files for msvc pre-compiled header usageTim Rowley10-88/+143
2018-01-10swr/rast: SIMD16 builder - cleanup naming (simd2 -> simd16)Tim Rowley5-233/+239
2018-01-10r600: don't emit tes samplers/views when tes isn't activeRoland Scheidegger2-0/+19
2018-01-10r600: increase number of UBOs to 15Roland Scheidegger3-22/+37
2018-01-10r600: use GET_BUFFER_RESINFO vtx fetch on eg instead of setting up constsRoland Scheidegger4-58/+50
2018-01-10r600: increase number of ubos by one to 14Roland Scheidegger4-4/+9
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-25 14:16:51 +0000