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path: root/src/gallium/drivers/freedreno
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2017-01-24gallium: Add integer 64 capabilityDave Airlie1-0/+1
v1.1: move to using a normal CAP. (Marek) v2: fill in the cap everywhere Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
2017-01-23gallium: add PIPE_CAP_TGSI_MUL_ZERO_WINSIlia Mirkin1-0/+1
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Axel Davy <axel.davy@ens.fr>
2017-01-22freedreno/a5xx: set frag shader threadsizeRob Clark1-2/+7
Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org>
2017-01-22freedreno/a5xx: set fragcoordxy properlyRob Clark1-1/+1
What a3xx docs call IJPERSPCENTERREGID.. the xy coord passed into bary.f. We were incorrectly setting both this and gl_FragCoord.xy to the same register resulting in all sorts of hilarity. Fixes stk, vdrift, 0ad, probably a bunch others. Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org>
2017-01-22freedreno/ir3: setup var locations in standalone compilerRob Clark1-1/+69
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-01-22freedreno/a5xx: fix psizeRob Clark2-8/+5
Note spritelist (POINTLIST_PSIZE) seems not to be a thing anymore on a5xx. Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org>
2017-01-22freedreno/a5xx: srgb fixRob Clark1-1/+2
Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org>
2017-01-22freedreno/a5xx: fix int vbosRob Clark1-1/+3
Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org>
2017-01-22freedreno/a5xx: fix clear for uint/sint formatsRob Clark1-19/+28
Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org>
2017-01-22freedreno/a5xx: fix cull stateRob Clark1-5/+5
Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org>
2017-01-22freedreno: update generated headersRob Clark6-13/+36
Signed-off-by: Rob Clark <robdclark@gmail.com> Cc: "17.0" <mesa-stable@lists.freedesktop.org>
2017-01-16gallium: add PIPE_CAP_TGSI_FS_FBFETCHIlia Mirkin1-1/+2
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-10freedreno: add "nogrow" debug paramRob Clark3-1/+4
Sometimes it is useful to disable the "growable" cmdstream buffers for debugging. (See 419a154d in libdrm) Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-01-10freedreno/a5xx: remove hack for glamorRob Clark1-3/+0
Now that issues glamor was hitting w/ glsl>=130 (aka missing INSTANCED bit in vertex attribute state) is fixed, remove hack. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-01-10freedreno/a5xx: fixed instancedRob Clark1-0/+1
Add missing bit, now that we know where it is. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-01-10freedreno/a5xx: use the non-_ZERO_BASE for vertexidRob Clark4-6/+20
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-01-10freedreno/a5xx: add texture MIPLVLSRob Clark1-3/+3
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-01-10freedreno/a5xx: fix fragcoord related hangsRob Clark2-2/+6
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-01-10freedreno: update generated headersRob Clark6-13/+22
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-01-05gallium: remove TGSI_OPCODE_ABSMarek Olšák1-5/+0
It's redundant with the source modifier. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-05gallium: add PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELYMarek Olšák1-0/+1
Drivers with good compilers don't need aggressive optimizations before TGSI. Reviewed-by: Eric Anholt <eric@anholt.net>
2016-12-30freedreno/ir3: rework varying slots (maybe??)Rob Clark1-4/+9
See: dEQP-GLES2.functional.shaders.swizzles.vector_swizzles.mediump_vec2_yyyy_fragment if we only access (in FS) varying.y then it ends up in slot zero.. I'm not sure the hw likes that.. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-29nir: Rename convert_to_ssa lower_regs_to_ssaJason Ekstrand1-1/+1
This matches the naming of nir_lower_vars_to_ssa, the other to-SSA pass.
2016-12-27freedreno/ir3: fix linkage::var sizeRob Clark1-1/+1
It should actually be 32 for a4xx/a5xx.. we still only advertise 16 but for a5xx the linkage map includes position/psize. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-27freedreno/ir3: treat clipvertex like a normal varyingRob Clark1-3/+1
We need this in case it is streamed out. Not sure why we were treating it specially before. Having it as a VS out is harmless if FS doesn't have a matching input. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-27freedreno/a5xx: transform-feedback supportRob Clark7-38/+209
We'll need to revisit when adding hw binning pass support, whether we can still do this in main draw step, as we do w/ a3xx/a4xx, or if we needed to move it to the binning stage. Still some failing piglits but most tests pass and the common cases seem to work. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-27freedreno: update generated headersRob Clark7-43/+81
Pull in a5xx streamout related regs. Also fixes a couple incorrect register definitions. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-27freedreno/ir3: UBO support for 64b GPUs (a5xx)Rob Clark1-3/+24
Update address calculation to support 64b addresses. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-27freedreno/ir3: rework location of driver constantsRob Clark6-53/+75
Rework how we lay out driver constants (driver-params, UBO/TFBO buffer addresses, immediates) for more flexibility. For a5xx+ we need to deal with the fact that gpu ptrs are 64b instead of 32b, which makes the fixed offset scheme not work so well. While we are dealing with that we might also make the layout more dynamic to account for varying # of UBOs, etc. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-27freedreno/a5xx: fix emit for bo addressesRob Clark1-3/+9
Reloc for the buffer address is two dwords on 64b devices (a5xx+) Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-27freedreno/a5xx: texture layoutRob Clark2-2/+2
Seems to be imilar to a4xx, and sampler state "array-pitch" needs to be aligned to page size. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: border color supportRob Clark1-3/+160
Not 100% sure it works if you have border color in VS.. but it might be right. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: use MRT0 to import linear zsRob Clark1-5/+20
A bit of a hack, but we need to do this until we can do tiled zs in sysmem (and associated tile/until blits for transfer_map). Fixes xonotic and glmark2 "refract", when reorder wasn't enabled. (reorder would paper over the issue by avoiding the extra round- trip to system memory and back to gmem. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno: fdN_gmem_restore_format() is not gen specificRob Clark8-50/+25
Refactor out into a common helper, since this is the same across generations when we need equiv z/s gmem restore format. Next patch needs this in a5xx, rather than creating yet another helper push this into core. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: cargo-cult end-batch sequence more faithfullyRob Clark4-4/+39
Fixes some issues at least with GMEM bypass mode, where we'd sometimes end up with some FS quads not hitting memory. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: misc fixRob Clark1-1/+1
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: fix (at least some) vtx formatsRob Clark1-1/+1
Swap/component-order doesn't seem to be quite what that is. At least blob was always setting it to XYZW ('11') but we weren't. Causing problems w/ formats like sint16.. Hard-coding this instead at least seems to get glamor working. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: more formatsRob Clark1-25/+25
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: fixup capsRob Clark2-6/+11
Might not be 100% accurate, mostly just copy from a4xx to get started. We are defn lying about occlusion query at this point (not implemented yet) but need it to expose anything higher than gl1.4 (glamor needs gl2.1) Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: fix random faults on first sysmem drawRob Clark1-0/+3
Not sure what this event is, but blob writes it.. and it seems to solve random write faults at mystery address that would sometimes happen on first BYPASS draw. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno: update generated headersRob Clark6-17/+80
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-18freedreno/a5xx: fix stride/size for mem->gmem blitsRob Clark1-5/+7
<brownpaperbag>these should be the in-GMEM dimensions</brownpaperbag> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-12treewide: s/comparitor/comparator/Ilia Mirkin1-1/+1
git grep -l comparitor | xargs sed -i 's/comparitor/comparator/g' Just happened to notice this in a patch that was sent and included one of the tokens in question. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-12-06freedreno/a5xx: fix draw packet size with index bufferRob Clark1-1/+1
gpuaddr of idx buffer is now two dwords (64b). Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06freedreno/a5xx: gmem bypass modeRob Clark1-0/+72
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06freedreno/a5xx: fix emit_string_marker()Rob Clark1-1/+4
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06freedreno: pitch alignment should match gmem alignmentRob Clark5-15/+22
Deal w/ differing gmem tile size alignment between generations, and make sure texture pitch matches. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06freedreno/a5xx: more formatsRob Clark1-41/+41
Bunch of stuff we can at least turn on for vbo formats. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06freedreno/a5xx: fix fragfaceRob Clark1-2/+4
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-06freedreno/a5xx: fix fragcoordRob Clark1-4/+11
Signed-off-by: Rob Clark <robdclark@gmail.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-22 19:13:55 +0000