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2017-09-09radeonsi: allow out-of-order rasterization in commutative blending casesout-of-orderNicolai Hähnle6-4/+73
We do not enable this by default for additive blending, since it slightly breaks OpenGL invariance guarantees due to non-determinism. Still, there may be some applications can benefit from white-listing via the radeonsi_commutative_blend_add drirc setting without any real visible artifacts.
2017-09-09radeonsi: add drirc option "radeonsi_assume_no_z_fights"Nicolai Hähnle5-4/+13
This option enables a performance optimization where typical non-blending draws with depth buffer may be rasterized out-of-order (on VI+, multi-SE chips). This optimization can lead to incorrect results when an applications renders multiple objects with the same Z value at the same pixel, so we will never enable it by default. But there may be applications that could benefit from white-listing.
2017-09-09radeonsi: enable out-of-order rasterization when possible on VI and GFX9 dGPUsNicolai Hähnle7-6/+193
This does not take commutative blending into account yet. R600_DEBUG=nooutoforder disables it.
2017-09-09gallium/radeon: pass old_(perfect_)enable to set_occlusion_query_stateNicolai Hähnle4-4/+11
The callee can derive the current enable state itself.
2017-09-09ac/surface: add radeon_surf::has_stencil for convenienceMarek Olšák11-14/+18
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07mesa/st/tests: Fix regressions with libunwind enabled introduced with 7be6d8fe12Gert Wollny1-0/+1
Add the according flags to link with libunwind. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=102565 Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07mesa/st/tests: Fix classic build regressions introduced with 7be6d8fe12Gert Wollny1-1/+6
Fixes the build in classic only mode, i.e. the new state tracker tests are only build when Gallium is enabled. Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07mesa/main: Fix GetTransformFeedbacki64 for glTransformFeedbackBufferBaseIago Toral Quiroga1-0/+22
The spec has special rules for querying buffer offsets and sizes when BindBufferBase is used, described in the OpenGL 4.6 spec, section 6.8 Buffer Object State: "To query the starting offset or size of the range of a buffer object binding in an indexed array, call GetInteger64i_v with target set to respectively the starting offset or binding size name from table 6.5 for that array. Index must be in the range zero to the number of bind points supported minus one. If the starting offset or size was not specified when the buffer object was bound (e.g. if it was bound with BindBufferBase), or if no buffer object is bound to the target array at index, zero is returned." Transform feedback buffer queries should follow the same rules, since it is the same case for them. There is a CTS test for this. Fixes: KHR-GL45.direct_state_access.xfb_buffers Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2017-09-07radeonsi: don't read tcs_out_lds_layout.patch_stride from an SGPRMarek Olšák1-6/+14
Same as before, writing TCS outputs to LDS is rare. Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07radeonsi: don't read tcs_out_lds_layout.vertex_size from an SGPRMarek Olšák3-6/+20
TCS outputs are usually not written to LDS, so no stats here. Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07radeonsi/gfx9: don't read LS out vertex stride from an SGPR in monolithic HSMarek Olšák2-1/+11
-44 bytes in a monolithic LS-HS binary. Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07radeonsi: don't read the LS output vertex stride from an SGPR in LSMarek Olšák1-4/+21
Now it's able to generate ds_write2_b64 instead of ds_write2_b32. -20 bytes in one shader binary. (having only 1 output) Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07radeonsi: don't read the number of TCS out vertices from an SGPR in TCSMarek Olšák1-2/+15
-16 bytes in one shader binary. Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07radeonsi: don't always apply the PrimID instancing bug workaround on SIMarek Olšák1-1/+1
It looks like commit 391673af7ad1565a5f6ac8fc2f8c9fcdd1fe9908 that should have fixed the perf regression didn't really change much if anything. Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07radeonsi: remove 2 callbacks from si_shader_contextMarek Olšák3-17/+13
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07winsys/amdgpu: disable local BOs on RavenMarek Olšák1-1/+2
It hangs with a high degree of reproducibility. Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07disk_cache: make the thread queue resizable and low priorityMarek Olšák1-6/+8
Acked-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07loader/dri3: Make sure we invalidate a drawable on size changeThomas Hellstrom1-0/+2
If we're seeing a drawable size change, in particular after processing a configure notify event, make sure we invalidate so that the state tracker picks up the new geometry. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2017-09-07loader/dri3: Process event after each fence waitThomas Hellstrom1-7/+10
This tries to mimic dri2 behaviour where events are typically processed while waiting for X replies. Since, during steady-state dri3 rendering, we seldom wait for xcb replies, and haven't enabled any automatic event processing, instead check for events after a fence wait. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2017-09-07st/mesa: skip draw calls with pipe_draw_info::count == 0Marek Olšák1-1/+6
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102502 Cc: 17.2 <mesa-stable@lists.freedesktop.org> Tested-by: Alexandre Demers <alexandre.f.demers@gmail.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-09-07docs: update envvar docs to reflect MESA_NO_ERROR changeEric Engestrom1-1/+1
I changed the behaviour earlier today, but forgot to update the corresponding docs. Fixes: 77713a0acb09f475d29f "mesa: allow user to set MESA_NO_ERROR=0" Suggested-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-09-07radv: do not use a bitfield when dirtying the vertex buffersSamuel Pitoiset2-3/+4
Useless to track which one has been updated because we re-upload all the vertex buffers in one shot. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-09-07radv: remove unused radv_meta_saved_state::vertex_saved fieldSamuel Pitoiset2-8/+0
It's always false. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-09-07mesa: allow user to set MESA_NO_ERROR=0Eric Engestrom1-1/+2
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102530 Cc: Michel Dänzer <michel@daenzer.net> Cc: Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2017-09-07util: rename include guard to avoid clashEric Engestrom1-3/+3
src/mesa/main/debug.h uses the same include guard. Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-07llvmpipe, tgsi: hook up dx10 gather4 opcodeRoland Scheidegger2-8/+25
Trivial. We already support tg4 for legacy tex opcodes, so the actual texture sampling code already handles it. (Just like TG4, we don't handle additional capabilities and always sample red channel.) Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2017-09-07llvmpipe, draw: increase shader cache limitsRoland Scheidegger2-4/+2
We're not particularly concerned with memory usage, if the tradeoff is shader recompiles. And it's common for apps to have a lot of shaders nowadays (and, since our shaders include a LOT of context state of course we may create quite a bit more shaders even). So quadruple the amount of shaders draw will cache (from 128 to 512). For llvmpipe (fs shaders) quadruple the number of instructions, keep the number of variants the same for now (only with very simple, non-texturing shaders the variant limit could really be reached), and simplify the definition, it's probably easier to just have one different definition per branch... Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2017-09-07ac/surface: reduce gfx9_surface_layout size.Dave Airlie1-2/+3
152->144. Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-09-07radv: reduce radv_amdgpu_winsys struct size.Dave Airlie1-3/+3
1168->1160. Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-09-07radv: reduce radv_image struct size.Dave Airlie1-3/+2
1480->1472. Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-09-07radv: reduce radv_shader_variant struct size.Dave Airlie1-1/+1
544->536 Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-09-07radv: reduce radv_cmd_state struct size.Dave Airlie1-2/+2
1632->1624. Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-09-07radv: reduce meta_saved_state struct size.Dave Airlie1-4/+3
904->896. Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-09-07nir: put compact into bitfields in nir_variable_dataDave Airlie1-1/+1
This being declared bool means it won't get merged with the previous bitfields, this seems like an oversight rather than deliberate. Noticed when running pahole. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-09-06anv: Annotate entrypoint table with index and func nameChad Versace1-2/+2
This helps when debugging a broken entrypoint table. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-09-06radeon/uvd: fix the assertion check for YUYV formatLeo Liu1-3/+5
Fixes:7319ff87("radeon/uvd: add YUYV format support for target buffer") Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2017-09-06intel: Add brand string for KBL-RAnuj Phogat1-1/+1
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-09-06intel: Remove unused device info for KBL GT1.5Anuj Phogat1-11/+0
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-09-06intel: Change a KBL pci id to GT2 from GT1.5Anuj Phogat1-1/+1
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-09-06intel: Fix few KBL brand stringsAnuj Phogat1-2/+2
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-09-06intel: Remove unused Kabylake pci idsAnuj Phogat1-7/+0
These PCI IDs are not used in any Kabylake SKUs. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-09-06Revert "Android: add -Wno-date-time flag for clang"Emil Velikov1-1/+0
This reverts commit 6dae9176d60d12de61aa03906c44f81e20ef7622. No longer needed as of last commit. Cc: Rob Herring <robh@kernel.org>
2017-09-06mesa: replace date/time macros with MESA_GIT_SHA1Emil Velikov1-3/+7
Former is non-deterministic, results in non-reproducible builds and compilers throw a warning about it. Cc: Rob Herring <robh@kernel.org> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-09-06mesa: don't use %s for PACKAGE_VERSION macroEmil Velikov2-4/+4
The macro itself is a well defined string, which cannot cause issues with printf or other printf-like functions. All other places through Mesa already use it directly, so let's update the final two instances. Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-09-06docs/release-calendar: update and extendEmil Velikov1-16/+16
v2: Correct 17.1.10 version, adjust some names. v3: Add missing <tr> (Andres) Cc: Juan A. Suárez <jasuarez@igalia.com> Cc: Andres Gomez <agomez@igalia.com> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Andres Gomez <agomez@igalia.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
2017-09-06docs/releasing: polish LLVM_CONFIG wording/handlingEmil Velikov1-5/+8
Use consistent way to manage "non-default" llvm installations, clearly documenting it. AKA, use LLVM_CONFIG throughout and unset for the Windows/mingw builds. v2: unset the save_ variable (Andres) Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Andres Gomez <agomez@igalia.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
2017-09-06docs/releasing: remove -jX instancesEmil Velikov1-2/+3
One can control the number of jobs via MAKEFLAGS. As such there's little reason to set the number of jobs for each make invocation. Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Andres Gomez <agomez@igalia.com> Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-09-06.gitignore: list *.orig and *.rejEmil Velikov1-0/+2
Should prevent accidental check-in of patch artefacts. Suggested-by: Mike Lothian <mike@fireburn.co.uk> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2017-09-06egl/x11: advertise __DRI_USE_INVALIDATE for DRI2Emil Velikov1-0/+1
Back in 2012 (commit 1e7776ca2bc - egl: Remove bogus invalidate code.) the loader use of invalidate() was purged as "bogus". One of the factors defining that statement was the lack of the loader-side invalidate extension - __DRI_USE_INVALIDATE. Since then the commit was reverted (commit eed0a80137d - egl: Restore "bogus" DRI2 invalidate event code.), always performing the driver invalidate call, although the loader was never updated to expose the extension. Do so allowing the driver to do fine grained tuning. Cc: Eric Anholt <eric@anholt.net> Cc: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Anholt <eric@anholt.net
2017-09-06egl/x11/dri3: adding missing __DRI_BACKGROUND_CALLABLE extensionEmil Velikov1-0/+1
Fixes: 3b7b6adf3ac ("egl: Implement __DRI_BACKGROUND_CALLABLE") Cc: Timothy Arceri <tarceri@itsqueeze.com> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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