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2017-07-05radeonsi: translate NIR to LLVMNicolai Hähnle4-4/+22
2017-07-05radeonsi: dump NIR instead of TGSI when appropriateNicolai Hähnle1-1/+5
2017-07-05radeonsi: bypass the shader cache for NIR shadersNicolai Hähnle1-2/+3
2017-07-05radeonsi: scan NIR shaders to obtain required infoNicolai Hähnle5-6/+335
2017-07-05ac/nir: add ac_shader_abi::inputsNicolai Hähnle2-0/+9
2017-07-05ac/nir: begin splitting off ac_nir_contextNicolai Hähnle2-201/+254
The eventual goal is to hide all radv-specific details behind ac_nir_context::abi, so that the NIR->LLVM code can be re-used by radeonsi. During development, we live with a partial split, where some of the NIR->LLVM code still relies on linking back to the nir_to_llvm_context (which should ultimately be renamed to reflect that it's radv-specific). The idea is to get rid of these backlinks over time.
2017-07-05radeonsi: add si_shader_selector::nirNicolai Hähnle1-0/+3
2017-07-05radeonsi: implement pipe_screen::get_compiler_options for NIRNicolai Hähnle1-0/+33
2017-07-05radeonsi: add nir include pathsNicolai Hähnle1-0/+1
2017-07-05ac/nir: start using ac_shader_abiNicolai Hähnle1-20/+18
v2: update for LLVMValueRefs in ac_shader_abi
2017-07-05ac,radeonsi: move some VS input descriptions to ac_shader_abiNicolai Hähnle3-31/+77
v2: use LLVM values instead of function parameter indices Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
2017-07-05radeonsi: store shader function arguments in a structureNicolai Hähnle1-298/+320
Aligns the code a bit more with ac/nir, and simplifies the setup of ac_shader_abi.
2017-07-05gallium/targets: link against NIR when building radeonsiNicolai Hähnle6-0/+8
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-07-05st/glsl_to_nir: move nir_lower_io to driversNicolai Hähnle3-2/+10
This allows drivers more freedom in how exactly they want to lower I/O, e.g. first lowering I/O to temporaries.
2017-07-05st/mesa: get rid of st_glsl_typesNicolai Hähnle10-173/+42
It's a duplicate of glsl_type::count_attribute_slots.
2017-07-05st/glsl_to_nir: use nir_lower_samplers_as_deref when requested by the driverNicolai Hähnle1-1/+6
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-07-05st/glsl_to_nir: fix the case where NIR clone testing is enabledNicolai Hähnle1-1/+2
In that case, prog->nir must be assigned at the end.
2017-07-05gallium: add PIPE_CAP_NIR_SAMPLERS_AS_DEREFNicolai Hähnle17-0/+18
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-07-05nir: add nir_lower_uniforms_to_ubo passNicolai Hähnle3-0/+99
This is a further lowering of default-block uniform loads that transforms load_uniform intrinsics into load_ubo intrinsics. This simplies the rest of the backend. v2: transform from load_uniform instead of straight from variables
2017-07-05nir: add nir_lower_samplers_as_deref passNicolai Hähnle5-0/+255
This pass is a replacement for the nir_lower_samplers pass, which has the advantage of keeping sampler references as derefs. This allows a unified treatment of texture instructions and image intrinsics in the backend.
2017-07-05nir: add load_frag_coord system value intrinsicNicolai Hähnle3-0/+6
Some drivers prefer to treat gl_FragCoord as a system value rather than a fragment shader input, see Const.GLSLFragCoordIsSysVal.
2017-07-05nir: fix nir_lower_wpos_ytransform when gl_FragCoord is a system valueNicolai Hähnle1-2/+4
2017-07-05nir: add nir_instr_rewrite_derefNicolai Hähnle2-0/+15
Allows modifying a texture instruction's texture and sampler derefs.
2017-07-05st/glsl_to_nir: fix edgeflag passthroughNicolai Hähnle2-1/+6
We have to mark the additional shader input as used, otherwise it will be eliminated, and we have to setup its index correctly. This is a bit of a hack, but so is everything surrounding edgeflag passthrough. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-07-05st/mesa: use pipe_shader_type_from_mesaNicolai Hähnle1-21/+2
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-07-05tgsi_from_mesa: add tgsi_get_gl_frag_result_semanticNicolai Hähnle2-0/+40
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-07-05tgsi_from_mesa: add pipe_shader_type_from_mesaNicolai Hähnle1-0/+23
So... the pipe_ prefix doesn't really fit into a TGSI header; on the other hand, the return type has the pipe_ prefix. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-07-05tgsi,st/mesa: move varying slot to semantic mapping into a helper for VSNicolai Hähnle5-99/+203
We will use this helper in radeonsi's NIR path. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-07-05ddebug: handle some cases of non-TGSI shadersNicolai Hähnle3-6/+28
NIR shaders are not captured properly in pipelined mode currently. This would require shader cloning, which requires linking all the Gallium drivers against NIR. We can always do that later. v2: avoid immediate crashes in pipelined mode Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
2017-07-05glsl_to_nir: zero-initialize var->data.descriptor_setNicolai Hähnle1-0/+1
This is convenient for backends that support both Vulkan and OpenGL while lowering samplers to derefs with nir_lower_samplers_as_deref. Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-07-05glsl: add glsl_base_type_is_integerNicolai Hähnle1-0/+11
We will use this from radeonsi/nir, which we want to keep as pure C code. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-07-05nir: add NIR_PRINT environment variableNicolai Hähnle1-0/+19
Reviewed-by: Rob Clark <robdclark@gmail.com>
2017-07-05glsl/blob: add valgrind checks that written data is definedNicolai Hähnle2-0/+13
Undefined data will eventually trigger a valgrind error while computing its CRC32 while writing it into the disk cache, but at that point, it is basically impossible to track down where the undefined data came from. With this change, finding the origin of undefined data becomes easy. v2: remove duplicate VALGRIND_CFLAGS (Emil) Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-07-05glsl: explicitly zero out padding to gl_shader_variable bitfieldNicolai Hähnle1-1/+4
Otherwise, the padding bits remain undefined, which leads to valgrind errors when storing the gl_shader_variable in the disk cache. v2: use rzalloc instead of an explicit padding member variable Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-07-05glsl: simplify add_uniform_to_shader::visit_fieldNicolai Hähnle1-6/+5
Each field gets a distinct name, so we should never hit the case where the name already exists in the parameter list. Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-07-05glsl: look for multiple variables simultaneously with find_assignment_visitorNicolai Hähnle1-41/+81
Save some passes over the IR. v2: redesign to make the users of find_assignments more readable v3: - fix missing ! - add some comments and make the num_found check more explicit (Timothy) Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1) Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-07-05gallium/radeon: fix VDPAU breakage, need VRAM with WCMarek Olšák1-1/+2
2017-07-04a5xx: enable polygon offset clampsIlia Mirkin1-1/+3
This is already set and emitted by the code. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04a5xx: implement logicop supportIlia Mirkin3-7/+13
The former 0x60 hardcoded in is equivalent to ROP_COPY with the shift. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04a5xx: enable polygon mode selectionIlia Mirkin4-7/+24
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04a5xx: disable ARB_depth_clamp for nowIlia Mirkin1-1/+3
We need to figure out how to implement it properly. Right now it doesn't work at all. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04a5xx: fix clip_halfz supportIlia Mirkin3-4/+7
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04a5xx: improve 3d texture samplingIlia Mirkin1-3/+0
At least the first level works now. Eventually the later levels stop working, there appears to be some alignment issue. But this improves the situation immensely. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04a5xx: remove one of the MIPFILTER_LINEAR bitsIlia Mirkin1-1/+0
It doesn't appear to do what we want. Removing this bit makes lodclamp-between as well as a number of dEQP tests pass, with no visible ill effect. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04a5xx: enable formats newly added to the headersIlia Mirkin1-69/+69
This enables S3TC, BPTC, ETC2, and ASTC texture decoding. Additionally this enables RGB32 texture buffer objects, as well as 11_11_10_FLOAT and 10_10_10_2 vertex formats (and related extensions). Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04a5xx: include color swap when decoding verticesIlia Mirkin1-0/+1
This fixes support for BGRA vertex formats Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04a5xx: update headersIlia Mirkin1-10/+47
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04gallium/radeon: attempt to fix a compiler failure in radeon_winsys.hMarek Olšák1-1/+1
trivial.
2017-07-04winsys/amdgpu: use 128KB BOs for suballocations of up to 64KB BOsMarek Olšák2-3/+5
This decreases the number of BOs, but might also increase memory usage. It's better for small textures. The gameplay is on the far right: https://people.freedesktop.org/~mareko/suballoc.svg Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04gallium/radeon: allow suballocating texturesMarek Olšák2-1/+15
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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