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-rw-r--r--src/amd/common/ac_nir_to_llvm.h97
-rw-r--r--src/amd/vulkan/radv_cmd_buffer.c14
-rw-r--r--src/amd/vulkan/radv_nir_to_llvm.c29
-rw-r--r--src/amd/vulkan/radv_pipeline.c22
-rw-r--r--src/amd/vulkan/radv_pipeline_cache.c2
-rw-r--r--src/amd/vulkan/radv_private.h12
-rw-r--r--src/amd/vulkan/radv_shader.h99
7 files changed, 139 insertions, 136 deletions
diff --git a/src/amd/common/ac_nir_to_llvm.h b/src/amd/common/ac_nir_to_llvm.h
index 4d48f7ebdd..0e4d0e302a 100644
--- a/src/amd/common/ac_nir_to_llvm.h
+++ b/src/amd/common/ac_nir_to_llvm.h
@@ -89,13 +89,6 @@ struct ac_nir_compiler_options {
enum chip_class chip_class;
};
-struct ac_userdata_info {
- int8_t sgpr_idx;
- uint8_t num_sgprs;
- bool indirect;
- uint32_t indirect_offset;
-};
-
enum ac_ud_index {
AC_UD_SCRATCH_RING_OFFSETS = 0,
AC_UD_PUSH_CONSTANTS = 1,
@@ -124,96 +117,6 @@ enum ac_ud_index {
#define INTERP_CENTROID 1
#define INTERP_SAMPLE 2
-/* descriptor index into scratch ring offsets */
-#define RING_SCRATCH 0
-#define RING_ESGS_VS 1
-#define RING_ESGS_GS 2
-#define RING_GSVS_VS 3
-#define RING_GSVS_GS 4
-#define RING_HS_TESS_FACTOR 5
-#define RING_HS_TESS_OFFCHIP 6
-#define RING_PS_SAMPLE_POSITIONS 7
-
-// Match MAX_SETS from radv_descriptor_set.h
-#define AC_UD_MAX_SETS MAX_SETS
-
-struct ac_userdata_locations {
- struct ac_userdata_info descriptor_sets[AC_UD_MAX_SETS];
- struct ac_userdata_info shader_data[AC_UD_MAX_UD];
-};
-
-struct ac_vs_output_info {
- uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
- uint8_t clip_dist_mask;
- uint8_t cull_dist_mask;
- uint8_t param_exports;
- bool writes_pointsize;
- bool writes_layer;
- bool writes_viewport_index;
- bool export_prim_id;
- unsigned pos_exports;
-};
-
-struct ac_es_output_info {
- uint32_t esgs_itemsize;
-};
-
-struct ac_shader_variant_info {
- struct ac_userdata_locations user_sgprs_locs;
- struct ac_shader_info info;
- unsigned num_user_sgprs;
- unsigned num_input_sgprs;
- unsigned num_input_vgprs;
- unsigned private_mem_vgprs;
- bool need_indirect_descriptor_sets;
- struct {
- struct {
- struct ac_vs_output_info outinfo;
- struct ac_es_output_info es_info;
- unsigned vgpr_comp_cnt;
- bool as_es;
- bool as_ls;
- uint64_t outputs_written;
- } vs;
- struct {
- unsigned num_interp;
- uint32_t input_mask;
- uint32_t flat_shaded_mask;
- bool can_discard;
- bool early_fragment_test;
- } fs;
- struct {
- unsigned block_size[3];
- } cs;
- struct {
- unsigned vertices_in;
- unsigned vertices_out;
- unsigned output_prim;
- unsigned invocations;
- unsigned gsvs_vertex_size;
- unsigned max_gsvs_emit_size;
- unsigned es_type; /* GFX9: VS or TES */
- } gs;
- struct {
- unsigned tcs_vertices_out;
- /* Which outputs are actually written */
- uint64_t outputs_written;
- /* Which patch outputs are actually written */
- uint32_t patch_outputs_written;
-
- } tcs;
- struct {
- struct ac_vs_output_info outinfo;
- struct ac_es_output_info es_info;
- bool as_es;
- unsigned primitive_mode;
- enum gl_tess_spacing spacing;
- bool ccw;
- bool point_mode;
- } tes;
- };
-};
-
static inline unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
{
return (index * 4) + chan;
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 3e0ed0e9a9..cadb06f0af 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -540,7 +540,7 @@ radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
}
-struct ac_userdata_info *
+struct radv_userdata_info *
radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
gl_shader_stage stage,
int idx)
@@ -567,7 +567,7 @@ radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
gl_shader_stage stage,
int idx, uint64_t va)
{
- struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
+ struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
uint32_t base_reg = pipeline->user_data_0[stage];
if (loc->sgpr_idx == -1)
return;
@@ -1236,7 +1236,7 @@ emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
uint64_t va,
gl_shader_stage stage)
{
- struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
+ struct radv_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
uint32_t base_reg = pipeline->user_data_0[stage];
if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
@@ -2290,7 +2290,7 @@ void radv_CmdBindPipeline(
cmd_buffer->tess_rings_needed = true;
if (radv_pipeline_has_gs(pipeline)) {
- struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
+ struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
AC_UD_SCRATCH_RING_OFFSETS);
if (cmd_buffer->ring_offsets_idx == -1)
cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
@@ -2716,7 +2716,7 @@ static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned in
for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
if (!pipeline->shaders[stage])
continue;
- struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
+ struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
if (loc->sgpr_idx == -1)
continue;
uint32_t base_reg = pipeline->user_data_0[stage];
@@ -2724,7 +2724,7 @@ static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned in
}
if (pipeline->gs_copy_shader) {
- struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
+ struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
if (loc->sgpr_idx != -1) {
uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
@@ -3207,7 +3207,7 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
struct radeon_winsys *ws = cmd_buffer->device->ws;
struct radeon_winsys_cs *cs = cmd_buffer->cs;
- struct ac_userdata_info *loc;
+ struct radv_userdata_info *loc;
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
AC_UD_CS_GRID_SIZE);
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 8779c9d2b1..9551def55e 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -26,6 +26,7 @@
*/
#include "radv_private.h"
+#include "radv_shader.h"
#include "nir/nir.h"
#include <llvm-c/Core.h>
@@ -46,14 +47,14 @@
struct radv_shader_context {
struct ac_llvm_context ac;
const struct ac_nir_compiler_options *options;
- struct ac_shader_variant_info *shader_info;
+ struct radv_shader_variant_info *shader_info;
struct ac_shader_abi abi;
unsigned max_workgroup_size;
LLVMContextRef context;
LLVMValueRef main_function;
- LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
+ LLVMValueRef descriptor_sets[RADV_UD_MAX_SETS];
LLVMValueRef ring_offsets;
LLVMValueRef vertex_buffers;
@@ -352,7 +353,7 @@ create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
static void
-set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
+set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
uint32_t indirect_offset)
{
ud_info->sgpr_idx = *sgpr_idx;
@@ -366,7 +367,7 @@ static void
set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
uint8_t num_sgprs)
{
- struct ac_userdata_info *ud_info =
+ struct radv_userdata_info *ud_info =
&ctx->shader_info->user_sgprs_locs.shader_data[idx];
assert(ud_info);
@@ -377,7 +378,7 @@ static void
set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
uint32_t indirect_offset)
{
- struct ac_userdata_info *ud_info =
+ struct radv_userdata_info *ud_info =
&ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
assert(ud_info);
@@ -2163,7 +2164,7 @@ radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
static void
handle_vs_outputs_post(struct radv_shader_context *ctx,
bool export_prim_id,
- struct ac_vs_output_info *outinfo)
+ struct radv_vs_output_info *outinfo)
{
uint32_t param_count = 0;
unsigned target;
@@ -2348,7 +2349,7 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
static void
handle_es_outputs_post(struct radv_shader_context *ctx,
- struct ac_es_output_info *outinfo)
+ struct radv_es_output_info *outinfo)
{
int j;
uint64_t max_output_written = 0;
@@ -2862,7 +2863,7 @@ static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
static void
ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
{
- struct ac_vs_output_info *outinfo;
+ struct radv_vs_output_info *outinfo;
switch (ctx->stage) {
case MESA_SHADER_FRAGMENT:
@@ -2976,7 +2977,7 @@ static
LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
struct nir_shader *const *shaders,
int shader_count,
- struct ac_shader_variant_info *shader_info,
+ struct radv_shader_variant_info *shader_info,
const struct ac_nir_compiler_options *options,
bool dump_shader)
{
@@ -3008,7 +3009,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
for(int i = 0; i < shader_count; ++i)
ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
- for (i = 0; i < AC_UD_MAX_SETS; i++)
+ for (i = 0; i < RADV_UD_MAX_SETS; i++)
shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
for (i = 0; i < AC_UD_MAX_UD; i++)
shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
@@ -3216,7 +3217,7 @@ static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
LLVMModuleRef llvm_module,
struct ac_shader_binary *binary,
struct ac_shader_config *config,
- struct ac_shader_variant_info *shader_info,
+ struct radv_shader_variant_info *shader_info,
gl_shader_stage stage,
bool dump_shader, bool supports_spill)
{
@@ -3295,7 +3296,7 @@ static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
}
static void
-ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
+ac_fill_shader_info(struct radv_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
{
switch (nir->info.stage) {
case MESA_SHADER_COMPUTE:
@@ -3337,7 +3338,7 @@ void
radv_compile_nir_shader(LLVMTargetMachineRef tm,
struct ac_shader_binary *binary,
struct ac_shader_config *config,
- struct ac_shader_variant_info *shader_info,
+ struct radv_shader_variant_info *shader_info,
struct nir_shader *const *nir,
int nir_count,
const struct ac_nir_compiler_options *options,
@@ -3407,7 +3408,7 @@ radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
struct nir_shader *geom_shader,
struct ac_shader_binary *binary,
struct ac_shader_config *config,
- struct ac_shader_variant_info *shader_info,
+ struct radv_shader_variant_info *shader_info,
const struct ac_nir_compiler_options *options,
bool dump_shader)
{
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f8f09a7e16..acb46ec12f 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1126,8 +1126,8 @@ calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_pipeline *pipeline)
{
struct radv_gs_state gs = {0};
- struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
- struct ac_es_output_info *es_info;
+ struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
+ struct radv_es_output_info *es_info;
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info;
else
@@ -1254,7 +1254,7 @@ calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_sta
unsigned alignment = 256 * num_se;
/* The maximum size is 63.999 MB per SE. */
unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
- struct ac_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
+ struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
/* Calculate the minimum size. */
unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
@@ -1478,7 +1478,7 @@ static const struct radv_prim_vertex_count prim_size_table[] = {
[V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
};
-static const struct ac_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
+static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
{
if (radv_pipeline_has_gs(pipeline))
return &pipeline->gs_copy_shader->info.vs.outinfo;
@@ -2383,7 +2383,7 @@ radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
uint32_t offset;
- struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
+ struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
if (loc->sgpr_idx == -1)
return;
@@ -2415,7 +2415,7 @@ static void
radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
const struct radv_pipeline *pipeline)
{
- const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
+ const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
uint32_t vgt_primitiveid_en = false;
uint32_t vgt_gs_mode = 0;
@@ -2448,7 +2448,7 @@ radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
radeon_emit(cs, shader->rsrc1);
radeon_emit(cs, shader->rsrc2);
- const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
+ const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
unsigned clip_dist_mask, cull_dist_mask, total_mask;
clip_dist_mask = outinfo->clip_dist_mask;
cull_dist_mask = outinfo->cull_dist_mask;
@@ -2609,7 +2609,7 @@ radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
tess->ls_hs_config);
- struct ac_userdata_info *loc;
+ struct radv_userdata_info *loc;
loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
if (loc->sgpr_idx != -1) {
@@ -2705,7 +2705,7 @@ radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
radv_pipeline_generate_hw_vs(cs, pipeline, pipeline->gs_copy_shader);
- struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
+ struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_GEOMETRY,
AC_UD_GS_VS_RING_STRIDE_ENTRIES);
if (loc->sgpr_idx != -1) {
uint32_t stride = gs->info.gs.max_gsvs_emit_size;
@@ -2745,7 +2745,7 @@ radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
struct radv_pipeline *pipeline)
{
struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
- const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
+ const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
uint32_t ps_input_cntl[32];
unsigned ps_offset = 0;
@@ -3220,7 +3220,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
- struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
+ struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
AC_UD_VS_BASE_VERTEX_START_INSTANCE);
if (loc->sgpr_idx != -1) {
pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
diff --git a/src/amd/vulkan/radv_pipeline_cache.c b/src/amd/vulkan/radv_pipeline_cache.c
index 7205a3d896..920afd3938 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -32,7 +32,7 @@
#include "ac_nir_to_llvm.h"
struct cache_entry_variant_info {
- struct ac_shader_variant_info variant_info;
+ struct radv_shader_variant_info variant_info;
struct ac_shader_config config;
uint32_t rsrc1, rsrc2;
};
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 22850c81d6..23815b9ccd 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1249,9 +1249,9 @@ static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
}
-struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
- gl_shader_stage stage,
- int idx);
+struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
+ gl_shader_stage stage,
+ int idx);
struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
@@ -1678,18 +1678,20 @@ struct radv_fence {
};
/* radv_nir_to_llvm.c */
+struct radv_shader_variant_info;
+
void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
struct nir_shader *geom_shader,
struct ac_shader_binary *binary,
struct ac_shader_config *config,
- struct ac_shader_variant_info *shader_info,
+ struct radv_shader_variant_info *shader_info,
const struct ac_nir_compiler_options *options,
bool dump_shader);
void radv_compile_nir_shader(LLVMTargetMachineRef tm,
struct ac_shader_binary *binary,
struct ac_shader_config *config,
- struct ac_shader_variant_info *shader_info,
+ struct radv_shader_variant_info *shader_info,
struct nir_shader *const *nir,
int nir_count,
const struct ac_nir_compiler_options *options,
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index b07f8a89e7..b0517b73a4 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -33,6 +33,19 @@
#include "nir/nir.h"
+/* descriptor index into scratch ring offsets */
+#define RING_SCRATCH 0
+#define RING_ESGS_VS 1
+#define RING_ESGS_GS 2
+#define RING_GSVS_VS 3
+#define RING_GSVS_GS 4
+#define RING_HS_TESS_FACTOR 5
+#define RING_HS_TESS_OFFCHIP 6
+#define RING_PS_SAMPLE_POSITIONS 7
+
+// Match MAX_SETS from radv_descriptor_set.h
+#define RADV_UD_MAX_SETS MAX_SETS
+
struct radv_shader_module {
struct nir_shader *nir;
unsigned char sha1[20];
@@ -40,6 +53,90 @@ struct radv_shader_module {
char data[0];
};
+struct radv_userdata_info {
+ int8_t sgpr_idx;
+ uint8_t num_sgprs;
+ bool indirect;
+ uint32_t indirect_offset;
+};
+
+struct radv_userdata_locations {
+ struct radv_userdata_info descriptor_sets[RADV_UD_MAX_SETS];
+ struct radv_userdata_info shader_data[AC_UD_MAX_UD];
+};
+
+struct radv_vs_output_info {
+ uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
+ uint8_t clip_dist_mask;
+ uint8_t cull_dist_mask;
+ uint8_t param_exports;
+ bool writes_pointsize;
+ bool writes_layer;
+ bool writes_viewport_index;
+ bool export_prim_id;
+ unsigned pos_exports;
+};
+
+struct radv_es_output_info {
+ uint32_t esgs_itemsize;
+};
+
+struct radv_shader_variant_info {
+ struct radv_userdata_locations user_sgprs_locs;
+ struct ac_shader_info info;
+ unsigned num_user_sgprs;
+ unsigned num_input_sgprs;
+ unsigned num_input_vgprs;
+ unsigned private_mem_vgprs;
+ bool need_indirect_descriptor_sets;
+ struct {
+ struct {
+ struct radv_vs_output_info outinfo;
+ struct radv_es_output_info es_info;
+ unsigned vgpr_comp_cnt;
+ bool as_es;
+ bool as_ls;
+ uint64_t outputs_written;
+ } vs;
+ struct {
+ unsigned num_interp;
+ uint32_t input_mask;
+ uint32_t flat_shaded_mask;
+ bool can_discard;
+ bool early_fragment_test;
+ } fs;
+ struct {
+ unsigned block_size[3];
+ } cs;
+ struct {
+ unsigned vertices_in;
+ unsigned vertices_out;
+ unsigned output_prim;
+ unsigned invocations;
+ unsigned gsvs_vertex_size;
+ unsigned max_gsvs_emit_size;
+ unsigned es_type; /* GFX9: VS or TES */
+ } gs;
+ struct {
+ unsigned tcs_vertices_out;
+ /* Which outputs are actually written */
+ uint64_t outputs_written;
+ /* Which patch outputs are actually written */
+ uint32_t patch_outputs_written;
+
+ } tcs;
+ struct {
+ struct radv_vs_output_info outinfo;
+ struct radv_es_output_info es_info;
+ bool as_es;
+ unsigned primitive_mode;
+ enum gl_tess_spacing spacing;
+ bool ccw;
+ bool point_mode;
+ } tes;
+ };
+};
+
struct radv_shader_variant {
uint32_t ref_count;
@@ -47,7 +144,7 @@ struct radv_shader_variant {
uint64_t bo_offset;
struct ac_shader_config config;
uint32_t code_size;
- struct ac_shader_variant_info info;
+ struct radv_shader_variant_info info;
unsigned rsrc1;
unsigned rsrc2;
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-21 19:13:08 +0000