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-rw-r--r--src/amd/common/r600d_common.h10
-rw-r--r--src/gallium/drivers/radeon/r600_query.c9
-rw-r--r--src/gallium/drivers/radeonsi/si_perfcounter.c3
-rw-r--r--src/gallium/drivers/radeonsi/si_state_draw.c6
4 files changed, 16 insertions, 12 deletions
diff --git a/src/amd/common/r600d_common.h b/src/amd/common/r600d_common.h
index 0b61215f2b..57757469e5 100644
--- a/src/amd/common/r600d_common.h
+++ b/src/amd/common/r600d_common.h
@@ -68,12 +68,10 @@
#define PKT3_EVENT_WRITE 0x46
#define PKT3_EVENT_WRITE_EOP 0x47
#define EOP_DATA_SEL(x) ((x) << 29)
- /* 0 - discard
- * 1 - send low 32bit data
- * 2 - send 64bit data
- * 3 - send 64bit GPU counter value
- * 4 - send 64bit sys counter value
- */
+#define EOP_DATA_SEL_DISCARD 0
+#define EOP_DATA_SEL_VALUE_32BIT 1
+#define EOP_DATA_SEL_VALUE_64BIT 2
+#define EOP_DATA_SEL_TIMESTAMP 3
#define PKT3_RELEASE_MEM 0x49 /* GFX9+ */
#define PKT3_SET_CONFIG_REG 0x68
#define PKT3_SET_CONTEXT_REG 0x69
diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c
index 98bdd80d73..ca04872267 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -778,7 +778,8 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
* (bottom-of-pipe)
*/
r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
- 0, 3, NULL, va, 0, query->b.type);
+ 0, EOP_DATA_SEL_TIMESTAMP,
+ NULL, va, 0, query->b.type);
}
break;
case PIPE_QUERY_PIPELINE_STATISTICS:
@@ -863,7 +864,8 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
/* fall through */
case PIPE_QUERY_TIMESTAMP:
r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
- 0, 3, NULL, va, 0, query->b.type);
+ 0, EOP_DATA_SEL_TIMESTAMP, NULL, va,
+ 0, query->b.type);
fence_va = va + 8;
break;
case PIPE_QUERY_PIPELINE_STATISTICS: {
@@ -885,7 +887,8 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
RADEON_PRIO_QUERY);
if (fence_va)
- r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, 1,
+ r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
+ EOP_DATA_SEL_VALUE_32BIT,
query->buffer.buf, fence_va, 0x80000000,
query->b.type);
}
diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c
index aa09e0ef6a..4a543ea244 100644
--- a/src/gallium/drivers/radeonsi/si_perfcounter.c
+++ b/src/gallium/drivers/radeonsi/si_perfcounter.c
@@ -614,7 +614,8 @@ static void si_pc_emit_stop(struct r600_common_context *ctx,
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
- r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, 1,
+ r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
+ EOP_DATA_SEL_VALUE_32BIT,
buffer, va, 0, R600_NOT_QUERY);
r600_gfx_wait_fence(ctx, va, 0, 0xffffffff);
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 3bec639687..ebc362ed03 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -899,7 +899,8 @@ void si_emit_cache_flush(struct si_context *sctx)
/* Necessary for DCC */
if (rctx->chip_class == VI)
r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
- 0, 0, NULL, 0, 0, R600_NOT_QUERY);
+ 0, EOP_DATA_SEL_DISCARD, NULL,
+ 0, 0, R600_NOT_QUERY);
}
if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
@@ -998,7 +999,8 @@ void si_emit_cache_flush(struct si_context *sctx)
va = sctx->wait_mem_scratch->gpu_address;
sctx->wait_mem_number++;
- r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags, 1,
+ r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags,
+ EOP_DATA_SEL_VALUE_32BIT,
sctx->wait_mem_scratch, va,
sctx->wait_mem_number, R600_NOT_QUERY);
r600_gfx_wait_fence(rctx, va, sctx->wait_mem_number, 0xffffffff);