diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2017-10-07 20:50:16 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2017-10-09 16:24:21 +0200 |
| commit | ed7f27ded85991cbfed3e2a18f4dda0e3b35b31c (patch) | |
| tree | e5790232872956d97b5ac197a5f94b8397cd3dfc /src | |
| parent | 8e969cce382951b92529ea427216a31aaa6a47fb (diff) | |
radeonsi: add performance thresholds for CP DMA, decrease it for clears
The first one isn't used yet.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_cp_dma.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c index 064f6c02cc..97adc27e7d 100644 --- a/src/gallium/drivers/radeonsi/si_cp_dma.c +++ b/src/gallium/drivers/radeonsi/si_cp_dma.c @@ -28,6 +28,12 @@ #include "sid.h" #include "radeon/r600_cs.h" +/* Recommended maximum sizes for optimal performance. + * Fall back to compute or SDMA if the size is greater. + */ +#define CP_DMA_COPY_PERF_THRESHOLD (64 * 1024) /* copied from Vulkan */ +#define CP_DMA_CLEAR_PERF_THRESHOLD (32 * 1024) /* guess (clear is much slower) */ + /* Set this if you want the ME to wait until CP DMA is done. * It should be set on the last CP DMA packet. */ #define CP_DMA_SYNC (1 << 0) @@ -230,7 +236,7 @@ static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst, (offset % 4 == 0) && /* CP DMA is very slow. Always use SDMA for big clears. This * alone improves DeusEx:MD performance by 70%. */ - (size > 128 * 1024 || + (size > CP_DMA_CLEAR_PERF_THRESHOLD || /* Buffers not used by the GFX IB yet will be cleared by SDMA. * This happens to move most buffer clears to SDMA, including * DCC and CMASK clears, because pipe->clear clears them before |