amd/common: pass chip_class to ac_dump_reg

Acked-by: Marek Olšák <marek.olsak@amd.com>

3 files changed, 75 insertions, 60 deletions

diff --git a/src/amd/common/ac_debug.c b/src/amd/common/ac_debug.c
index 0de00e27e7..570ba85085 100644
--- a/src/amd/common/ac_debug.c
+++ b/src/amd/common/ac_debug.c
@@ -101,8 +101,8 @@ static void print_named_value(FILE *file, const char *name, uint32_t value,
 	print_value(file, value, bits);
 }
 
-void ac_dump_reg(FILE *file, unsigned offset, uint32_t value,
-		 uint32_t field_mask)
+void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset,
+		 uint32_t value, uint32_t field_mask)
 {
 	int r, f;
 
@@ -196,7 +196,7 @@ static void ac_parse_set_reg_packet(FILE *f, unsigned count, unsigned reg_offset
 	}
 
 	for (i = 0; i < count; i++)
-		ac_dump_reg(f, reg + i*4, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, reg + i*4, ac_ib_get(ib), ~0);
 }
 
 static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
@@ -244,28 +244,28 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
 		ac_parse_set_reg_packet(f, count, SI_SH_REG_OFFSET, ib);
 		break;
 	case PKT3_ACQUIRE_MEM:
-		ac_dump_reg(f, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_030230_CP_COHER_SIZE_HI, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_0301E4_CP_COHER_BASE_HI, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_030230_CP_COHER_SIZE_HI, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_0301E4_CP_COHER_BASE_HI, ac_ib_get(ib), ~0);
 		print_named_value(f, "POLL_INTERVAL", ac_ib_get(ib), 16);
 		break;
 	case PKT3_SURFACE_SYNC:
 		if (ib->chip_class >= CIK) {
-			ac_dump_reg(f, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
-			ac_dump_reg(f, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
-			ac_dump_reg(f, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
+			ac_dump_reg(f, ib->chip_class, R_0301F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
+			ac_dump_reg(f, ib->chip_class, R_0301F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
+			ac_dump_reg(f, ib->chip_class, R_0301F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
 		} else {
-			ac_dump_reg(f, R_0085F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
-			ac_dump_reg(f, R_0085F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
-			ac_dump_reg(f, R_0085F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
+			ac_dump_reg(f, ib->chip_class, R_0085F0_CP_COHER_CNTL, ac_ib_get(ib), ~0);
+			ac_dump_reg(f, ib->chip_class, R_0085F4_CP_COHER_SIZE, ac_ib_get(ib), ~0);
+			ac_dump_reg(f, ib->chip_class, R_0085F8_CP_COHER_BASE, ac_ib_get(ib), ~0);
 		}
 		print_named_value(f, "POLL_INTERVAL", ac_ib_get(ib), 16);
 		break;
 	case PKT3_EVENT_WRITE: {
 		uint32_t event_dw = ac_ib_get(ib);
-		ac_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, event_dw,
+		ac_dump_reg(f, ib->chip_class, R_028A90_VGT_EVENT_INITIATOR, event_dw,
 			    S_028A90_EVENT_TYPE(~0));
 		print_named_value(f, "EVENT_INDEX", (event_dw >> 8) & 0xf, 4);
 		print_named_value(f, "INV_L2", (event_dw >> 20) & 0x1, 1);
@@ -277,7 +277,7 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
 	}
 	case PKT3_EVENT_WRITE_EOP: {
 		uint32_t event_dw = ac_ib_get(ib);
-		ac_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, event_dw,
+		ac_dump_reg(f, ib->chip_class, R_028A90_VGT_EVENT_INITIATOR, event_dw,
 			    S_028A90_EVENT_TYPE(~0));
 		print_named_value(f, "EVENT_INDEX", (event_dw >> 8) & 0xf, 4);
 		print_named_value(f, "TCL1_VOL_ACTION_ENA", (event_dw >> 12) & 0x1, 1);
@@ -297,7 +297,7 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
 	}
 	case PKT3_RELEASE_MEM: {
 		uint32_t event_dw = ac_ib_get(ib);
-		ac_dump_reg(f, R_028A90_VGT_EVENT_INITIATOR, event_dw,
+		ac_dump_reg(f, ib->chip_class, R_028A90_VGT_EVENT_INITIATOR, event_dw,
 			    S_028A90_EVENT_TYPE(~0));
 		print_named_value(f, "EVENT_INDEX", (event_dw >> 8) & 0xf, 4);
 		print_named_value(f, "TCL1_VOL_ACTION_ENA", (event_dw >> 12) & 0x1, 1);
@@ -328,52 +328,52 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
 		print_named_value(f, "POLL_INTERVAL", ac_ib_get(ib), 16);
 		break;
 	case PKT3_DRAW_INDEX_AUTO:
-		ac_dump_reg(f, R_030930_VGT_NUM_INDICES, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_030930_VGT_NUM_INDICES, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_0287F0_VGT_DRAW_INITIATOR, ac_ib_get(ib), ~0);
 		break;
 	case PKT3_DRAW_INDEX_2:
-		ac_dump_reg(f, R_028A78_VGT_DMA_MAX_SIZE, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_0287E8_VGT_DMA_BASE, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_0287E4_VGT_DMA_BASE_HI, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_030930_VGT_NUM_INDICES, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_0287F0_VGT_DRAW_INITIATOR, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_028A78_VGT_DMA_MAX_SIZE, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_0287E8_VGT_DMA_BASE, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_0287E4_VGT_DMA_BASE_HI, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_030930_VGT_NUM_INDICES, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_0287F0_VGT_DRAW_INITIATOR, ac_ib_get(ib), ~0);
 		break;
 	case PKT3_INDEX_TYPE:
-		ac_dump_reg(f, R_028A7C_VGT_DMA_INDEX_TYPE, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_028A7C_VGT_DMA_INDEX_TYPE, ac_ib_get(ib), ~0);
 		break;
 	case PKT3_NUM_INSTANCES:
-		ac_dump_reg(f, R_030934_VGT_NUM_INSTANCES, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_030934_VGT_NUM_INSTANCES, ac_ib_get(ib), ~0);
 		break;
 	case PKT3_WRITE_DATA:
-		ac_dump_reg(f, R_370_CONTROL, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_371_DST_ADDR_LO, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_372_DST_ADDR_HI, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_370_CONTROL, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_371_DST_ADDR_LO, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_372_DST_ADDR_HI, ac_ib_get(ib), ~0);
 		/* The payload is written automatically */
 		break;
 	case PKT3_CP_DMA:
-		ac_dump_reg(f, R_410_CP_DMA_WORD0, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_411_CP_DMA_WORD1, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_412_CP_DMA_WORD2, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_413_CP_DMA_WORD3, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_414_COMMAND, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_410_CP_DMA_WORD0, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_411_CP_DMA_WORD1, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_412_CP_DMA_WORD2, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_413_CP_DMA_WORD3, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_414_COMMAND, ac_ib_get(ib), ~0);
 		break;
 	case PKT3_DMA_DATA:
-		ac_dump_reg(f, R_500_DMA_DATA_WORD0, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_501_SRC_ADDR_LO, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_502_SRC_ADDR_HI, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_503_DST_ADDR_LO, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_504_DST_ADDR_HI, ac_ib_get(ib), ~0);
-		ac_dump_reg(f, R_414_COMMAND, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_500_DMA_DATA_WORD0, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_501_SRC_ADDR_LO, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_502_SRC_ADDR_HI, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_503_DST_ADDR_LO, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_504_DST_ADDR_HI, ac_ib_get(ib), ~0);
+		ac_dump_reg(f, ib->chip_class, R_414_COMMAND, ac_ib_get(ib), ~0);
 		break;
 	case PKT3_INDIRECT_BUFFER_SI:
 	case PKT3_INDIRECT_BUFFER_CONST:
 	case PKT3_INDIRECT_BUFFER_CIK: {
 		uint32_t base_lo_dw = ac_ib_get(ib);
-		ac_dump_reg(f, R_3F0_IB_BASE_LO, base_lo_dw, ~0);
+		ac_dump_reg(f, ib->chip_class, R_3F0_IB_BASE_LO, base_lo_dw, ~0);
 		uint32_t base_hi_dw = ac_ib_get(ib);
-		ac_dump_reg(f, R_3F1_IB_BASE_HI, base_hi_dw, ~0);
+		ac_dump_reg(f, ib->chip_class, R_3F1_IB_BASE_HI, base_hi_dw, ~0);
 		uint32_t control_dw = ac_ib_get(ib);
-		ac_dump_reg(f, R_3F2_CONTROL, control_dw, ~0);
+		ac_dump_reg(f, ib->chip_class, R_3F2_CONTROL, control_dw, ~0);
 
 		if (!ib->addr_callback)
 			break;
diff --git a/src/amd/common/ac_debug.h b/src/amd/common/ac_debug.h
index 277025d8b6..35e950014b 100644
--- a/src/amd/common/ac_debug.h
+++ b/src/amd/common/ac_debug.h
@@ -38,8 +38,8 @@
 
 typedef void *(*ac_debug_addr_callback)(void *data, uint64_t addr);
 
-void ac_dump_reg(FILE *file, unsigned offset, uint32_t value,
-		 uint32_t field_mask);
+void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset,
+		 uint32_t value, uint32_t field_mask);
 void ac_parse_ib_chunk(FILE *f, uint32_t *ib, int num_dw, const int *trace_ids,
 		       unsigned trace_id_count, enum chip_class chip_class,
 		       ac_debug_addr_callback addr_callback, void *addr_callback_data);
diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c
index 28c777d105..182574d653 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -231,7 +231,7 @@ static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
 	uint32_t value;
 
 	if (ws->read_registers(ws, offset, 1, &value))
-		ac_dump_reg(f, offset, value, ~0);
+		ac_dump_reg(f, sctx->b.chip_class, offset, value, ~0);
 }
 
 static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
@@ -564,6 +564,7 @@ struct si_log_chunk_desc_list {
 	const char *shader_name;
 	const char *elem_name;
 	slot_remap_func slot_remap;
+	enum chip_class chip_class;
 	unsigned element_dw_size;
 	unsigned num_elements;
 
@@ -596,37 +597,44 @@ si_log_chunk_desc_list_print(void *data, FILE *f)
 		switch (chunk->element_dw_size) {
 		case 4:
 			for (unsigned j = 0; j < 4; j++)
-				ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
+				ac_dump_reg(f, chunk->chip_class,
+					    R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
 					    gpu_list[j], 0xffffffff);
 			break;
 		case 8:
 			for (unsigned j = 0; j < 8; j++)
-				ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
+				ac_dump_reg(f, chunk->chip_class,
+					    R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
 					    gpu_list[j], 0xffffffff);
 
 			fprintf(f, COLOR_CYAN "    Buffer:" COLOR_RESET "\n");
 			for (unsigned j = 0; j < 4; j++)
-				ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
+				ac_dump_reg(f, chunk->chip_class,
+					    R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
 					    gpu_list[4+j], 0xffffffff);
 			break;
 		case 16:
 			for (unsigned j = 0; j < 8; j++)
-				ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
+				ac_dump_reg(f, chunk->chip_class,
+					    R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
 					    gpu_list[j], 0xffffffff);
 
 			fprintf(f, COLOR_CYAN "    Buffer:" COLOR_RESET "\n");
 			for (unsigned j = 0; j < 4; j++)
-				ac_dump_reg(f, R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
+				ac_dump_reg(f, chunk->chip_class,
+					    R_008F00_SQ_BUF_RSRC_WORD0 + j*4,
 					    gpu_list[4+j], 0xffffffff);
 
 			fprintf(f, COLOR_CYAN "    FMASK:" COLOR_RESET "\n");
 			for (unsigned j = 0; j < 8; j++)
-				ac_dump_reg(f, R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
+				ac_dump_reg(f, chunk->chip_class,
+					    R_008F10_SQ_IMG_RSRC_WORD0 + j*4,
 					    gpu_list[8+j], 0xffffffff);
 
 			fprintf(f, COLOR_CYAN "    Sampler state:" COLOR_RESET "\n");
 			for (unsigned j = 0; j < 4; j++)
-				ac_dump_reg(f, R_008F30_SQ_IMG_SAMP_WORD0 + j*4,
+				ac_dump_reg(f, chunk->chip_class,
+					    R_008F30_SQ_IMG_SAMP_WORD0 + j*4,
 					    gpu_list[12+j], 0xffffffff);
 			break;
 		}
@@ -646,7 +654,8 @@ static const struct u_log_chunk_type si_log_chunk_type_descriptor_list = {
 	.print = si_log_chunk_desc_list_print,
 };
 
-static void si_dump_descriptor_list(struct si_descriptors *desc,
+static void si_dump_descriptor_list(struct si_screen *screen,
+				    struct si_descriptors *desc,
 				    const char *shader_name,
 				    const char *elem_name,
 				    unsigned element_dw_size,
@@ -665,6 +674,7 @@ static void si_dump_descriptor_list(struct si_descriptors *desc,
 	chunk->element_dw_size = element_dw_size;
 	chunk->num_elements = num_elements;
 	chunk->slot_remap = slot_remap;
+	chunk->chip_class = screen->b.chip_class;
 
 	r600_resource_reference(&chunk->buf, desc->buffer);
 	chunk->gpu_list = desc->gpu_list;
@@ -715,24 +725,28 @@ static void si_dump_descriptors(struct si_context *sctx,
 	if (processor == PIPE_SHADER_VERTEX) {
 		assert(info); /* only CS may not have an info struct */
 
-		si_dump_descriptor_list(&sctx->vertex_buffers, name,
+		si_dump_descriptor_list(sctx->screen, &sctx->vertex_buffers, name,
 					" - Vertex buffer", 4, info->num_inputs,
 					si_identity, log);
 	}
 
-	si_dump_descriptor_list(&descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS],
+	si_dump_descriptor_list(sctx->screen,
+				&descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS],
 				name, " - Constant buffer", 4,
 				util_last_bit(enabled_constbuf),
 				si_get_constbuf_slot, log);
-	si_dump_descriptor_list(&descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS],
+	si_dump_descriptor_list(sctx->screen,
+				&descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS],
 				name, " - Shader buffer", 4,
 				util_last_bit(enabled_shaderbuf),
 				si_get_shaderbuf_slot, log);
-	si_dump_descriptor_list(&descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES],
+	si_dump_descriptor_list(sctx->screen,
+				&descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES],
 				name, " - Sampler", 16,
 				util_last_bit(enabled_samplers),
 				si_get_sampler_slot, log);
-	si_dump_descriptor_list(&descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES],
+	si_dump_descriptor_list(sctx->screen,
+				&descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES],
 				name, " - Image", 8,
 				util_last_bit(enabled_images),
 				si_get_image_slot, log);
@@ -1058,7 +1072,8 @@ void si_log_draw_state(struct si_context *sctx, struct u_log_context *log)
 	si_dump_gfx_shader(sctx, &sctx->gs_shader, log);
 	si_dump_gfx_shader(sctx, &sctx->ps_shader, log);
 
-	si_dump_descriptor_list(&sctx->descriptors[SI_DESCS_RW_BUFFERS],
+	si_dump_descriptor_list(sctx->screen,
+				&sctx->descriptors[SI_DESCS_RW_BUFFERS],
 				"", "RW buffers", 4, SI_NUM_RW_BUFFERS,
 				si_identity, log);
 	si_dump_gfx_descriptors(sctx, &sctx->vs_shader, log);