diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2017-07-05 23:33:13 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2017-07-17 10:50:39 -0400 |
| commit | facfab28fe47467d3adb3eae179075e4424c3b82 (patch) | |
| tree | e1455ff7da705d59e55c074bfbcadde07cd6f454 /src/gallium/drivers/radeonsi/si_pipe.c | |
| parent | 93391ac47895f2235a6102e7a923dfea3fb44fc4 (diff) | |
radeonsi/gfx9: add workarounds to avoid VGPR indexing completely
For inputs and outputs, indirect indexing is lowered by the GLSL compiler.
For temporaries, use alloca and disable the "promote-alloca" pass.
In the future, we could switch all codepaths to alloca permanently and
just rely on the "promote-alloca" pass.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_pipe.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index afb2bcbf07..8a4bc41a4e 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -141,8 +141,9 @@ si_create_llvm_target_machine(struct si_screen *sscreen) char features[256]; snprintf(features, sizeof(features), - "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s", + "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s", sscreen->b.chip_class >= GFX9 ? ",+xnack" : ",-xnack", + sscreen->llvm_has_working_vgpr_indexing ? "" : ",-promote-alloca", sscreen->b.debug_flags & DBG_SI_SCHED ? ",+si-scheduler" : ""); return LLVMCreateTargetMachine(ac_get_llvm_target(triple), triple, @@ -757,7 +758,6 @@ static int si_get_shader_param(struct pipe_screen* pscreen, /* Supported boolean features. */ case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: - case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: case PIPE_SHADER_CAP_INTEGERS: @@ -767,10 +767,18 @@ static int si_get_shader_param(struct pipe_screen* pscreen, return 1; case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: - /* TODO: Indirection of geometry shader input dimension is not - * handled yet - */ - return shader != PIPE_SHADER_GEOMETRY; + /* TODO: Indirect indexing of GS inputs is unimplemented. */ + return shader != PIPE_SHADER_GEOMETRY && + (sscreen->llvm_has_working_vgpr_indexing || + /* TCS and TES load inputs directly from LDS or + * offchip memory, so indirect indexing is trivial. */ + shader == PIPE_SHADER_TESS_CTRL || + shader == PIPE_SHADER_TESS_EVAL); + + case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: + return sscreen->llvm_has_working_vgpr_indexing || + /* TCS stores outputs directly to memory. */ + shader == PIPE_SHADER_TESS_CTRL; /* Unsupported boolean features. */ case PIPE_SHADER_CAP_SUBROUTINES: @@ -1006,6 +1014,11 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, sscreen->b.family <= CHIP_POLARIS12) || sscreen->b.family == CHIP_VEGA10 || sscreen->b.family == CHIP_RAVEN; + /* While it would be nice not to have this flag, we are constrained + * by the reality that LLVM 5.0 doesn't have working VGPR indexing + * on GFX9. + */ + sscreen->llvm_has_working_vgpr_indexing = sscreen->b.chip_class <= VI; sscreen->b.has_cp_dma = true; sscreen->b.has_streamout = true; |