diff options
| author | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2016-07-20 10:33:44 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2017-03-30 14:44:33 +0200 |
| commit | a136926eef082963e0025ac5e44eff9f2d931663 (patch) | |
| tree | 1a08949877f061c7cb8d6b7c9a82cf9d4ab011d7 /src/amd/addrlib | |
| parent | 48bf5d0800ef394879a5a229ac2ae5a15a4c75e5 (diff) | |
amdgpu/addrlib: Seperate 2 dcc related workarounds by different flags
1) dccCompatible for padding MSAA surface to support fast clear
2) dccPipeWorkaround for padding surface to support dcc
Diffstat (limited to 'src/amd/addrlib')
| -rw-r--r-- | src/amd/addrlib/addrinterface.h | 6 | ||||
| -rw-r--r-- | src/amd/addrlib/core/addrlib1.cpp | 2 | ||||
| -rw-r--r-- | src/amd/addrlib/r800/ciaddrlib.cpp | 4 |
3 files changed, 9 insertions, 3 deletions
diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h index d2d6d94698..14dff66942 100644 --- a/src/amd/addrlib/addrinterface.h +++ b/src/amd/addrlib/addrinterface.h @@ -504,7 +504,11 @@ typedef union _ADDR_SURFACE_FLAGS UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable UINT_32 dispTileType : 1; ///< NI: force display Tiling for 128 bit shared resoruce - UINT_32 dccCompatible : 1; ///< VI: whether to support dcc fast clear + UINT_32 dccCompatible : 1; ///< VI: whether to make MSAA surface support dcc fast clear + UINT_32 dccPipeWorkaround : 1; ///< VI: whether to workaround the HW limit that + /// dcc can't be enabled if pipe config of tile mode + /// is different from that of ASIC, this flag + /// is address lib internal flag, client should ignore it UINT_32 czDispCompatible : 1; ///< SI+: CZ family has a HW bug needs special alignment. /// This flag indicates we need to follow the /// alignment with CZ families or other ASICs under diff --git a/src/amd/addrlib/core/addrlib1.cpp b/src/amd/addrlib/core/addrlib1.cpp index 809bca2391..2d640cf65f 100644 --- a/src/amd/addrlib/core/addrlib1.cpp +++ b/src/amd/addrlib/core/addrlib1.cpp @@ -336,6 +336,8 @@ ADDR_E_RETURNCODE Lib::ComputeSurfaceInfo( if (returnCode == ADDR_OK) { + localIn.flags.dccPipeWorkaround = localIn.flags.dccCompatible; + if (localIn.tileMode == ADDR_TM_UNKNOWN) { // HWL layer may override tile mode if necessary diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp index 5ccc5da419..1f7bb189fe 100644 --- a/src/amd/addrlib/r800/ciaddrlib.cpp +++ b/src/amd/addrlib/r800/ciaddrlib.cpp @@ -979,7 +979,7 @@ VOID CiLib::HwlOptimizeTileMode( if (pInOut->maxBaseAlign != 0) { - pInOut->flags.dccCompatible = FALSE; + pInOut->flags.dccPipeWorkaround = FALSE; } } @@ -2095,7 +2095,7 @@ VOID CiLib::HwlComputeSurfaceAlignmentsMacroTiled( // P4. In theory, all asics that have such switching should be patched but we now only know what // to pad for Fiji. if ((m_settings.isFiji == TRUE) && - (flags.dccCompatible == TRUE) && + (flags.dccPipeWorkaround == TRUE) && (flags.prt == FALSE) && (mipLevel == 0) && (tileMode == ADDR_TM_PRT_TILED_THIN1) && |