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authorNicolai Hähnle <nicolai.haehnle@amd.com>2016-10-31 11:36:35 +0100
committerNicolai Hähnle <nicolai.haehnle@amd.com>2016-11-02 12:36:26 +0100
commit9ee519787ae1ddc4fbfe1ca68ba69d8b89f70d98 (patch)
tree212068e0012cb36e4ddb688f5140a32616f5156e
parent1c3caf5bbb7acba935d5b81fb4f96ee9abd08668 (diff)
radeonsi: fix signature of export intrinsic in VS epilog
The incompatible signature becomes an issue when the VS epilog gets merged with the main vertex shader at the IR level.
-rw-r--r--src/gallium/drivers/radeonsi/si_shader.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 2b8c168a1f..887174257a 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -7114,9 +7114,9 @@ static bool si_compile_vs_epilog(struct si_screen *sscreen,
args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
args[5] = LLVMGetParam(ctx.main_fn,
VS_EPILOG_PRIMID_LOC); /* X */
- args[6] = uint->undef; /* Y */
- args[7] = uint->undef; /* Z */
- args[8] = uint->undef; /* W */
+ args[6] = base->undef; /* Y */
+ args[7] = base->undef; /* Z */
+ args[8] = base->undef; /* W */
lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
LLVMVoidTypeInContext(base->gallivm->context),