diff options
| author | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2016-01-19 14:59:22 -0500 |
|---|---|---|
| committer | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2016-01-22 11:59:50 -0500 |
| commit | 843855bbf0da2204ce536623ba957bfa83fdbd52 (patch) | |
| tree | dbf3493501dedbf918e84f04d076778c9cba6cc9 | |
| parent | 3e640c256aa1bf0d3b2e14ddc23a8d84caddcb92 (diff) | |
radeonsi: fix discard-only fragment shaders (v2)
When a fragment shader is used that has no outputs but does conditional
discard (KILL_IF), all fragments are killed without this patch.
By comparing various register settings, my conclusion is that the exec mask
is either not properly forwarded to the DB by NULL exports or ends up being
unused, at least when there is _only_ a NULL export (the ISA documentation
claims that NULL exports can be used to override a previously exported exec
mask).
Of the various approaches I have tried to work around the problem, this one
seems to be the least invasive one.
v2: take discard by alpha test into account as well
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93761
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_shaders.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 79f2335b9b..fae804c6ca 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -438,6 +438,7 @@ static void si_shader_ps(struct si_shader *shader) unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); uint64_t va; bool has_centroid; + bool writes_execmask; pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state); @@ -492,10 +493,13 @@ static void si_shader_ps(struct si_shader *shader) si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl); si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control); + writes_execmask = info->uses_kill || + shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS; si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, info->writes_samplemask ? V_028710_SPI_SHADER_32_ABGR : info->writes_stencil ? V_028710_SPI_SHADER_32_GR : info->writes_z ? V_028710_SPI_SHADER_32_R : + (writes_execmask && !info->num_outputs) ? V_028710_SPI_SHADER_32_R : V_028710_SPI_SHADER_ZERO); si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format); |